[J-u-boot.git] / include / configs / m53evk.h

/*
 * Aries M53 configuration
 * Copyright (C) 2012-2013 Marek Vasut <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __M53EVK_CONFIG_H__
#define __M53EVK_CONFIG_H__

#define CONFIG_MXC_GPIO

#include <asm/arch/imx-regs.h>

#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		2
#define PHYS_SDRAM_1			CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2			CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE			(gd->ram_size)
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	0x70000000
#define CONFIG_SYS_MEMTEST_END		0x8ff00000

#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_SYS_TEXT_BASE		0x71000000

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */

/*
 * Serial Driver
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART2_BASE
#define CONFIG_CONS_INDEX		1

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1
#endif

/*
 * NAND
 */
#define CONFIG_ENV_SIZE			(16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_USE_FLASH_BBT

/* Environment is in NAND */
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_RANGE		(4 * CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OFFSET		(8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
#define CONFIG_ENV_OFFSET_REDUND	\
		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT			"nand0=mxc_nand"
#define MTDPARTS_DEFAULT			\
	"mtdparts=mxc_nand:"			\
		"1024k(u-boot),"		\
		"512k(env1),"			\
		"512k(env2),"			\
		"14m(boot),"			\
		"240m(data),"			\
		"-@2048k(UBI)"
#endif

/*
 * Ethernet on SOC (FEC)
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE			FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR		0x0
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE		RMII
#define CONFIG_ETHPRIME			"FEC0"
#endif

/*
 * I2C
 */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
#endif

/*
 * RTC
 */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000
#endif

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT		1
#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS		0
#endif

/*
 * SATA
 */
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif

/*
 * LCD
 */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
#define CONFIG_IPUV3_CLK		200000000
#endif

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTFILE		"fitImage"
#define CONFIG_LOADADDR		0x70800000
#define CONFIG_BOOTCOMMAND	"run mmc_mmc"
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

/*
 * NAND SPL
 */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
#define CONFIG_SPL_TEXT_BASE		0x70008000
#define CONFIG_SPL_PAD_TO		0x8000
#define CONFIG_SPL_STACK		0x70004000

#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0

/*
 * Extra Environments
 */
#define CONFIG_PREBOOT		"run try_bootscript"
#define CONFIG_HOSTNAME		m53evk

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"consdev=ttymxc1\0"						\
	"baudrate=115200\0"						\
	"bootscript=boot.scr\0"						\
	"bootdev=/dev/mmcblk0p1\0"					\
	"rootdev=/dev/mmcblk0p2\0"					\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0"		\
	"kernel_addr_r=0x72000000\0"					\
	"addcons="							\
		"setenv bootargs ${bootargs} "				\
		"console=${consdev},${baudrate}\0"			\
	"addip="							\
		"setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
			"${netmask}:${hostname}:${netdev}:off\0"	\
	"addmisc="							\
		"setenv bootargs ${bootargs} ${miscargs}\0"		\
	"adddfltmtd="							\
		"if test \"x${mtdparts}\" == \"x\" ; then "		\
			"mtdparts default ; "				\
		"fi\0"							\
	"addmtd="							\
		"run adddfltmtd ; "					\
		"setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addargs=run addcons addmtd addmisc\0"				\
	"mmcload="							\
		"mmc rescan ; "						\
		"load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"		\
	"ubiload="							\
		"ubi part UBI ; ubifsmount ubi0:rootfs ; "		\
		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
	"netload="							\
		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
	"miscargs=nohlt panic=1\0"					\
	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0"		\
	"ubiargs="							\
		"setenv bootargs ubi.mtd=5 "				\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"nfsargs="							\
		"setenv bootargs root=/dev/nfs rw "			\
			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
	"mmc_mmc="							\
		"run mmcload mmcargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"mmc_ubi="							\
		"run mmcload ubiargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"mmc_nfs="							\
		"run mmcload nfsargs addip addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"ubi_mmc="							\
		"run ubiload mmcargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"ubi_ubi="							\
		"run ubiload ubiargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"ubi_nfs="							\
		"run ubiload nfsargs addip addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"net_mmc="							\
		"run netload mmcargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"net_ubi="							\
		"run netload ubiargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs="							\
		"run netload nfsargs addip addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"try_bootscript="						\
		"mmc rescan;"						\
		"if test -e mmc 0:1 ${bootscript} ; then "		\
		"if load mmc 0:1 ${kernel_addr_r} ${bootscript};"	\
		"then ; "						\
			"echo Running bootscript... ; "			\
			"source ${kernel_addr_r} ; "			\
		"fi ; "							\
		"fi\0"

#endif	/* __M53EVK_CONFIG_H__ */
Commit	Line	Data
0f83b365	1	/*
2a4058c2	2	* Aries M53 configuration
0f83b365 MV	3	* Copyright (C) 2012-2013 Marek Vasut <[email protected]>
0f83b365 MV	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
0f83b365 MV	6	*/
	7
	8	#ifndef __M53EVK_CONFIG_H__
	9	#define __M53EVK_CONFIG_H__
	10
0f83b365	11	#define CONFIG_MXC_GPIO
0f83b365 MV	12
	13	#include <asm/arch/imx-regs.h>
	14
0f83b365	15	#define CONFIG_REVISION_TAG
18fb0e3c	16	#define CONFIG_SYS_FSL_CLK
0f83b365	17
62d3c2d6 MV	18	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
62d3c2d6 MV	19
0f83b365 MV	20	/*
	21	* Memory configurations
	22	*/
	23	#define CONFIG_NR_DRAM_BANKS 2
	24	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
97334c66	25	#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
0f83b365	26	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
97334c66 MV	27	#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
97334c66 MV	28	#define PHYS_SDRAM_SIZE (gd->ram_size)
0f83b365 MV	29	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
0f83b365 MV	30	#define CONFIG_SYS_MEMTEST_START 0x70000000
2f844e76	31	#define CONFIG_SYS_MEMTEST_END 0x8ff00000
0f83b365 MV	32
	33	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
	34	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
	35	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
	36
	37	#define CONFIG_SYS_INIT_SP_OFFSET \
	38	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	39	#define CONFIG_SYS_INIT_SP_ADDR \
	40	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	41
	42	#define CONFIG_SYS_TEXT_BASE 0x71000000
	43
	44	/*
	45	* U-Boot general configurations
	46	*/
	47	#define CONFIG_SYS_LONGHELP
0f83b365	48	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
0f83b365 MV	49	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	50	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	51	/* Boot argument buffer size */
0f83b365 MV	52	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
0f83b365 MV	53	#define CONFIG_CMDLINE_EDITING /* Command history etc */
0f83b365 MV	54
	55	/*
	56	* Serial Driver
	57	*/
	58	#define CONFIG_MXC_UART
	59	#define CONFIG_MXC_UART_BASE UART2_BASE
	60	#define CONFIG_CONS_INDEX 1
0f83b365 MV	61
	62	/*
	63	* MMC Driver
	64	*/
	65	#ifdef CONFIG_CMD_MMC
0f83b365 MV	66	#define CONFIG_FSL_ESDHC
	67	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	68	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	69	#endif
	70
	71	/*
	72	* NAND
	73	*/
	74	#define CONFIG_ENV_SIZE (16 * 1024)
	75	#ifdef CONFIG_CMD_NAND
	76	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	77	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
	78	#define CONFIG_NAND_MXC
	79	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
	80	#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
	81	#define CONFIG_SYS_NAND_LARGEPAGE
	82	#define CONFIG_MXC_NAND_HWECC
	83	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	84
	85	/* Environment is in NAND */
0f83b365 MV	86	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
0f83b365 MV	87	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
fc23b530 MV	88	#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
fc23b530 MV	89	#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
0f83b365 MV	90	#define CONFIG_ENV_OFFSET_REDUND \
	91	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
	92
0f83b365 MV	93	#define CONFIG_MTD_DEVICE
0f83b365 MV	94	#define CONFIG_MTD_PARTITIONS
8331273c	95	#define MTDIDS_DEFAULT "nand0=mxc_nand"
0f83b365	96	#define MTDPARTS_DEFAULT \
8331273c	97	"mtdparts=mxc_nand:" \
fc23b530 MV	98	"1024k(u-boot)," \
	99	"512k(env1)," \
	100	"512k(env2)," \
	101	"14m(boot)," \
	102	"240m(data)," \
	103	"-@2048k(UBI)"
0f83b365 MV	104	#endif
	105
	106	/*
	107	* Ethernet on SOC (FEC)
	108	*/
	109	#ifdef CONFIG_CMD_NET
	110	#define CONFIG_FEC_MXC
	111	#define IMX_FEC_BASE FEC_BASE_ADDR
	112	#define CONFIG_FEC_MXC_PHYADDR 0x0
	113	#define CONFIG_MII
	114	#define CONFIG_DISCOVER_PHY
	115	#define CONFIG_FEC_XCV_TYPE RMII
85d8a5fc	116	#define CONFIG_ETHPRIME "FEC0"
0f83b365 MV	117	#endif
	118
	119	/*
	120	* I2C
	121	*/
	122	#ifdef CONFIG_CMD_I2C
b089d039	123	#define CONFIG_SYS_I2C
b089d039	124	#define CONFIG_SYS_I2C_MXC
03544c66 AA	125	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	126	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	127	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
25fe0572	128	#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
0f83b365 MV	129	#endif
	130
	131	/*
	132	* RTC
	133	*/
	134	#ifdef CONFIG_CMD_DATE
	135	#define CONFIG_RTC_M41T62
	136	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	137	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	138	#endif
	139
	140	/*
	141	* USB
	142	*/
	143	#ifdef CONFIG_CMD_USB
0f83b365	144	#define CONFIG_USB_EHCI_MX5
0f83b365	145	#define CONFIG_USB_ETHER_ASIX
a743415f	146	#define CONFIG_USB_ETHER_MCS7830
0f83b365 MV	147	#define CONFIG_USB_ETHER_SMSC95XX
	148	#define CONFIG_MXC_USB_PORT 1
	149	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	150	#define CONFIG_MXC_USB_FLAGS 0
	151	#endif
	152
	153	/*
	154	* SATA
	155	*/
	156	#ifdef CONFIG_CMD_SATA
	157	#define CONFIG_DWC_AHSATA
	158	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	159	#define CONFIG_DWC_AHSATA_PORT_ID 0
	160	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
	161	#define CONFIG_LBA48
	162	#define CONFIG_LIBATA
	163	#endif
	164
502a710f MV	165	/*
	166	* LCD
	167	*/
	168	#ifdef CONFIG_VIDEO
	169	#define CONFIG_VIDEO_IPUV3
502a710f	170	#define CONFIG_VIDEO_BMP_RLE8
62d3c2d6	171	#define CONFIG_VIDEO_BMP_GZIP
502a710f	172	#define CONFIG_SPLASH_SCREEN
62d3c2d6 MV	173	#define CONFIG_SPLASHIMAGE_GUARD
62d3c2d6 MV	174	#define CONFIG_SPLASH_SCREEN_ALIGN
502a710f MV	175	#define CONFIG_BMP_16BPP
502a710f MV	176	#define CONFIG_VIDEO_LOGO
62d3c2d6 MV	177	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
62d3c2d6 MV	178	#define CONFIG_IPUV3_CLK 200000000
502a710f MV	179	#endif
502a710f MV	180
0f83b365 MV	181	/*
	182	* Boot Linux
	183	*/
	184	#define CONFIG_CMDLINE_TAG
	185	#define CONFIG_INITRD_TAG
	186	#define CONFIG_REVISION_TAG
	187	#define CONFIG_SETUP_MEMORY_TAGS
85d8a5fc	188	#define CONFIG_BOOTFILE "fitImage"
0f83b365	189	#define CONFIG_LOADADDR 0x70800000
85d8a5fc	190	#define CONFIG_BOOTCOMMAND "run mmc_mmc"
0f83b365	191	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
0f83b365 MV	192
	193	/*
	194	* NAND SPL
	195	*/
0f83b365 MV	196	#define CONFIG_SPL_FRAMEWORK
0f83b365 MV	197	#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
0f83b365 MV	198	#define CONFIG_SPL_TEXT_BASE 0x70008000
	199	#define CONFIG_SPL_PAD_TO 0x8000
	200	#define CONFIG_SPL_STACK 0x70004000
0f83b365 MV	201
	202	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	203	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	204	#define CONFIG_SYS_NAND_OOBSIZE 64
	205	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	206	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	207	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	208
85d8a5fc LR	209	/*
	210	* Extra Environments
	211	*/
	212	#define CONFIG_PREBOOT "run try_bootscript"
	213	#define CONFIG_HOSTNAME m53evk
	214
	215	#define CONFIG_EXTRA_ENV_SETTINGS \
	216	"consdev=ttymxc1\0" \
	217	"baudrate=115200\0" \
	218	"bootscript=boot.scr\0" \
	219	"bootdev=/dev/mmcblk0p1\0" \
	220	"rootdev=/dev/mmcblk0p2\0" \
	221	"netdev=eth0\0" \
	222	"rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
	223	"kernel_addr_r=0x72000000\0" \
	224	"addcons=" \
	225	"setenv bootargs ${bootargs} " \
	226	"console=${consdev},${baudrate}\0" \
	227	"addip=" \
	228	"setenv bootargs ${bootargs} " \
	229	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	230	"${netmask}:${hostname}:${netdev}:off\0" \
	231	"addmisc=" \
	232	"setenv bootargs ${bootargs} ${miscargs}\0" \
	233	"adddfltmtd=" \
	234	"if test \"x${mtdparts}\" == \"x\" ; then " \
	235	"mtdparts default ; " \
	236	"fi\0" \
	237	"addmtd=" \
	238	"run adddfltmtd ; " \
	239	"setenv bootargs ${bootargs} ${mtdparts}\0" \
	240	"addargs=run addcons addmtd addmisc\0" \
	241	"mmcload=" \
	242	"mmc rescan ; " \
febae49a	243	"load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
85d8a5fc LR	244	"ubiload=" \
	245	"ubi part UBI ; ubifsmount ubi0:rootfs ; " \
	246	"ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
	247	"netload=" \
	248	"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
	249	"miscargs=nohlt panic=1\0" \
	250	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
	251	"ubiargs=" \
	252	"setenv bootargs ubi.mtd=5 " \
	253	"root=ubi0:rootfs rootfstype=ubifs\0" \
	254	"nfsargs=" \
	255	"setenv bootargs root=/dev/nfs rw " \
	256	"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
	257	"mmc_mmc=" \
	258	"run mmcload mmcargs addargs ; " \
	259	"bootm ${kernel_addr_r}\0" \
	260	"mmc_ubi=" \
	261	"run mmcload ubiargs addargs ; " \
	262	"bootm ${kernel_addr_r}\0" \
	263	"mmc_nfs=" \
	264	"run mmcload nfsargs addip addargs ; " \
	265	"bootm ${kernel_addr_r}\0" \
	266	"ubi_mmc=" \
	267	"run ubiload mmcargs addargs ; " \
	268	"bootm ${kernel_addr_r}\0" \
	269	"ubi_ubi=" \
	270	"run ubiload ubiargs addargs ; " \
	271	"bootm ${kernel_addr_r}\0" \
	272	"ubi_nfs=" \
	273	"run ubiload nfsargs addip addargs ; " \
	274	"bootm ${kernel_addr_r}\0" \
	275	"net_mmc=" \
	276	"run netload mmcargs addargs ; " \
	277	"bootm ${kernel_addr_r}\0" \
	278	"net_ubi=" \
	279	"run netload ubiargs addargs ; " \
	280	"bootm ${kernel_addr_r}\0" \
	281	"net_nfs=" \
	282	"run netload nfsargs addip addargs ; " \
	283	"bootm ${kernel_addr_r}\0" \
	284	"try_bootscript=" \
	285	"mmc rescan;" \
14b256e5	286	"if test -e mmc 0:1 ${bootscript} ; then " \
febae49a	287	"if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
252499e6 MV	288	"then ; " \
	289	"echo Running bootscript... ; " \
	290	"source ${kernel_addr_r} ; " \
14b256e5	291	"fi ; " \
85d8a5fc LR	292	"fi\0"
85d8a5fc LR	293
0f83b365	294	#endif /* __M53EVK_CONFIG_H__ */