projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| c4d0e811 SL |
2 | /* |
| 3 | * Copyright 2011-2013 Freescale Semiconductor, Inc. | |
| 34f39ce8 | 4 | * Copyright 2020-2021 NXP |
| c4d0e811 SL |
5 | */ |
| 6 | ||
| 7 | /* | |
| 254887a5 | 8 | * T2080/T2081 QDS board configuration file |
| c4d0e811 SL |
9 | */ |
| 10 | ||
| 254887a5 SL |
11 | #ifndef __T208xQDS_H |
| 12 | #define __T208xQDS_H | |
| c4d0e811 | 13 | |
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| c4d0e811 | 16 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
| 0f3d80e9 | 17 | #if defined(CONFIG_ARCH_T2080) |
| c4d0e811 SL |
18 | #define CONFIG_FSL_SATA_V2 |
| 19 | #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ | |
| 20 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| 21 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
| 254887a5 | 22 | #endif |
| c4d0e811 SL |
23 | |
| 24 | /* High Level Configuration Options */ | |
| c4d0e811 | 25 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| c4d0e811 SL |
26 | #define CONFIG_ENABLE_36BIT_PHYS |
| 27 | ||
| c4d0e811 | 28 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
| 51370d56 | 29 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| c4d0e811 SL |
30 | |
| 31 | #ifdef CONFIG_RAMBOOT_PBL | |
| b19e288f | 32 | #define CONFIG_SPL_FLUSH_IMAGE |
| b19e288f SL |
33 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 34 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 35 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 36 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 37 | #ifdef CONFIG_SPL_BUILD | |
| 38 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 39 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 40 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| b19e288f SL |
41 | #endif |
| 42 | ||
| 88718be3 | 43 | #ifdef CONFIG_MTD_RAW_NAND |
| b19e288f SL |
44 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 45 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
| 46 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| ab37df9d T |
47 | #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR |
| 48 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 49 | #endif | |
| b19e288f SL |
50 | #endif |
| 51 | ||
| 52 | #ifdef CONFIG_SPIFLASH | |
| 53 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| b19e288f SL |
54 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 55 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| 56 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) | |
| 57 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) | |
| 58 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) | |
| b19e288f SL |
59 | #ifndef CONFIG_SPL_BUILD |
| 60 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c4d0e811 | 61 | #endif |
| b19e288f SL |
62 | #endif |
| 63 | ||
| 64 | #ifdef CONFIG_SDCARD | |
| 65 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| b19e288f SL |
66 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 67 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) | |
| 68 | #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) | |
| 69 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
| b19e288f SL |
70 | #ifndef CONFIG_SPL_BUILD |
| 71 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 72 | #endif | |
| b19e288f SL |
73 | #endif |
| 74 | ||
| 75 | #endif /* CONFIG_RAMBOOT_PBL */ | |
| c4d0e811 SL |
76 | |
| 77 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
| 78 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 79 | /* Set 1M boot space */ | |
| 80 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
| 81 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
| 82 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
| 83 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| c4d0e811 SL |
84 | #endif |
| 85 | ||
| c4d0e811 SL |
86 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 87 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 88 | #endif | |
| 89 | ||
| 90 | /* | |
| 91 | * These can be toggled for performance analysis, otherwise use default. | |
| 92 | */ | |
| 93 | #define CONFIG_SYS_CACHE_STASHING | |
| c4d0e811 | 94 | #ifdef CONFIG_DDR_ECC |
| c4d0e811 SL |
95 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 96 | #endif | |
| 97 | ||
| c4d0e811 SL |
98 | /* |
| 99 | * Config the L3 Cache as L3 SRAM | |
| 100 | */ | |
| b19e288f SL |
101 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 102 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
| 103 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
| a09fea1d | 104 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
| b19e288f SL |
105 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 106 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
| 107 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
| c4d0e811 SL |
108 | |
| 109 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 110 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 111 | ||
| 112 | /* EEPROM */ | |
| c4d0e811 SL |
113 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 114 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| c4d0e811 SL |
115 | |
| 116 | /* | |
| 117 | * DDR Setup | |
| 118 | */ | |
| 119 | #define CONFIG_VERY_BIG_RAM | |
| 120 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 121 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| c4d0e811 SL |
122 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 123 | #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ | |
| 124 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 125 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| 126 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
| 127 | #define CTRL_INTLV_PREFERED cacheline | |
| 128 | ||
| 129 | /* | |
| 130 | * IFC Definitions | |
| 131 | */ | |
| 132 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
| 133 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 134 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 135 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 136 | + 0x8000000) | \ | |
| 137 | CSPR_PORT_SIZE_16 | \ | |
| 138 | CSPR_MSEL_NOR | \ | |
| 139 | CSPR_V) | |
| 140 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
| 141 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 142 | CSPR_PORT_SIZE_16 | \ | |
| 143 | CSPR_MSEL_NOR | \ | |
| 144 | CSPR_V) | |
| 145 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 146 | /* NOR Flash Timing Params */ | |
| 147 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 148 | ||
| 149 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 150 | FTIM0_NOR_TEADC(0x5) | \ | |
| 151 | FTIM0_NOR_TEAHC(0x5)) | |
| 152 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 153 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 154 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 155 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 156 | FTIM2_NOR_TCH(0x4) | \ | |
| 157 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 158 | FTIM2_NOR_TWP(0x1c)) | |
| 159 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 160 | ||
| 161 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 162 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 163 | ||
| c4d0e811 SL |
164 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 165 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 166 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 167 | ||
| 168 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 169 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 170 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 171 | ||
| c4d0e811 SL |
172 | #define QIXIS_BASE 0xffdf0000 |
| 173 | #define QIXIS_LBMAP_SWITCH 6 | |
| 174 | #define QIXIS_LBMAP_MASK 0x0f | |
| 175 | #define QIXIS_LBMAP_SHIFT 0 | |
| 176 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 177 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 46caebc1 YS |
178 | #define QIXIS_LBMAP_NAND 0x09 |
| 179 | #define QIXIS_LBMAP_SD 0x00 | |
| 180 | #define QIXIS_RCW_SRC_NAND 0x104 | |
| 181 | #define QIXIS_RCW_SRC_SD 0x040 | |
| c4d0e811 SL |
182 | #define QIXIS_RST_CTL_RESET 0x83 |
| 183 | #define QIXIS_RST_FORCE_MEM 0x1 | |
| 184 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 185 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 186 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 187 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) | |
| 188 | ||
| 189 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
| 190 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 191 | | CSPR_PORT_SIZE_8 \ | |
| 192 | | CSPR_MSEL_GPCM \ | |
| 193 | | CSPR_V) | |
| 088d52cf | 194 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) |
| c4d0e811 SL |
195 | #define CONFIG_SYS_CSOR3 0x0 |
| 196 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 197 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 198 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 199 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 200 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 201 | FTIM1_GPCM_TRAD(0x3f)) | |
| 202 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| 6b7679c8 | 203 | FTIM2_GPCM_TCH(0x8) | \ |
| c4d0e811 SL |
204 | FTIM2_GPCM_TWP(0x1f)) |
| 205 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 206 | ||
| 207 | /* NAND Flash on IFC */ | |
| c4d0e811 SL |
208 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 209 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 210 | ||
| 211 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 212 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 213 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 214 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 215 | | CSPR_V) | |
| 216 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 217 | ||
| 218 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 219 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 220 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 221 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
| 222 | | CSOR_NAND_PGS_2K /* Page Size = 2K */\ | |
| 223 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ | |
| 224 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 225 | ||
| c4d0e811 SL |
226 | /* ONFI NAND Flash mode0 Timing Params */ |
| 227 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 228 | FTIM0_NAND_TWP(0x18) | \ | |
| 229 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 230 | FTIM0_NAND_TWH(0x0a)) | |
| 231 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 232 | FTIM1_NAND_TWBE(0x39) | \ | |
| 233 | FTIM1_NAND_TRR(0x0e) | \ | |
| 234 | FTIM1_NAND_TRP(0x18)) | |
| 235 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 236 | FTIM2_NAND_TREH(0x0a) | \ | |
| 237 | FTIM2_NAND_TWHRE(0x1e)) | |
| 238 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 239 | ||
| 240 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 241 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 242 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| c4d0e811 | 243 | |
| 88718be3 | 244 | #if defined(CONFIG_MTD_RAW_NAND) |
| c4d0e811 SL |
245 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 246 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 247 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 248 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 249 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 250 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 251 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 252 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 22cbf964 SL |
253 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 254 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 255 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 256 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 257 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 258 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 259 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 260 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 261 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 262 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| c4d0e811 SL |
263 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 264 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 265 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 266 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 267 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 268 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 269 | #else | |
| 270 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 271 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 272 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 273 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 274 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 275 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 276 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 277 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 22cbf964 SL |
278 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 279 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 280 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 281 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 282 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 283 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 284 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 285 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| c4d0e811 SL |
286 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 287 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 288 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 289 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 290 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 291 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 292 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 293 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 294 | #endif | |
| c4d0e811 SL |
295 | |
| 296 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 297 | #define CONFIG_SYS_RAMBOOT | |
| 298 | #endif | |
| 299 | ||
| c4d0e811 SL |
300 | #define CONFIG_HWCONFIG |
| 301 | ||
| 302 | /* define to use L1 as initial stack */ | |
| 303 | #define CONFIG_L1_INIT_RAM | |
| 304 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 305 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 306 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 307 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| c4d0e811 SL |
308 | /* The assembler doesn't like typecast */ |
| 309 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 310 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 311 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 312 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 313 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 314 | GENERATED_GBL_DATA_SIZE) | |
| 315 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 9307cbab | 316 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| c4d0e811 SL |
317 | |
| 318 | /* | |
| 319 | * Serial Port | |
| 320 | */ | |
| c4d0e811 SL |
321 | #define CONFIG_SYS_NS16550_SERIAL |
| 322 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 323 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 324 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 325 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 326 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 327 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 328 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 329 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 330 | ||
| c4d0e811 SL |
331 | /* |
| 332 | * I2C | |
| 333 | */ | |
| 8e4be6df | 334 | |
| c4d0e811 SL |
335 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
| 336 | #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ | |
| 337 | #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ | |
| 338 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 339 | ||
| 3ad2737e YZ |
340 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 341 | ||
| 342 | /* Voltage monitor on channel 2*/ | |
| 343 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
| 344 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
| 345 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
| 346 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
| 347 | ||
| 3ad2737e YZ |
348 | /* The lowest and highest voltage allowed for T208xQDS */ |
| 349 | #define VDD_MV_MIN 819 | |
| 350 | #define VDD_MV_MAX 1212 | |
| c4d0e811 SL |
351 | |
| 352 | /* | |
| 353 | * RapidIO | |
| 354 | */ | |
| 355 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
| 356 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
| 357 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
| 358 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
| 359 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
| 360 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
| 361 | /* | |
| 362 | * for slave u-boot IMAGE instored in master memory space, | |
| 363 | * PHYS must be aligned based on the SIZE | |
| 364 | */ | |
| e4911815 LG |
365 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 366 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
| 367 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
| 368 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
| c4d0e811 SL |
369 | /* |
| 370 | * for slave UCODE and ENV instored in master memory space, | |
| 371 | * PHYS must be aligned based on the SIZE | |
| 372 | */ | |
| e4911815 | 373 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| c4d0e811 SL |
374 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 375 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
| 376 | ||
| 377 | /* slave core release by master*/ | |
| 378 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
| 379 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
| 380 | ||
| 381 | /* | |
| 382 | * SRIO_PCIE_BOOT - SLAVE | |
| 383 | */ | |
| 384 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 385 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
| 386 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
| 387 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
| 388 | #endif | |
| 389 | ||
| 390 | /* | |
| 391 | * eSPI - Enhanced SPI | |
| 392 | */ | |
| c4d0e811 SL |
393 | |
| 394 | /* | |
| 395 | * General PCI | |
| 396 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 397 | */ | |
| b38eaec5 RD |
398 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 399 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 400 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 401 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| c4d0e811 SL |
402 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 403 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| c4d0e811 | 404 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| c4d0e811 | 405 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| c4d0e811 | 406 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| c4d0e811 SL |
407 | |
| 408 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 409 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| c4d0e811 | 410 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| c4d0e811 | 411 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| c4d0e811 | 412 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| c4d0e811 SL |
413 | |
| 414 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 415 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
| c4d0e811 | 416 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull |
| c4d0e811 | 417 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| c4d0e811 | 418 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| c4d0e811 SL |
419 | |
| 420 | /* controller 4, Base address 203000 */ | |
| 421 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 | |
| c4d0e811 | 422 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull |
| c4d0e811 | 423 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
| c4d0e811 SL |
424 | |
| 425 | #ifdef CONFIG_PCI | |
| c4d0e811 | 426 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| c4d0e811 SL |
427 | #endif |
| 428 | ||
| 429 | /* Qman/Bman */ | |
| 430 | #ifndef CONFIG_NOBQFMAN | |
| c4d0e811 SL |
431 | #define CONFIG_SYS_BMAN_NUM_PORTALS 18 |
| 432 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
| 433 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 434 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
435 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 436 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 437 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 438 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 439 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 440 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 441 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 442 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| c4d0e811 SL |
443 | #define CONFIG_SYS_QMAN_NUM_PORTALS 18 |
| 444 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
| 445 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 446 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
447 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 448 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 449 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 450 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 451 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 452 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 453 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 454 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| c4d0e811 SL |
455 | |
| 456 | #define CONFIG_SYS_DPAA_FMAN | |
| 457 | #define CONFIG_SYS_DPAA_PME | |
| 458 | #define CONFIG_SYS_PMAN | |
| 459 | #define CONFIG_SYS_DPAA_DCE | |
| 460 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
| 461 | #define CONFIG_SYS_INTERLAKEN | |
| 462 | ||
| c4d0e811 SL |
463 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 464 | #endif /* CONFIG_NOBQFMAN */ | |
| 465 | ||
| 466 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| c4d0e811 SL |
467 | #define RGMII_PHY1_ADDR 0x1 |
| 468 | #define RGMII_PHY2_ADDR 0x2 | |
| 469 | #define FM1_10GEC1_PHY_ADDR 0x3 | |
| 470 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
| 471 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
| 472 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
| 473 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
| 474 | #endif | |
| 475 | ||
| c4d0e811 SL |
476 | /* |
| 477 | * SATA | |
| 478 | */ | |
| 479 | #ifdef CONFIG_FSL_SATA_V2 | |
| c4d0e811 SL |
480 | #define CONFIG_SATA1 |
| 481 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 482 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 483 | #define CONFIG_SATA2 | |
| 484 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 485 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 486 | #define CONFIG_LBA48 | |
| c4d0e811 SL |
487 | #endif |
| 488 | ||
| 489 | /* | |
| 490 | * USB | |
| 491 | */ | |
| 8850c5d5 | 492 | #ifdef CONFIG_USB_EHCI_HCD |
| c4d0e811 | 493 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| c4d0e811 SL |
494 | #define CONFIG_HAS_FSL_DR_USB |
| 495 | #endif | |
| 496 | ||
| 497 | /* | |
| 498 | * SDHC | |
| 499 | */ | |
| 500 | #ifdef CONFIG_MMC | |
| c4d0e811 SL |
501 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 502 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
| c4d0e811 SL |
503 | #endif |
| 504 | ||
| 9941cf78 SL |
505 | /* |
| 506 | * Dynamic MTD Partition support with mtdparts | |
| 507 | */ | |
| 9941cf78 | 508 | |
| c4d0e811 SL |
509 | /* |
| 510 | * Environment | |
| 511 | */ | |
| 512 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 513 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 514 | ||
| c4d0e811 SL |
515 | /* |
| 516 | * Miscellaneous configurable options | |
| 517 | */ | |
| c4d0e811 SL |
518 | |
| 519 | /* | |
| 520 | * For booting Linux, the board info and command line data | |
| 521 | * have to be in the first 64 MB of memory, since this is | |
| 522 | * the maximum mapped by the Linux kernel during initialization. | |
| 523 | */ | |
| 524 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 525 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 526 | ||
| c4d0e811 SL |
527 | /* |
| 528 | * Environment Configuration | |
| 529 | */ | |
| 530 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| c4d0e811 SL |
531 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ |
| 532 | ||
| c4d0e811 SL |
533 | #define __USB_PHY_TYPE utmi |
| 534 | ||
| 535 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 536 | "hwconfig=fsl_ddr:" \ | |
| 537 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
| 538 | "bank_intlv=auto;" \ | |
| 539 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 540 | "netdev=eth0\0" \ | |
| 541 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 542 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 543 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 544 | "protect off $ubootaddr +$filesize && " \ | |
| 545 | "erase $ubootaddr +$filesize && " \ | |
| 546 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 547 | "protect on $ubootaddr +$filesize && " \ | |
| 548 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 549 | "consoledev=ttyS0\0" \ | |
| 550 | "ramdiskaddr=2000000\0" \ | |
| 551 | "ramdiskfile=t2080qds/ramdisk.uboot\0" \ | |
| b24a4f62 | 552 | "fdtaddr=1e00000\0" \ |
| c4d0e811 | 553 | "fdtfile=t2080qds/t2080qds.dtb\0" \ |
| 3246584d | 554 | "bdev=sda3\0" |
| c4d0e811 SL |
555 | |
| 556 | /* | |
| 557 | * For emulation this causes u-boot to jump to the start of the | |
| 558 | * proof point app code automatically | |
| 559 | */ | |
| 7ae1b080 | 560 | #define PROOF_POINTS \ |
| c4d0e811 SL |
561 | "setenv bootargs root=/dev/$bdev rw " \ |
| 562 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 563 | "cpu 1 release 0x29000000 - - -;" \ | |
| 564 | "cpu 2 release 0x29000000 - - -;" \ | |
| 565 | "cpu 3 release 0x29000000 - - -;" \ | |
| 566 | "cpu 4 release 0x29000000 - - -;" \ | |
| 567 | "cpu 5 release 0x29000000 - - -;" \ | |
| 568 | "cpu 6 release 0x29000000 - - -;" \ | |
| 569 | "cpu 7 release 0x29000000 - - -;" \ | |
| 570 | "go 0x29000000" | |
| 571 | ||
| 7ae1b080 | 572 | #define HVBOOT \ |
| c4d0e811 SL |
573 | "setenv bootargs config-addr=0x60000000; " \ |
| 574 | "bootm 0x01000000 - 0x00f00000" | |
| 575 | ||
| 7ae1b080 | 576 | #define ALU \ |
| c4d0e811 SL |
577 | "setenv bootargs root=/dev/$bdev rw " \ |
| 578 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 579 | "cpu 1 release 0x01000000 - - -;" \ | |
| 580 | "cpu 2 release 0x01000000 - - -;" \ | |
| 581 | "cpu 3 release 0x01000000 - - -;" \ | |
| 582 | "cpu 4 release 0x01000000 - - -;" \ | |
| 583 | "cpu 5 release 0x01000000 - - -;" \ | |
| 584 | "cpu 6 release 0x01000000 - - -;" \ | |
| 585 | "cpu 7 release 0x01000000 - - -;" \ | |
| 586 | "go 0x01000000" | |
| 587 | ||
| c4d0e811 | 588 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 589 | |
| 254887a5 | 590 | #endif /* __T208xQDS_H */ |