projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| c4d0e811 SL |
2 | /* |
| 3 | * Copyright 2011-2013 Freescale Semiconductor, Inc. | |
| 8e4be6df | 4 | * Copyright 2020 NXP |
| c4d0e811 SL |
5 | */ |
| 6 | ||
| 7 | /* | |
| 254887a5 | 8 | * T2080/T2081 QDS board configuration file |
| c4d0e811 SL |
9 | */ |
| 10 | ||
| 254887a5 SL |
11 | #ifndef __T208xQDS_H |
| 12 | #define __T208xQDS_H | |
| c4d0e811 | 13 | |
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| c4d0e811 | 16 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
| 0f3d80e9 | 17 | #if defined(CONFIG_ARCH_T2080) |
| c4d0e811 SL |
18 | #define CONFIG_FSL_SATA_V2 |
| 19 | #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ | |
| 20 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| 21 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
| 254887a5 | 22 | #endif |
| c4d0e811 SL |
23 | |
| 24 | /* High Level Configuration Options */ | |
| c4d0e811 | 25 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| c4d0e811 SL |
26 | #define CONFIG_ENABLE_36BIT_PHYS |
| 27 | ||
| c4d0e811 | 28 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
| 51370d56 | 29 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| c4d0e811 SL |
30 | |
| 31 | #ifdef CONFIG_RAMBOOT_PBL | |
| e4536f8e | 32 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg |
| b19e288f | 33 | |
| b19e288f | 34 | #define CONFIG_SPL_FLUSH_IMAGE |
| b19e288f SL |
35 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 36 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 37 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 38 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 39 | #ifdef CONFIG_SPL_BUILD | |
| 40 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 41 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 42 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| b19e288f SL |
43 | #endif |
| 44 | ||
| 88718be3 | 45 | #ifdef CONFIG_MTD_RAW_NAND |
| b19e288f SL |
46 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 47 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
| 48 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 49 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
| 0f3d80e9 | 50 | #if defined(CONFIG_ARCH_T2080) |
| ec90ac73 | 51 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg |
| ec90ac73 | 52 | #endif |
| b19e288f SL |
53 | #endif |
| 54 | ||
| 55 | #ifdef CONFIG_SPIFLASH | |
| 56 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| b19e288f SL |
57 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 58 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| 59 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) | |
| 60 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) | |
| 61 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) | |
| b19e288f SL |
62 | #ifndef CONFIG_SPL_BUILD |
| 63 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c4d0e811 | 64 | #endif |
| 0f3d80e9 | 65 | #if defined(CONFIG_ARCH_T2080) |
| ec90ac73 | 66 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg |
| ec90ac73 | 67 | #endif |
| b19e288f SL |
68 | #endif |
| 69 | ||
| 70 | #ifdef CONFIG_SDCARD | |
| 71 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| b19e288f SL |
72 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 73 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) | |
| 74 | #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) | |
| 75 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
| b19e288f SL |
76 | #ifndef CONFIG_SPL_BUILD |
| 77 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 78 | #endif | |
| 0f3d80e9 | 79 | #if defined(CONFIG_ARCH_T2080) |
| ec90ac73 | 80 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg |
| ec90ac73 | 81 | #endif |
| b19e288f SL |
82 | #endif |
| 83 | ||
| 84 | #endif /* CONFIG_RAMBOOT_PBL */ | |
| c4d0e811 SL |
85 | |
| 86 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
| 87 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 88 | /* Set 1M boot space */ | |
| 89 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
| 90 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
| 91 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
| 92 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| c4d0e811 SL |
93 | #endif |
| 94 | ||
| c4d0e811 SL |
95 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 96 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 97 | #endif | |
| 98 | ||
| 99 | /* | |
| 100 | * These can be toggled for performance analysis, otherwise use default. | |
| 101 | */ | |
| 102 | #define CONFIG_SYS_CACHE_STASHING | |
| 103 | #define CONFIG_BTB /* toggle branch predition */ | |
| 104 | #define CONFIG_DDR_ECC | |
| 105 | #ifdef CONFIG_DDR_ECC | |
| 106 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 107 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 108 | #endif | |
| 109 | ||
| c4d0e811 SL |
110 | #ifndef __ASSEMBLY__ |
| 111 | unsigned long get_board_sys_clk(void); | |
| 112 | unsigned long get_board_ddr_clk(void); | |
| 113 | #endif | |
| 114 | ||
| 115 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
| 116 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 117 | ||
| 118 | /* | |
| 119 | * Config the L3 Cache as L3 SRAM | |
| 120 | */ | |
| b19e288f SL |
121 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 122 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
| 123 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
| a09fea1d | 124 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
| b19e288f SL |
125 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 126 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
| 127 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
| c4d0e811 SL |
128 | |
| 129 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 130 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 131 | ||
| 132 | /* EEPROM */ | |
| 133 | #define CONFIG_ID_EEPROM | |
| 134 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 135 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 136 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 137 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 138 | ||
| 139 | /* | |
| 140 | * DDR Setup | |
| 141 | */ | |
| 142 | #define CONFIG_VERY_BIG_RAM | |
| 143 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 144 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 40483e1e SL |
145 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 146 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| c4d0e811 | 147 | #define CONFIG_DDR_SPD |
| c4d0e811 SL |
148 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 149 | #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ | |
| 150 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 151 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| 152 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
| 153 | #define CTRL_INTLV_PREFERED cacheline | |
| 154 | ||
| 155 | /* | |
| 156 | * IFC Definitions | |
| 157 | */ | |
| 158 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
| 159 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 160 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 161 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 162 | + 0x8000000) | \ | |
| 163 | CSPR_PORT_SIZE_16 | \ | |
| 164 | CSPR_MSEL_NOR | \ | |
| 165 | CSPR_V) | |
| 166 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
| 167 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 168 | CSPR_PORT_SIZE_16 | \ | |
| 169 | CSPR_MSEL_NOR | \ | |
| 170 | CSPR_V) | |
| 171 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 172 | /* NOR Flash Timing Params */ | |
| 173 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 174 | ||
| 175 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 176 | FTIM0_NOR_TEADC(0x5) | \ | |
| 177 | FTIM0_NOR_TEAHC(0x5)) | |
| 178 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 179 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 180 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 181 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 182 | FTIM2_NOR_TCH(0x4) | \ | |
| 183 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 184 | FTIM2_NOR_TWP(0x1c)) | |
| 185 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 186 | ||
| 187 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 188 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 189 | ||
| 190 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 191 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 192 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 193 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 194 | ||
| 195 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 196 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 197 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 198 | ||
| 199 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 200 | #define QIXIS_BASE 0xffdf0000 | |
| 201 | #define QIXIS_LBMAP_SWITCH 6 | |
| 202 | #define QIXIS_LBMAP_MASK 0x0f | |
| 203 | #define QIXIS_LBMAP_SHIFT 0 | |
| 204 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 205 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 46caebc1 YS |
206 | #define QIXIS_LBMAP_NAND 0x09 |
| 207 | #define QIXIS_LBMAP_SD 0x00 | |
| 208 | #define QIXIS_RCW_SRC_NAND 0x104 | |
| 209 | #define QIXIS_RCW_SRC_SD 0x040 | |
| c4d0e811 SL |
210 | #define QIXIS_RST_CTL_RESET 0x83 |
| 211 | #define QIXIS_RST_FORCE_MEM 0x1 | |
| 212 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 213 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 214 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 215 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) | |
| 216 | ||
| 217 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
| 218 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 219 | | CSPR_PORT_SIZE_8 \ | |
| 220 | | CSPR_MSEL_GPCM \ | |
| 221 | | CSPR_V) | |
| 088d52cf | 222 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) |
| c4d0e811 SL |
223 | #define CONFIG_SYS_CSOR3 0x0 |
| 224 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 225 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 226 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 227 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 228 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 229 | FTIM1_GPCM_TRAD(0x3f)) | |
| 230 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| 6b7679c8 | 231 | FTIM2_GPCM_TCH(0x8) | \ |
| c4d0e811 SL |
232 | FTIM2_GPCM_TWP(0x1f)) |
| 233 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 234 | ||
| 235 | /* NAND Flash on IFC */ | |
| 236 | #define CONFIG_NAND_FSL_IFC | |
| 237 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 238 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 239 | ||
| 240 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 241 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 242 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 243 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 244 | | CSPR_V) | |
| 245 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 246 | ||
| 247 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 248 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 249 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 250 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
| 251 | | CSOR_NAND_PGS_2K /* Page Size = 2K */\ | |
| 252 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ | |
| 253 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 254 | ||
| 255 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 256 | ||
| 257 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 258 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 259 | FTIM0_NAND_TWP(0x18) | \ | |
| 260 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 261 | FTIM0_NAND_TWH(0x0a)) | |
| 262 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 263 | FTIM1_NAND_TWBE(0x39) | \ | |
| 264 | FTIM1_NAND_TRR(0x0e) | \ | |
| 265 | FTIM1_NAND_TRP(0x18)) | |
| 266 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 267 | FTIM2_NAND_TREH(0x0a) | \ | |
| 268 | FTIM2_NAND_TWHRE(0x1e)) | |
| 269 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 270 | ||
| 271 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 272 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 273 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| c4d0e811 SL |
274 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 275 | ||
| 88718be3 | 276 | #if defined(CONFIG_MTD_RAW_NAND) |
| c4d0e811 SL |
277 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 278 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 279 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 280 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 281 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 282 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 283 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 284 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 22cbf964 SL |
285 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 286 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 287 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 288 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 289 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 290 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 291 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 292 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 293 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 294 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| c4d0e811 SL |
295 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 296 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 297 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 298 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 299 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 300 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 301 | #else | |
| 302 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 303 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 304 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 305 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 306 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 307 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 308 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 309 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 22cbf964 SL |
310 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 311 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 312 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 313 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 314 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 315 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 316 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 317 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| c4d0e811 SL |
318 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 319 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 320 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 321 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 322 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 323 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 324 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 325 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 326 | #endif | |
| c4d0e811 SL |
327 | |
| 328 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 329 | #define CONFIG_SYS_RAMBOOT | |
| 330 | #endif | |
| 331 | ||
| b19e288f SL |
332 | #ifdef CONFIG_SPL_BUILD |
| 333 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 334 | #else | |
| 335 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 336 | #endif | |
| 337 | ||
| c4d0e811 SL |
338 | #define CONFIG_HWCONFIG |
| 339 | ||
| 340 | /* define to use L1 as initial stack */ | |
| 341 | #define CONFIG_L1_INIT_RAM | |
| 342 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 343 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 344 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 345 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| c4d0e811 SL |
346 | /* The assembler doesn't like typecast */ |
| 347 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 348 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 349 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 350 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 351 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 352 | GENERATED_GBL_DATA_SIZE) | |
| 353 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 9307cbab | 354 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| c4d0e811 SL |
355 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 356 | ||
| 357 | /* | |
| 358 | * Serial Port | |
| 359 | */ | |
| c4d0e811 SL |
360 | #define CONFIG_SYS_NS16550_SERIAL |
| 361 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 362 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 363 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 364 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 365 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 366 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 367 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 368 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 369 | ||
| c4d0e811 SL |
370 | /* |
| 371 | * I2C | |
| 372 | */ | |
| 2147a169 | 373 | #if !CONFIG_IS_ENABLED(DM_I2C) |
| c4d0e811 | 374 | #define CONFIG_SYS_I2C |
| c4d0e811 SL |
375 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 376 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 377 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F | |
| 378 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
| 379 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
| 380 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
| 381 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
| 382 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
| 383 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
| 384 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
| 385 | #define CONFIG_SYS_FSL_I2C3_SPEED 100000 | |
| 386 | #define CONFIG_SYS_FSL_I2C4_SPEED 100000 | |
| 8e4be6df BL |
387 | #endif |
| 388 | ||
| 389 | #define CONFIG_SYS_I2C_FSL | |
| 390 | ||
| c4d0e811 SL |
391 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
| 392 | #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ | |
| 393 | #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ | |
| 394 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 395 | ||
| 3ad2737e YZ |
396 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 397 | ||
| 398 | /* Voltage monitor on channel 2*/ | |
| 399 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
| 400 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
| 401 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
| 402 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
| 403 | ||
| 404 | #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" | |
| 405 | #ifndef CONFIG_SPL_BUILD | |
| 406 | #define CONFIG_VID | |
| 407 | #endif | |
| 408 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
| 409 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
| 410 | /* The lowest and highest voltage allowed for T208xQDS */ | |
| 411 | #define VDD_MV_MIN 819 | |
| 412 | #define VDD_MV_MAX 1212 | |
| c4d0e811 SL |
413 | |
| 414 | /* | |
| 415 | * RapidIO | |
| 416 | */ | |
| 417 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
| 418 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
| 419 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
| 420 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
| 421 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
| 422 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
| 423 | /* | |
| 424 | * for slave u-boot IMAGE instored in master memory space, | |
| 425 | * PHYS must be aligned based on the SIZE | |
| 426 | */ | |
| e4911815 LG |
427 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 428 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
| 429 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
| 430 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
| c4d0e811 SL |
431 | /* |
| 432 | * for slave UCODE and ENV instored in master memory space, | |
| 433 | * PHYS must be aligned based on the SIZE | |
| 434 | */ | |
| e4911815 | 435 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| c4d0e811 SL |
436 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 437 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
| 438 | ||
| 439 | /* slave core release by master*/ | |
| 440 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
| 441 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
| 442 | ||
| 443 | /* | |
| 444 | * SRIO_PCIE_BOOT - SLAVE | |
| 445 | */ | |
| 446 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 447 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
| 448 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
| 449 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
| 450 | #endif | |
| 451 | ||
| 452 | /* | |
| 453 | * eSPI - Enhanced SPI | |
| 454 | */ | |
| c4d0e811 SL |
455 | |
| 456 | /* | |
| 457 | * General PCI | |
| 458 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 459 | */ | |
| b38eaec5 RD |
460 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 461 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 462 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 463 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| c4d0e811 SL |
464 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 465 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 466 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| c4d0e811 | 467 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| c4d0e811 | 468 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| c4d0e811 | 469 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| c4d0e811 SL |
470 | |
| 471 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 472 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| c4d0e811 | 473 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| c4d0e811 | 474 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| c4d0e811 | 475 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| c4d0e811 SL |
476 | |
| 477 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 478 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
| c4d0e811 | 479 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull |
| c4d0e811 | 480 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| c4d0e811 | 481 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| c4d0e811 SL |
482 | |
| 483 | /* controller 4, Base address 203000 */ | |
| 484 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 | |
| c4d0e811 | 485 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull |
| c4d0e811 | 486 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
| c4d0e811 SL |
487 | |
| 488 | #ifdef CONFIG_PCI | |
| 1b14fb7b HZ |
489 | #if !defined(CONFIG_DM_PCI) |
| 490 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 491 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 492 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 493 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 494 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 495 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 496 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 497 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 498 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 499 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 500 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 501 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 502 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 503 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 504 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
| 505 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 506 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| c4d0e811 | 507 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 1b14fb7b | 508 | #endif |
| c4d0e811 | 509 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| c4d0e811 SL |
510 | #endif |
| 511 | ||
| 512 | /* Qman/Bman */ | |
| 513 | #ifndef CONFIG_NOBQFMAN | |
| c4d0e811 SL |
514 | #define CONFIG_SYS_BMAN_NUM_PORTALS 18 |
| 515 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
| 516 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 517 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
518 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 519 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 520 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 521 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 522 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 523 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 524 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 525 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| c4d0e811 SL |
526 | #define CONFIG_SYS_QMAN_NUM_PORTALS 18 |
| 527 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
| 528 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 529 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
530 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 531 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 532 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 533 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 534 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 535 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 536 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 537 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| c4d0e811 SL |
538 | |
| 539 | #define CONFIG_SYS_DPAA_FMAN | |
| 540 | #define CONFIG_SYS_DPAA_PME | |
| 541 | #define CONFIG_SYS_PMAN | |
| 542 | #define CONFIG_SYS_DPAA_DCE | |
| 543 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
| 544 | #define CONFIG_SYS_INTERLAKEN | |
| 545 | ||
| 546 | /* Default address of microcode for the Linux Fman driver */ | |
| 547 | #if defined(CONFIG_SPIFLASH) | |
| 548 | /* | |
| 549 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 550 | * env, so we got 0x110000. | |
| 551 | */ | |
| dcf1d774 | 552 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| c4d0e811 SL |
553 | #elif defined(CONFIG_SDCARD) |
| 554 | /* | |
| 555 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| b19e288f SL |
556 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 557 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
| c4d0e811 | 558 | */ |
| b19e288f | 559 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 88718be3 | 560 | #elif defined(CONFIG_MTD_RAW_NAND) |
| b19e288f | 561 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| c4d0e811 SL |
562 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 563 | /* | |
| 564 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
| 565 | * in two corenet boards, slave's ucode could be stored in master's memory | |
| 566 | * space, the address can be mapped from slave TLB->slave LAW-> | |
| 567 | * slave SRIO or PCIE outbound window->master inbound window-> | |
| 568 | * master LAW->the ucode address in master's memory space. | |
| 569 | */ | |
| dcf1d774 | 570 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
| c4d0e811 | 571 | #else |
| dcf1d774 | 572 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| c4d0e811 SL |
573 | #endif |
| 574 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
| 575 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 576 | #endif /* CONFIG_NOBQFMAN */ | |
| 577 | ||
| 578 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| c4d0e811 SL |
579 | #define RGMII_PHY1_ADDR 0x1 |
| 580 | #define RGMII_PHY2_ADDR 0x2 | |
| 581 | #define FM1_10GEC1_PHY_ADDR 0x3 | |
| 582 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
| 583 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
| 584 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
| 585 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
| 586 | #endif | |
| 587 | ||
| 588 | #ifdef CONFIG_FMAN_ENET | |
| c4d0e811 | 589 | #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| c4d0e811 SL |
590 | #endif |
| 591 | ||
| 592 | /* | |
| 593 | * SATA | |
| 594 | */ | |
| 595 | #ifdef CONFIG_FSL_SATA_V2 | |
| c4d0e811 SL |
596 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 597 | #define CONFIG_SATA1 | |
| 598 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 599 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 600 | #define CONFIG_SATA2 | |
| 601 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 602 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 603 | #define CONFIG_LBA48 | |
| c4d0e811 SL |
604 | #endif |
| 605 | ||
| 606 | /* | |
| 607 | * USB | |
| 608 | */ | |
| 8850c5d5 | 609 | #ifdef CONFIG_USB_EHCI_HCD |
| c4d0e811 SL |
610 | #define CONFIG_USB_EHCI_FSL |
| 611 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| c4d0e811 SL |
612 | #define CONFIG_HAS_FSL_DR_USB |
| 613 | #endif | |
| 614 | ||
| 615 | /* | |
| 616 | * SDHC | |
| 617 | */ | |
| 618 | #ifdef CONFIG_MMC | |
| c4d0e811 SL |
619 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 620 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
| 621 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| c4d0e811 SL |
622 | #endif |
| 623 | ||
| 9941cf78 SL |
624 | /* |
| 625 | * Dynamic MTD Partition support with mtdparts | |
| 626 | */ | |
| 9941cf78 | 627 | |
| c4d0e811 SL |
628 | /* |
| 629 | * Environment | |
| 630 | */ | |
| 631 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 632 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 633 | ||
| c4d0e811 SL |
634 | /* |
| 635 | * Miscellaneous configurable options | |
| 636 | */ | |
| c4d0e811 | 637 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| c4d0e811 SL |
638 | |
| 639 | /* | |
| 640 | * For booting Linux, the board info and command line data | |
| 641 | * have to be in the first 64 MB of memory, since this is | |
| 642 | * the maximum mapped by the Linux kernel during initialization. | |
| 643 | */ | |
| 644 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 645 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 646 | ||
| 647 | #ifdef CONFIG_CMD_KGDB | |
| 648 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 649 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 650 | #endif | |
| 651 | ||
| 652 | /* | |
| 653 | * Environment Configuration | |
| 654 | */ | |
| 655 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 656 | #define CONFIG_BOOTFILE "uImage" | |
| 657 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ | |
| 658 | ||
| 659 | /* default location for tftp and bootm */ | |
| 660 | #define CONFIG_LOADADDR 1000000 | |
| c4d0e811 SL |
661 | #define __USB_PHY_TYPE utmi |
| 662 | ||
| 663 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 664 | "hwconfig=fsl_ddr:" \ | |
| 665 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
| 666 | "bank_intlv=auto;" \ | |
| 667 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 668 | "netdev=eth0\0" \ | |
| 669 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 670 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 671 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 672 | "protect off $ubootaddr +$filesize && " \ | |
| 673 | "erase $ubootaddr +$filesize && " \ | |
| 674 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 675 | "protect on $ubootaddr +$filesize && " \ | |
| 676 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 677 | "consoledev=ttyS0\0" \ | |
| 678 | "ramdiskaddr=2000000\0" \ | |
| 679 | "ramdiskfile=t2080qds/ramdisk.uboot\0" \ | |
| b24a4f62 | 680 | "fdtaddr=1e00000\0" \ |
| c4d0e811 | 681 | "fdtfile=t2080qds/t2080qds.dtb\0" \ |
| 3246584d | 682 | "bdev=sda3\0" |
| c4d0e811 SL |
683 | |
| 684 | /* | |
| 685 | * For emulation this causes u-boot to jump to the start of the | |
| 686 | * proof point app code automatically | |
| 687 | */ | |
| 688 | #define CONFIG_PROOF_POINTS \ | |
| 689 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 690 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 691 | "cpu 1 release 0x29000000 - - -;" \ | |
| 692 | "cpu 2 release 0x29000000 - - -;" \ | |
| 693 | "cpu 3 release 0x29000000 - - -;" \ | |
| 694 | "cpu 4 release 0x29000000 - - -;" \ | |
| 695 | "cpu 5 release 0x29000000 - - -;" \ | |
| 696 | "cpu 6 release 0x29000000 - - -;" \ | |
| 697 | "cpu 7 release 0x29000000 - - -;" \ | |
| 698 | "go 0x29000000" | |
| 699 | ||
| 700 | #define CONFIG_HVBOOT \ | |
| 701 | "setenv bootargs config-addr=0x60000000; " \ | |
| 702 | "bootm 0x01000000 - 0x00f00000" | |
| 703 | ||
| 704 | #define CONFIG_ALU \ | |
| 705 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 706 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 707 | "cpu 1 release 0x01000000 - - -;" \ | |
| 708 | "cpu 2 release 0x01000000 - - -;" \ | |
| 709 | "cpu 3 release 0x01000000 - - -;" \ | |
| 710 | "cpu 4 release 0x01000000 - - -;" \ | |
| 711 | "cpu 5 release 0x01000000 - - -;" \ | |
| 712 | "cpu 6 release 0x01000000 - - -;" \ | |
| 713 | "cpu 7 release 0x01000000 - - -;" \ | |
| 714 | "go 0x01000000" | |
| 715 | ||
| 716 | #define CONFIG_LINUX \ | |
| 717 | "setenv bootargs root=/dev/ram rw " \ | |
| 718 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 719 | "setenv ramdiskaddr 0x02000000;" \ | |
| 720 | "setenv fdtaddr 0x00c00000;" \ | |
| 721 | "setenv loadaddr 0x1000000;" \ | |
| 722 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 723 | ||
| 724 | #define CONFIG_HDBOOT \ | |
| 725 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 726 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 727 | "tftp $loadaddr $bootfile;" \ | |
| 728 | "tftp $fdtaddr $fdtfile;" \ | |
| 729 | "bootm $loadaddr - $fdtaddr" | |
| 730 | ||
| 731 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 732 | "setenv bootargs root=/dev/nfs rw " \ | |
| 733 | "nfsroot=$serverip:$rootpath " \ | |
| 734 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 735 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 736 | "tftp $loadaddr $bootfile;" \ | |
| 737 | "tftp $fdtaddr $fdtfile;" \ | |
| 738 | "bootm $loadaddr - $fdtaddr" | |
| 739 | ||
| 740 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 741 | "setenv bootargs root=/dev/ram rw " \ | |
| 742 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 743 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 744 | "tftp $loadaddr $bootfile;" \ | |
| 745 | "tftp $fdtaddr $fdtfile;" \ | |
| 746 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 747 | ||
| 748 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 749 | ||
| c4d0e811 | 750 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 751 | |
| 254887a5 | 752 | #endif /* __T208xQDS_H */ |