[J-u-boot.git] / include / configs / db-mv784mp-gp.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2014-2015 Stefan Roese <[email protected]>
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_DB_784MP_GP		/* Board target name for DDR training */

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_LBA48

/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_SCAN_SHOW
#endif

/* NAND */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPD_EEPROM		0x4e
#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
dd580801	2	/*
c4be10b5	3	* Copyright (C) 2014-2015 Stefan Roese <[email protected]>
dd580801 SR	4	*/
	5
	6	#ifndef _CONFIG_DB_MV7846MP_GP_H
	7	#define _CONFIG_DB_MV7846MP_GP_H
	8
	9	/*
	10	* High Level Configuration Options (easy to change)
	11	*/
2554167c SR	12	#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
2554167c SR	13
2923c2d2 SR	14	/*
	15	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	16	* for DDR ECC byte filling in the SPL before loading the main
	17	* U-Boot into it.
	18	*/
dd580801 SR	19	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
dd580801 SR	20
dd580801 SR	21	/* I2C */
	22	#define CONFIG_SYS_I2C
	23	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	24	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
dd580801 SR	25	#define CONFIG_SYS_I2C_SLAVE 0x0
	26	#define CONFIG_SYS_I2C_SPEED 100000
	27
49114c87	28	/* USB/EHCI configuration */
49114c87	29	#define CONFIG_EHCI_IS_TDI
8a333716	30	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
49114c87	31
dd580801 SR	32	/* SPI NOR flash default params, used by sf commands */
	33	#define CONFIG_SF_DEFAULT_SPEED 1000000
	34	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
dd580801 SR	35
dd580801 SR	36	/* Environment in SPI NOR flash */
dd580801 SR	37	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	38	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	39	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	40
dd580801	41	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
dd580801	42
e863f7f0	43	/* SATA support */
c4be10b5	44	#define CONFIG_SYS_SATA_MAX_DEVICE 2
c4be10b5	45	#define CONFIG_LBA48
e863f7f0	46
41e705ac	47	/* PCIe support */
6451223a	48	#ifndef CONFIG_SPL_BUILD
41e705ac	49	#define CONFIG_PCI_MVEBU
41e705ac	50	#define CONFIG_PCI_SCAN_SHOW
6451223a	51	#endif
41e705ac	52
d6b6303d SR	53	/* NAND */
	54	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	55	#define CONFIG_SYS_NAND_ONFI_DETECTION
	56
dd580801 SR	57	/*
	58	* mv-common.h should be defined after CMD configs since it used them
	59	* to enable certain macros
	60	*/
	61	#include "mv-common.h"
	62
2554167c SR	63	/*
	64	* Memory layout while starting into the bin_hdr via the
	65	* BootROM:
	66	*
	67	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	68	* 0x4000.4030 bin_hdr start address
	69	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	70	* 0x4007.fffc BootROM stack top
	71	*
	72	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	73	* L2 cache thus cannot be used.
	74	*/
	75
	76	/* SPL */
	77	/* Defines for SPL */
2554167c SR	78	#define CONFIG_SPL_TEXT_BASE 0x40004030
	79	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	80
	81	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	82	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	83
6451223a SR	84	#ifdef CONFIG_SPL_BUILD
	85	#define CONFIG_SYS_MALLOC_SIMPLE
	86	#endif
2554167c SR	87
	88	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	89	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	90
2554167c	91	/* SPL related SPI defines */
2554167c	92	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
2bd8711e	93	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
2554167c SR	94
2554167c SR	95	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
2554167c	96	#define CONFIG_SPD_EEPROM 0x4e
698ffab2	97	#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
2554167c	98
dd580801	99	#endif /* _CONFIG_DB_MV7846MP_GP_H */