[J-u-boot.git] / include / configs / db-mv784mp-gp.h

/*
 * Copyright (C) 2014 Stefan Roese <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_ARMADA_XP		/* SOC Family Name */
#define CONFIG_DB_784MP_GP		/* Board target name for DDR training */

#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE

#define	CONFIG_SYS_TEXT_BASE	0x04000000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_TIME

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define CONFIG_PHY_ADDR			{ 0x10, 0x11, 0x12, 0x13 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R

#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST

/* SATA support */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE

/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO

#define CONFIG_SYS_ATA_REG_OFFSET	0x0100 /* Offset for register access */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0100 /* Offset for data I/O */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4

/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	CONFIG_SYS_IDE_MAXBUS

/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	MVEBU_AXP_SATA_BASE
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x2000
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x4000

#define CONFIG_DOS_PARTITION
#endif /* CONFIG_CMD_IDE */

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					 CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(16 << 10)

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS		0
#define CONFIG_SPL_SPI_CS		0
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM		0x4e

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
dd580801 SR	1	/*
	2	* Copyright (C) 2014 Stefan Roese <[email protected]>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_DB_MV7846MP_GP_H
	8	#define _CONFIG_DB_MV7846MP_GP_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_ARMADA_XP /* SOC Family Name */
2554167c SR	14	#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
2554167c SR	15
dd580801 SR	16	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
	17	#define CONFIG_SYS_GENERIC_BOARD
	18	#define CONFIG_DISPLAY_BOARDINFO_LATE
	19
	20	#define CONFIG_SYS_TEXT_BASE 0x04000000
	21	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	22
	23	/*
	24	* Commands configuration
	25	*/
	26	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
dd580801 SR	27	#define CONFIG_CMD_DHCP
	28	#define CONFIG_CMD_ENV
	29	#define CONFIG_CMD_I2C
e863f7f0	30	#define CONFIG_CMD_IDE
dd580801 SR	31	#define CONFIG_CMD_PING
	32	#define CONFIG_CMD_SF
	33	#define CONFIG_CMD_SPI
	34	#define CONFIG_CMD_TFTPPUT
	35	#define CONFIG_CMD_TIME
	36
	37	/* I2C */
	38	#define CONFIG_SYS_I2C
	39	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	40	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
dd580801 SR	41	#define CONFIG_SYS_I2C_SLAVE 0x0
	42	#define CONFIG_SYS_I2C_SPEED 100000
	43
	44	/* SPI NOR flash default params, used by sf commands */
	45	#define CONFIG_SF_DEFAULT_SPEED 1000000
	46	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	47	#define CONFIG_SPI_FLASH_STMICRO
	48
	49	/* Environment in SPI NOR flash */
	50	#define CONFIG_ENV_IS_IN_SPI_FLASH
	51	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	52	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	53	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	54
	55	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
cae9008f	56	#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
dd580801 SR	57	#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
	58	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	59	#define CONFIG_RESET_PHY_R
	60
	61	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	62	#define CONFIG_SYS_ALT_MEMTEST
	63
e863f7f0 AS	64	/* SATA support */
	65	#ifdef CONFIG_CMD_IDE
	66	#define __io
	67	#define CONFIG_IDE_PREINIT
	68	#define CONFIG_MVSATA_IDE
	69
	70	/* Needs byte-swapping for ATA data register */
	71	#define CONFIG_IDE_SWAP_IO
	72
	73	#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
	74	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
	75	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
	76
	77	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	78	#define CONFIG_SYS_ATA_STRIDE 4
	79
	80	/* CONFIG_CMD_IDE requires some #defines for ATA registers */
	81	#define CONFIG_SYS_IDE_MAXBUS 2
	82	#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
	83
	84	/* ATA registers base is at SATA controller base */
	85	#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
	86	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
	87	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
	88
	89	#define CONFIG_DOS_PARTITION
	90	#endif /* CONFIG_CMD_IDE */
	91
dd580801 SR	92	/*
	93	* mv-common.h should be defined after CMD configs since it used them
	94	* to enable certain macros
	95	*/
	96	#include "mv-common.h"
	97
2554167c SR	98	/*
	99	* Memory layout while starting into the bin_hdr via the
	100	* BootROM:
	101	*
	102	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	103	* 0x4000.4030 bin_hdr start address
	104	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	105	* 0x4007.fffc BootROM stack top
	106	*
	107	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	108	* L2 cache thus cannot be used.
	109	*/
	110
	111	/* SPL */
	112	/* Defines for SPL */
	113	#define CONFIG_SPL_FRAMEWORK
	114	#define CONFIG_SPL_TEXT_BASE 0x40004030
	115	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	116
	117	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	118	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	119
	120	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	121	CONFIG_SPL_BSS_MAX_SIZE)
	122	#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
	123
	124	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	125	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	126
	127	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	128	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	129	#define CONFIG_SPL_SERIAL_SUPPORT
	130	#define CONFIG_SPL_I2C_SUPPORT
2554167c SR	131
	132	/* SPL related SPI defines */
	133	#define CONFIG_SPL_SPI_SUPPORT
	134	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	135	#define CONFIG_SPL_SPI_LOAD
	136	#define CONFIG_SPL_SPI_BUS 0
	137	#define CONFIG_SPL_SPI_CS 0
	138	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
	139
	140	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
ff9112df	141	#define CONFIG_SYS_MVEBU_DDR_AXP
2554167c SR	142	#define CONFIG_SPD_EEPROM 0x4e
2554167c SR	143
dd580801	144	#endif /* _CONFIG_DB_MV7846MP_GP_H */