projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4c835a60 SR |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* | |
| 3 | * (c) 2018 Stefan Roese <[email protected]> | |
| 4 | * | |
| 5 | * This code is mostly based on the code extracted from this MediaTek | |
| 6 | * github repository: | |
| 7 | * | |
| 8 | * https://github.com/MediaTek-Labs/linkit-smart-uboot.git | |
| 9 | * | |
| 10 | * I was not able to find a specific license or other developers | |
| 11 | * copyrights here, so I can't add them here. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <config.h> | |
| 15 | #include <asm/regdef.h> | |
| 16 | #include <asm/mipsregs.h> | |
| 17 | #include <asm/addrspace.h> | |
| 18 | #include <asm/asm.h> | |
| 19 | #include "mt76xx.h" | |
| 20 | ||
| 21 | #ifndef BIT | |
| 22 | #define BIT(nr) (1 << (nr)) | |
| 23 | #endif | |
| 24 | ||
| 25 | #define DELAY_USEC(us) ((us) / 100) | |
| 26 | ||
| 27 | #define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16) | |
| 28 | #define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12) | |
| 29 | ||
| 30 | #if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) | |
| 31 | #define DDR_CFG1_SIZE_VAL 0x222e2323 | |
| 32 | #define DDR_CFG4_SIZE_VAL 7 | |
| 33 | #endif | |
| 34 | #if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) | |
| 35 | #define DDR_CFG1_SIZE_VAL 0x22322323 | |
| 36 | #define DDR_CFG4_SIZE_VAL 9 | |
| 37 | #endif | |
| 38 | #if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) | |
| 39 | #define DDR_CFG1_SIZE_VAL 0x22362323 | |
| 40 | #define DDR_CFG4_SIZE_VAL 9 | |
| 41 | #endif | |
| 42 | #if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) | |
| 43 | #define DDR_CFG1_SIZE_VAL 0x223a2323 | |
| 44 | #define DDR_CFG4_SIZE_VAL 9 | |
| 45 | #endif | |
| 46 | ||
| 47 | #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT) | |
| 48 | #define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16) | |
| 49 | #endif | |
| 50 | #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT) | |
| 51 | #define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16) | |
| 52 | #endif | |
| 53 | ||
| 54 | #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT) | |
| 55 | #define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12) | |
| 56 | #endif | |
| 57 | #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT) | |
| 58 | #define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12) | |
| 59 | #endif | |
| 60 | ||
| 61 | .set noreorder | |
| 62 | ||
| 63 | LEAF(lowlevel_init) | |
| 64 | ||
| 65 | /* Load base addresses as physical addresses for later usage */ | |
| 66 | li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE) | |
| 67 | li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE) | |
| 68 | li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE) | |
| 69 | ||
| 70 | /* polling CPLL is ready */ | |
| 71 | li t1, DELAY_USEC(1000000) | |
| 72 | la t5, MT76XX_ROM_STATUS_REG | |
| 73 | 1: | |
| 74 | lw t2, 0(t5) | |
| 75 | andi t2, t2, 0x1 | |
| 76 | bnez t2, CPLL_READY | |
| 77 | subu t1, t1, 1 | |
| 78 | bgtz t1, 1b | |
| 79 | nop | |
| 80 | la t0, MT76XX_CLKCFG0_REG | |
| 81 | lw t3, 0(t0) | |
| 82 | ori t3, t3, 0x1 | |
| 83 | sw t3, 0(t0) | |
| 84 | b CPLL_DONE | |
| 85 | nop | |
| 86 | CPLL_READY: | |
| 87 | la t0, MT76XX_CLKCFG0_REG | |
| 88 | lw t1, 0(t0) | |
| 89 | li t2, ~0x0c | |
| 90 | and t1, t1, t2 | |
| 91 | ori t1, t1, 0xc | |
| 92 | sw t1, 0(t0) | |
| 93 | la t0, MT76XX_DYN_CFG0_REG | |
| 94 | lw t3, 0(t0) | |
| 95 | li t5, ~((0x0f << 8) | (0x0f << 0)) | |
| 96 | and t3, t3, t5 | |
| 97 | li t5, (10 << 8) | (1 << 0) | |
| 98 | or t3, t3, t5 | |
| 99 | sw t3, 0(t0) | |
| 100 | la t0, MT76XX_CLKCFG0_REG | |
| 101 | lw t3, 0(t0) | |
| 102 | li t4, ~0x0F | |
| 103 | and t3, t3, t4 | |
| 104 | ori t3, t3, 0xc | |
| 105 | sw t3, 0(t0) | |
| 106 | lw t3, 0(t0) | |
| 107 | ori t3, t3, 0x08 | |
| 108 | sw t3, 0(t0) | |
| 109 | ||
| 110 | CPLL_DONE: | |
| a8b0bf63 SR |
111 | /* Reset MC */ |
| 112 | lw t2, 0x34(s0) | |
| 113 | ori t2, BIT(10) | |
| 114 | sw t2, 0x34(s0) | |
| 115 | nop | |
| 116 | ||
| 4c835a60 SR |
117 | /* |
| 118 | * SDR and DDR initialization: delay 200us | |
| 119 | */ | |
| 120 | li t0, DELAY_USEC(200 + 40) | |
| 121 | li t1, 0x1 | |
| 122 | 1: | |
| 123 | sub t0, t0, t1 | |
| 124 | bnez t0, 1b | |
| 125 | nop | |
| 126 | ||
| 127 | /* set DRAM IO PAD for MT7628IC */ | |
| 128 | /* DDR LDO Enable */ | |
| 129 | lw t4, 0x100(s2) | |
| 130 | li t2, BIT(31) | |
| 131 | or t4, t4, t2 | |
| 132 | sw t4, 0x100(s2) | |
| 133 | lw t4, 0x10c(s2) | |
| 134 | j LDO_1P8V | |
| 135 | nop | |
| 136 | LDO_1P8V: | |
| 137 | li t2, ~BIT(6) | |
| 138 | and t4, t4, t2 | |
| 139 | sw t4, 0x10c(s2) | |
| 140 | j DDRLDO_SOFT_START | |
| 141 | LDO_2P5V: | |
| 142 | /* suppose external DDR1 LDO 2.5V */ | |
| 143 | li t2, BIT(6) | |
| 144 | or t4, t4, t2 | |
| 145 | sw t4, 0x10c(s2) | |
| 146 | ||
| 147 | DDRLDO_SOFT_START: | |
| 148 | lw t2, 0x10c(s2) | |
| 149 | li t3, BIT(16) | |
| 150 | or t2, t2, t3 | |
| 151 | sw t2, 0x10c(s2) | |
| 152 | li t3, DELAY_USEC(250*50) | |
| 153 | LDO_DELAY: | |
| 154 | subu t3, t3, 1 | |
| 155 | bnez t3, LDO_DELAY | |
| 156 | nop | |
| 157 | ||
| 158 | lw t2, 0x10c(s2) | |
| 159 | li t3, BIT(18) | |
| 160 | or t2, t2, t3 | |
| 161 | sw t2, 0x10c(s2) | |
| 162 | ||
| 163 | SET_RG_BUCK_FPWM: | |
| 164 | lw t2, 0x104(s2) | |
| 165 | ori t2, t2, BIT(10) | |
| 166 | sw t2, 0x104(s2) | |
| 167 | ||
| 168 | DDR_PAD_CFG: | |
| 169 | /* clean CLK PAD */ | |
| 170 | lw t2, 0x704(s2) | |
| 171 | li t8, 0xfffff0f0 | |
| 172 | and t2, t2, t8 | |
| 173 | /* clean CMD PAD */ | |
| 174 | lw t3, 0x70c(s2) | |
| 175 | li t8, 0xfffff0f0 | |
| 176 | and t3, t3, t8 | |
| 177 | /* clean DQ IPAD */ | |
| 178 | lw t4, 0x710(s2) | |
| 179 | li t8, 0xfffff8ff | |
| 180 | and t4, t4, t8 | |
| 181 | /* clean DQ OPAD */ | |
| 182 | lw t5, 0x714(s2) | |
| 183 | li t8, 0xfffff0f0 | |
| 184 | and t5, t5, t8 | |
| 185 | /* clean DQS IPAD */ | |
| 186 | lw t6, 0x718(s2) | |
| 187 | li t8, 0xfffff8ff | |
| 188 | and t6, t6, t8 | |
| 189 | /* clean DQS OPAD */ | |
| 190 | lw t7, 0x71c(s2) | |
| 191 | li t8, 0xfffff0f0 | |
| 192 | and t7, t7, t8 | |
| 193 | ||
| 194 | lw t9, 0xc(s0) | |
| 195 | srl t9, t9, 16 | |
| 196 | andi t9, t9, 0x1 | |
| 197 | bnez t9, MT7628_AN_DDR1_PAD | |
| 198 | MT7628_KN_PAD: | |
| 199 | li t8, 0x00000303 | |
| 200 | or t2, t2, t8 | |
| 201 | or t3, t3, t8 | |
| 202 | or t5, t5, t8 | |
| 203 | or t7, t7, t8 | |
| 204 | li t8, 0x00000000 | |
| 205 | or t4, t4, t8 | |
| 206 | or t6, t6, t8 | |
| 207 | j SET_PAD_CFG | |
| 208 | MT7628_AN_DDR1_PAD: | |
| 209 | lw t1, 0x10(s0) | |
| 210 | andi t1, t1, 0x1 | |
| 211 | beqz t1, MT7628_AN_DDR2_PAD | |
| 212 | li t8, 0x00000c0c | |
| 213 | or t2, t2, t8 | |
| 214 | li t8, 0x00000202 | |
| 215 | or t3, t3, t8 | |
| 216 | li t8, 0x00000707 | |
| 217 | or t5, t5, t8 | |
| 218 | li t8, 0x00000c0c | |
| 219 | or t7, t7, t8 | |
| 220 | li t8, 0x00000000 | |
| 221 | or t4, t4, t8 | |
| 222 | or t6, t6, t8 | |
| 223 | j SET_PAD_CFG | |
| 224 | MT7628_AN_DDR2_PAD: | |
| 225 | li t8, 0x00000c0c | |
| 226 | or t2, t2, t8 | |
| 227 | li t8, 0x00000202 | |
| 228 | or t3, t3, t8 | |
| 229 | li t8, 0x00000404 | |
| 230 | or t5, t5, t8 | |
| 231 | li t8, 0x00000c0c | |
| 232 | or t7, t7, t8 | |
| 233 | li t8, 0x00000000 /* ODT off */ | |
| 234 | or t4, t4, t8 | |
| 235 | or t6, t6, t8 | |
| 236 | ||
| 237 | SET_PAD_CFG: | |
| 238 | sw t2, 0x704(s2) | |
| 239 | sw t3, 0x70c(s2) | |
| 240 | sw t4, 0x710(s2) | |
| 241 | sw t5, 0x714(s2) | |
| 242 | sw t6, 0x718(s2) | |
| 243 | sw t7, 0x71c(s2) | |
| 244 | ||
| 245 | /* | |
| 246 | * DDR initialization: reset pin to 0 | |
| 247 | */ | |
| 248 | lw t2, 0x34(s0) | |
| 249 | and t2, ~BIT(10) | |
| 250 | sw t2, 0x34(s0) | |
| 251 | nop | |
| 252 | ||
| 253 | /* | |
| 254 | * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready) | |
| 255 | */ | |
| 256 | DDR_READY: | |
| 257 | li t1, DDR_CFG1_REG | |
| 258 | lw t0, 0(t1) | |
| 259 | nop | |
| 260 | and t2, t0, BIT(21) | |
| 261 | beqz t2, DDR_READY | |
| 262 | nop | |
| 263 | ||
| 264 | /* | |
| 265 | * DDR initialization | |
| 266 | * | |
| 267 | * Only DDR2 supported right now. DDR2 support can be added, once | |
| 268 | * boards using it will get added to mainline U-Boot. | |
| 269 | */ | |
| 270 | li t1, DDR_CFG2_REG | |
| 271 | lw t0, 0(t1) | |
| 272 | nop | |
| 273 | and t0, ~BIT(30) | |
| 274 | and t0, ~(7 << 4) | |
| 275 | or t0, (4 << 4) | |
| 276 | or t0, BIT(30) | |
| 277 | or t0, BIT(11) | |
| 278 | sw t0, 0(t1) | |
| 279 | nop | |
| 280 | ||
| 281 | li t1, DDR_CFG3_REG | |
| 282 | lw t2, 0(t1) | |
| 283 | /* Disable ODT; reference board ok, ev board fail */ | |
| 284 | and t2, ~BIT(6) | |
| 285 | or t2, BIT(2) | |
| 286 | li t0, DDR_CFG4_REG | |
| 287 | lw t1, 0(t0) | |
| 288 | li t2, ~(0x01f | 0x0f0) | |
| 289 | and t1, t1, t2 | |
| 290 | ori t1, t1, DDR_CFG4_SIZE_VAL | |
| 291 | sw t1, 0(t0) | |
| 292 | nop | |
| 293 | ||
| 294 | /* | |
| 295 | * DDR initialization: config size and width on reg DDR_CFG1 | |
| 296 | */ | |
| 297 | li t6, DDR_CFG1_SIZE_VAL | |
| 298 | ||
| 299 | and t6, ~DDR_CFG1_CHIP_WIDTH_MASK | |
| 300 | or t6, DDR_CFG1_CHIP_WIDTH_VAL | |
| 301 | ||
| 302 | /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */ | |
| 303 | and t6, ~DDR_CFG1_BUS_WIDTH_MASK | |
| 304 | or t6, DDR_CFG1_BUS_WIDTH_VAL | |
| 305 | ||
| 306 | li t5, DDR_CFG1_REG | |
| 307 | sw t6, 0(t5) | |
| 308 | nop | |
| 309 | ||
| 310 | /* | |
| 311 | * DDR: enable self auto refresh for power saving | |
| 312 | * enable it by default for both RAM and ROM version (for CoC) | |
| 313 | */ | |
| 314 | lw t1, 0x14(s1) | |
| 315 | nop | |
| 316 | and t1, 0xff000000 | |
| 317 | or t1, 0x01 | |
| 318 | sw t1, 0x14(s1) | |
| 319 | nop | |
| 320 | lw t1, 0x10(s1) | |
| 321 | nop | |
| 322 | or t1, 0x10 | |
| 323 | sw t1, 0x10(s1) | |
| 324 | nop | |
| 325 | ||
| 326 | jr ra | |
| 327 | nop | |
| 328 | END(lowlevel_init) |