[J-u-boot.git] / include / configs / linkstation.h

/*
 * Copyright (C) 2006 Mihai Georgian <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 *
 * Standard configuration - all models
 * 0xFFF00000	boot from flash
 *
 * Test configuration (boot from RAM using uloader.o)
 * LinkStation HD-HLAN and KuroBox Standard
 * 0x03F00000	boot from RAM
 * LinkStation HD-HGLAN and KuroBox HG
 * 0x07F00000	boot from RAM
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#if 0
#define DEBUG
#endif

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/*-----------------------------------------------------------------------
 * User configurable settings:
 *   Mandatory settings:
 *     CONFIG_IPADDR_LS		- the IP address of the LinkStation
 *     CONFIG_SERVERIP_LS	- the address of the server for NFS/TFTP/DHCP/BOOTP
 *   Optional settins:
 *     CONFIG_NCIP_LS		- the adress of the computer running net console
 *							  if not configured, it will be set to
 *							  CONFIG_SERVERIP_LS
 */


#define CONFIG_IPADDR_LS	192.168.11.150
#define CONFIG_SERVERIP_LS	192.168.11.149

#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS)
#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined
#endif

#if !defined(CONFIG_NCIP_LS)
#define CONFIG_NCIP_LS		CONFIG_SERVERIP_LS
#endif

/*----------------------------------------------------------------------
 * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING
 *---------------------------------------------------------------------*/

#define CONFIG_MPC8245		1
#define CONFIG_LINKSTATION	1

/*---------------------------------------
 * Supported models
 *
 * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN)
 * LinkStation old model               (CONFIG_LAN) - totally untested
 * LinkStation HGLAN / KuroBox HG      (CONFIG_HGLAN)
 *
 * Models not supported yet
 * TeraStatin                          (CONFIG_HTGL)
 */

#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
#define CONFIG_IDENT_STRING		" LinkStation / KuroBox"
#elif defined(CONFIG_HGLAN)
#define CONFIG_IDENT_STRING		" LinkStation HG / KuroBox HG"
#elif defined(CONFIG_HTGL)
#define CONFIG_IDENT_STRING		" TeraStation"
#else
#error No LinkStation model defined
#endif

#define CONFIG_BOOTDELAY	5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOT_RETRY_TIME

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"Boot in %02d seconds ('s' to stop)...", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR	"s"

#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_EXT2

#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET

#define CONFIG_OF_LIBFDT	1

#define OF_STDOUT_PATH		"/soc10x/serial@80004600"

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/

#define CONFIG_BOOTCOMMAND	"run bootcmd1"
#define CONFIG_BOOTARGS		"root=/dev/sda1 console=ttyS1,57600 [email protected]/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
#define CONFIG_NFSBOOTCOMMAND	"bootp;run nfsargs;bootm"

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
#define UBFILE			"share/u-boot/u-boot-hd.flash.bin"
#elif defined(CONFIG_HGLAN)
#define UBFILE			"share/u-boot/u-boot-hg.flash.bin"
#elif defined(CONFIG_HTGL)
#define UBFILE			"share/u-boot/u-boot-ht.flash.bin"
#else
#error No LinkStation model defined
#endif

#define CONFIG_EXTRA_ENV_SETTINGS						\
	"autoload=no\0"								\
	"stdin=nc\0"								\
	"stdout=nc\0"								\
	"stderr=nc\0"								\
	"ipaddr="__stringify(CONFIG_IPADDR_LS)"\0"			\
	"netmask=255.255.255.0\0"						\
	"serverip="__stringify(CONFIG_SERVERIP_LS)"\0"			\
	"ncip="__stringify(CONFIG_NCIP_LS)"\0"				\
	"netretry=no\0"								\
	"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0"		\
	"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0"	\
	"ldaddr=800000\0"							\
	"hdpart=0:1\0"								\
	"hdfile=boot/uImage\0"							\
	"hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0"	\
	"boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0"	\
	"hdboot=run hdload;run boothd\0"					\
	"flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0"		\
	"emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0"		\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
	"bootretry=30\0"							\
	"bootcmd1=run hdboot;run flboot\0"					\
	"bootcmd2=run flboot\0"							\
	"bootcmd3=run emboot\0"							\
	"writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \
	"writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \
	"ubpart=0:3\0"								\
	"ubfile="UBFILE"\0"							\
	"ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \
	"ubsaddr=fff00000\0"							\
	"ubeaddr=fff2ffff\0"							\
	"ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \
	"upgrade=run ubload ubflash\0"

/*-----------------------------------------------------------------------
 * PCI stuff
 */
#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
/* Verified: CONFIG_PCI_PNP doesn't work */
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

#ifndef CONFIG_PCI_PNP
/* Keep the following defines in sync with the BAT mappings */

#define PCI_ETH_IOADDR      0xbfff00
#define PCI_ETH_MEMADDR     0xbffffc00
#define PCI_IDE_IOADDR      0xbffed0
#define PCI_IDE_MEMADDR     0xbffffb00
#define PCI_USB0_IOADDR     0
#define PCI_USB0_MEMADDR    0xbfffe000
#define PCI_USB1_IOADDR     0
#define PCI_USB1_MEMADDR    0xbfffd000
#define PCI_USB2_IOADDR     0
#define PCI_USB2_MEMADDR    0xbfffcf00

#endif

/*-----------------------------------------------------------------------
 * Ethernet stuff
 */

#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
#define CONFIG_TULIP
#define CONFIG_TULIP_USE_IO
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CONFIG_RTL8169
#endif

#define CONFIG_NET_RETRY_COUNT		5

#define CONFIG_NETCONSOLE

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000

#define CONFIG_SYS_FLASH_BASE		0xFFC00000
#define CONFIG_SYS_FLASH_SIZE		0x00400000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
#define CONFIG_SYS_EUMB_ADDR		0x80000000
#define CONFIG_SYS_PCI_MEM_ADDR	0xB0000000
#define CONFIG_SYS_MISC_REGION_ADDR	0xFE000000

#define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256 kB			*/
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve some kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 1M ... 8M in DRAM		*/

/* Maximum amount of RAM */
#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
#define CONFIG_SYS_MAX_RAM_SIZE	0x04000000	/* 64MB of SDRAM  */
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CONFIG_SYS_MAX_RAM_SIZE	0x08000000	/* 128MB of SDRAM */
#else
#error Unknown LinkStation type
#endif

/*-----------------------------------------------------------------------
 * Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build
 *
 * RAM based builds are for testing purposes. A Linux module, uloader.o,
 * exists to load U-Boot and pass control to it
 *
 * Always do "make clean" after changing the build type
 */
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#if 1 /* RAM is available when the first C function is called */
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000)
#else
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#endif
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*----------------------------------------------------------------------
 * Serial configuration
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		57600

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4600)	/* Console port	*/
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)	/* AVR port	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8245 user's manual.
 *
 * Unless indicated otherwise, the values are
 * taken from the orignal Linkstation boot code
 *
 * Most of the low level configuration setttings are normally used
 * in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
 * Low level initialisation is done in board/linkstation/early_init.S
 * The values below are included for reference purpose only
 */

/* FIXME: 32.768 MHz is the crystal frequency but */
/* the real frequency is lower by about 0.75%     */
#define CONFIG_SYS_CLK_FREQ	32768000
#define CONFIG_SYS_HZ			1000

/* Bit-field values for MCCR1.  */
#define CONFIG_SYS_ROMNAL      0
#define CONFIG_SYS_ROMFAL      11

#define CONFIG_SYS_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
#define CONFIG_SYS_BANK1_ROW	0
#define CONFIG_SYS_BANK2_ROW	0
#define CONFIG_SYS_BANK3_ROW	0
#define CONFIG_SYS_BANK4_ROW	0
#define CONFIG_SYS_BANK5_ROW	0
#define CONFIG_SYS_BANK6_ROW	0
#define CONFIG_SYS_BANK7_ROW	0

/* Bit-field values for MCCR2.  */
#define CONFIG_SYS_TSWAIT      0
#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
#define CONFIG_SYS_REFINT      0x15e0
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CONFIG_SYS_REFINT      0x1580
#endif

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
#define CONFIG_SYS_BSTOPRE	0x91c

/* Bit-field values for MCCR3.  */
#define CONFIG_SYS_REFREC      7

/* Bit-field values for MCCR4.  */
#define CONFIG_SYS_PRETOACT		2
#define CONFIG_SYS_ACTTOPRE		2	/* Original value was 2	*/
#define CONFIG_SYS_ACTORW		2
#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
/*#define CONFIG_SYS_SDMODE_BURSTLEN	3*/
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
/*#define CONFIG_SYS_SDMODE_BURSTLEN	2*/
#endif
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM		1	/* Original setting but there is no EXTROM */
#define CONFIG_SYS_REGDIMM		0
#define CONFIG_SYS_DBUS_SIZE2		1
#define CONFIG_SYS_SDMODE_WRAP		0

#define CONFIG_SYS_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
#define CONFIG_SYS_SDRAM_DSCD		0x30

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START     0x3ff00000
#define CONFIG_SYS_BANK1_END       0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START     0x3ff00000
#define CONFIG_SYS_BANK2_END       0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START     0x3ff00000
#define CONFIG_SYS_BANK3_END       0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START     0x3ff00000
#define CONFIG_SYS_BANK4_END       0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START     0x3ff00000
#define CONFIG_SYS_BANK5_END       0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START     0x3ff00000
#define CONFIG_SYS_BANK6_END       0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START     0x3ff00000
#define CONFIG_SYS_BANK7_END       0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0x15

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* NOTES:
 * 1) GUARDED and WRITETHROUGH not allowed in IBATS
 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 */

/* SDRAM */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* EUMB: 1MB of address space */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* PCI Mem: 256MB of address space */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* PCI and local ROM/Flash: last 32MB of address space */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 *
 * FIXME: This doesn't appear to be true for the newer kernels
 * which map more that 8 MB
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#undef  CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CONFIG_ENV_IS_IN_FLASH
/*
 * The original LinkStation flash organisation uses
 * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
 * We use the last sector of this area to store the environment
 * which leaves max. 384 kB for the U-Boot itself
 */
#define CONFIG_ENV_ADDR		0xFFF60000
#define CONFIG_ENV_SIZE		0x00010000
#define CONFIG_ENV_SECT_SIZE	0x00010000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * IDE/ATA definitions
 */
#undef  CONFIG_IDE_LED				/* No IDE LED			*/
#define CONFIG_IDE_RESET			/* no reset for ide supported	*/
#define CONFIG_IDE_PREINIT			/* check for units		*/
#define CONFIG_LBA48				/* 48 bit LBA supported		*/

#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
#define CONFIG_SYS_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
#elif defined(CONFIG_HGTL)
#define CONFIG_SYS_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
#else
#error Config IDE: Unknown LinkStation type
#endif

#define CONFIG_SYS_ATA_BASE_ADDR	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
#define CONFIG_SYS_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0		/* Offset for alternate registers */

/*-----------------------------------------------------------------------
 * Partitions and file system
 */
#define CONFIG_DOS_PARTITION

#endif	/* __CONFIG_H */
Commit	Line	Data
61525f2f GL	1	/*
	2	* Copyright (C) 2006 Mihai Georgian <[email protected]>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
61525f2f GL	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
2ae18241 WD	10	/*
	11	* Valid values for CONFIG_SYS_TEXT_BASE are:
	12	*
	13	* Standard configuration - all models
	14	* 0xFFF00000 boot from flash
	15	*
	16	* Test configuration (boot from RAM using uloader.o)
	17	* LinkStation HD-HLAN and KuroBox Standard
	18	* 0x03F00000 boot from RAM
	19	* LinkStation HD-HGLAN and KuroBox HG
	20	* 0x07F00000 boot from RAM
	21	*/
	22	#ifndef CONFIG_SYS_TEXT_BASE
	23	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	24	#endif
	25
61525f2f GL	26	#if 0
	27	#define DEBUG
	28	#endif
	29
	30	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	31
	32	/*-----------------------------------------------------------------------
	33	* User configurable settings:
	34	* Mandatory settings:
	35	* CONFIG_IPADDR_LS - the IP address of the LinkStation
	36	* CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP
	37	* Optional settins:
	38	* CONFIG_NCIP_LS - the adress of the computer running net console
	39	* if not configured, it will be set to
	40	* CONFIG_SERVERIP_LS
	41	*/
	42
	43
	44	#define CONFIG_IPADDR_LS 192.168.11.150
	45	#define CONFIG_SERVERIP_LS 192.168.11.149
	46
	47	#if !defined(CONFIG_IPADDR_LS) \|\| !defined(CONFIG_SERVERIP_LS)
	48	#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined
	49	#endif
	50
	51	#if !defined(CONFIG_NCIP_LS)
	52	#define CONFIG_NCIP_LS CONFIG_SERVERIP_LS
	53	#endif
	54
	55	/*----------------------------------------------------------------------
	56	* DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING
	57	---------------------------------------------------------------------/
	58
	59	#define CONFIG_MPC8245 1
	60	#define CONFIG_LINKSTATION 1
	61
	62	/*---------------------------------------
	63	* Supported models
	64	*
	65	* LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN)
	66	* LinkStation old model (CONFIG_LAN) - totally untested
	67	* LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN)
	68	*
	69	* Models not supported yet
	70	* TeraStatin (CONFIG_HTGL)
	71	*/
	72
	73	#if defined(CONFIG_HLAN) \|\| defined(CONFIG_LAN)
	74	#define CONFIG_IDENT_STRING " LinkStation / KuroBox"
	75	#elif defined(CONFIG_HGLAN)
	76	#define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG"
	77	#elif defined(CONFIG_HTGL)
	78	#define CONFIG_IDENT_STRING " TeraStation"
	79	#else
	80	#error No LinkStation model defined
	81	#endif
	82
	83	#define CONFIG_BOOTDELAY 5
	84	#define CONFIG_ZERO_BOOTDELAY_CHECK
	85	#undef CONFIG_BOOT_RETRY_TIME
	86
	87	#define CONFIG_AUTOBOOT_KEYED
c37207d7 WD	88	#define CONFIG_AUTOBOOT_PROMPT \
c37207d7 WD	89	"Boot in %02d seconds ('s' to stop)...", bootdelay
61525f2f GL	90	#define CONFIG_AUTOBOOT_STOP_STR "s"
	91
	92	#define CONFIG_CMD_IDE
	93	#define CONFIG_CMD_PCI
	94	#define CONFIG_CMD_DHCP
	95	#define CONFIG_CMD_PING
	96	#define CONFIG_CMD_EXT2
	97
a782fb2d TR	98	#define CONFIG_BOOTP_SUBNETMASK
	99	#define CONFIG_BOOTP_GATEWAY
	100	#define CONFIG_BOOTP_HOSTNAME
	101	#define CONFIG_BOOTP_NISDOMAIN
	102	#define CONFIG_BOOTP_BOOTPATH
	103	#define CONFIG_BOOTP_BOOTFILESIZE
	104	#define CONFIG_BOOTP_DNS
	105	#define CONFIG_BOOTP_DNS2
	106	#define CONFIG_BOOTP_SEND_HOSTNAME
	107	#define CONFIG_BOOTP_NTPSERVER
	108	#define CONFIG_BOOTP_TIMEOFFSET
61525f2f GL	109
	110	#define CONFIG_OF_LIBFDT 1
	111
61525f2f GL	112	#define OF_STDOUT_PATH "/soc10x/serial@80004600"
	113
	114	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	115	#include <config_cmd_default.h>
	116
	117	/*
	118	* Miscellaneous configurable options
	119	*/
6d0f6bcf JCPV	120	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	121	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	122	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
61525f2f	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	125	#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
	126	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	127	#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */
61525f2f	128
53677ef1	129	#define CONFIG_BOOTCOMMAND "run bootcmd1"
61525f2f	130	#define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 [email protected]/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
53677ef1	131	#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm"
61525f2f	132
6d0f6bcf	133	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
61525f2f	134
61525f2f GL	135	#if defined(CONFIG_HLAN) \|\| defined(CONFIG_LAN)
	136	#define UBFILE "share/u-boot/u-boot-hd.flash.bin"
	137	#elif defined(CONFIG_HGLAN)
	138	#define UBFILE "share/u-boot/u-boot-hg.flash.bin"
	139	#elif defined(CONFIG_HTGL)
	140	#define UBFILE "share/u-boot/u-boot-ht.flash.bin"
	141	#else
	142	#error No LinkStation model defined
	143	#endif
	144
	145	#define CONFIG_EXTRA_ENV_SETTINGS \
	146	"autoload=no\0" \
	147	"stdin=nc\0" \
	148	"stdout=nc\0" \
	149	"stderr=nc\0" \
5368c55d	150	"ipaddr="__stringify(CONFIG_IPADDR_LS)"\0" \
61525f2f	151	"netmask=255.255.255.0\0" \
5368c55d MV	152	"serverip="__stringify(CONFIG_SERVERIP_LS)"\0" \
5368c55d MV	153	"ncip="__stringify(CONFIG_NCIP_LS)"\0" \
61525f2f GL	154	"netretry=no\0" \
	155	"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \
	156	"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \
	157	"ldaddr=800000\0" \
	158	"hdpart=0:1\0" \
	159	"hdfile=boot/uImage\0" \
	160	"hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \
	161	"boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \
	162	"hdboot=run hdload;run boothd\0" \
	163	"flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \
	164	"emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \
	165	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	166	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
	167	"bootretry=30\0" \
	168	"bootcmd1=run hdboot;run flboot\0" \
	169	"bootcmd2=run flboot\0" \
	170	"bootcmd3=run emboot\0" \
	171	"writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \
	172	"writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \
	173	"ubpart=0:3\0" \
	174	"ubfile="UBFILE"\0" \
	175	"ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \
	176	"ubsaddr=fff00000\0" \
	177	"ubeaddr=fff2ffff\0" \
	178	"ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \
	179	"upgrade=run ubload ubflash\0"
	180
	181	/*-----------------------------------------------------------------------
	182	* PCI stuff
	183	*/
	184	#define CONFIG_PCI
842033e6	185	#define CONFIG_PCI_INDIRECT_BRIDGE
61525f2f GL	186	/* Verified: CONFIG_PCI_PNP doesn't work */
	187	#undef CONFIG_PCI_PNP
	188	#define CONFIG_PCI_SCAN_SHOW
	189
	190	#ifndef CONFIG_PCI_PNP
	191	/* Keep the following defines in sync with the BAT mappings */
	192
	193	#define PCI_ETH_IOADDR 0xbfff00
	194	#define PCI_ETH_MEMADDR 0xbffffc00
	195	#define PCI_IDE_IOADDR 0xbffed0
	196	#define PCI_IDE_MEMADDR 0xbffffb00
	197	#define PCI_USB0_IOADDR 0
	198	#define PCI_USB0_MEMADDR 0xbfffe000
	199	#define PCI_USB1_IOADDR 0
	200	#define PCI_USB1_MEMADDR 0xbfffd000
	201	#define PCI_USB2_IOADDR 0
	202	#define PCI_USB2_MEMADDR 0xbfffcf00
	203
	204	#endif
	205
	206	/*-----------------------------------------------------------------------
	207	* Ethernet stuff
	208	*/
61525f2f GL	209
	210	#if defined(CONFIG_LAN) \|\| defined(CONFIG_HLAN)
	211	#define CONFIG_TULIP
	212	#define CONFIG_TULIP_USE_IO
	213	#elif defined(CONFIG_HGLAN) \|\| defined(CONFIG_HTGL)
	214	#define CONFIG_RTL8169
	215	#endif
	216
	217	#define CONFIG_NET_RETRY_COUNT 5
	218
	219	#define CONFIG_NETCONSOLE
	220
	221	/*-----------------------------------------------------------------------
	222	* Start addresses for the final memory configuration
	223	* (Set up by the startup code)
6d0f6bcf	224	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
61525f2f	225	*/
6d0f6bcf	226	#define CONFIG_SYS_SDRAM_BASE 0x00000000
61525f2f	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_FLASH_BASE 0xFFC00000
6d0f6bcf JCPV	229	#define CONFIG_SYS_FLASH_SIZE 0x00400000
14d0a02a	230	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
61525f2f	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
	233	#define CONFIG_SYS_EUMB_ADDR 0x80000000
	234	#define CONFIG_SYS_PCI_MEM_ADDR 0xB0000000
	235	#define CONFIG_SYS_MISC_REGION_ADDR 0xFE000000
61525f2f	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256 kB */
6d0f6bcf JCPV	238	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
61525f2f	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	241	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
61525f2f GL	242
	243	/* Maximum amount of RAM */
	244	#if defined(CONFIG_HLAN) \|\| defined(CONFIG_LAN)
6d0f6bcf	245	#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */
61525f2f	246	#elif defined(CONFIG_HGLAN) \|\| defined(CONFIG_HTGL)
6d0f6bcf	247	#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */
61525f2f GL	248	#else
	249	#error Unknown LinkStation type
	250	#endif
	251
	252	/*-----------------------------------------------------------------------
14d0a02a	253	* Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build
61525f2f GL	254	*
	255	* RAM based builds are for testing purposes. A Linux module, uloader.o,
	256	* exists to load U-Boot and pass control to it
	257	*
	258	* Always do "make clean" after changing the build type
	259	*/
6d0f6bcf JCPV	260	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	261	#define CONFIG_SYS_RAMBOOT
61525f2f GL	262	#endif
	263
	264	/*-----------------------------------------------------------------------
	265	* Definitions for initial stack pointer and data area
	266	*/
	267	#if 1 /* RAM is available when the first C function is called */
6d0f6bcf	268	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000)
61525f2f	269	#else
6d0f6bcf	270	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
61525f2f	271	#endif
553f0982	272	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	273	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
61525f2f GL	274
	275	/*----------------------------------------------------------------------
	276	* Serial configuration
	277	*/
	278	#define CONFIG_CONS_INDEX 1
	279	#define CONFIG_BAUDRATE 57600
61525f2f	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	282	#define CONFIG_SYS_NS16550_SERIAL
61525f2f	283
6d0f6bcf	284	#define CONFIG_SYS_NS16550_REG_SIZE 1
61525f2f	285
6d0f6bcf	286	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
61525f2f	287
6d0f6bcf JCPV	288	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4600) /* Console port */
6d0f6bcf JCPV	289	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) /* AVR port */
61525f2f GL	290
	291	/*
	292	* Low Level Configuration Settings
	293	* (address mappings, register initial values, etc.)
	294	* You should know what you are doing if you make changes here.
	295	* For the detail description refer to the MPC8245 user's manual.
	296	*
	297	* Unless indicated otherwise, the values are
	298	* taken from the orignal Linkstation boot code
	299	*
	300	* Most of the low level configuration setttings are normally used
a47a12be	301	* in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
61525f2f GL	302	* Low level initialisation is done in board/linkstation/early_init.S
	303	* The values below are included for reference purpose only
	304	*/
	305
	306	/* FIXME: 32.768 MHz is the crystal frequency but */
	307	/* the real frequency is lower by about 0.75% */
	308	#define CONFIG_SYS_CLK_FREQ 32768000
6d0f6bcf	309	#define CONFIG_SYS_HZ 1000
61525f2f GL	310
61525f2f GL	311	/* Bit-field values for MCCR1. */
6d0f6bcf JCPV	312	#define CONFIG_SYS_ROMNAL 0
	313	#define CONFIG_SYS_ROMFAL 11
	314
	315	#define CONFIG_SYS_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */
	316	#define CONFIG_SYS_BANK1_ROW 0
	317	#define CONFIG_SYS_BANK2_ROW 0
	318	#define CONFIG_SYS_BANK3_ROW 0
	319	#define CONFIG_SYS_BANK4_ROW 0
	320	#define CONFIG_SYS_BANK5_ROW 0
	321	#define CONFIG_SYS_BANK6_ROW 0
	322	#define CONFIG_SYS_BANK7_ROW 0
61525f2f GL	323
61525f2f GL	324	/* Bit-field values for MCCR2. */
6d0f6bcf	325	#define CONFIG_SYS_TSWAIT 0
61525f2f	326	#if defined(CONFIG_LAN) \|\| defined(CONFIG_HLAN)
6d0f6bcf	327	#define CONFIG_SYS_REFINT 0x15e0
61525f2f	328	#elif defined(CONFIG_HGLAN) \|\| defined(CONFIG_HTGL)
6d0f6bcf	329	#define CONFIG_SYS_REFINT 0x1580
61525f2f GL	330	#endif
	331
	332	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
6d0f6bcf	333	#define CONFIG_SYS_BSTOPRE 0x91c
61525f2f GL	334
61525f2f GL	335	/* Bit-field values for MCCR3. */
6d0f6bcf	336	#define CONFIG_SYS_REFREC 7
61525f2f GL	337
61525f2f GL	338	/* Bit-field values for MCCR4. */
6d0f6bcf JCPV	339	#define CONFIG_SYS_PRETOACT 2
	340	#define CONFIG_SYS_ACTTOPRE 2 /* Original value was 2 */
	341	#define CONFIG_SYS_ACTORW 2
61525f2f	342	#if defined(CONFIG_LAN) \|\| defined(CONFIG_HLAN)
6d0f6bcf JCPV	343	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* For 100MHz bus */
6d0f6bcf JCPV	344	/#define CONFIG_SYS_SDMODE_BURSTLEN 3/
61525f2f	345	#elif defined(CONFIG_HGLAN) \|\| defined(CONFIG_HTGL)
6d0f6bcf JCPV	346	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* For 133MHz bus */
6d0f6bcf JCPV	347	/#define CONFIG_SYS_SDMODE_BURSTLEN 2/
61525f2f	348	#endif
6d0f6bcf JCPV	349	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	350	#define CONFIG_SYS_EXTROM 1 /* Original setting but there is no EXTROM */
	351	#define CONFIG_SYS_REGDIMM 0
	352	#define CONFIG_SYS_DBUS_SIZE2 1
	353	#define CONFIG_SYS_SDMODE_WRAP 0
61525f2f	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_PGMAX 0x32 /* All boards use this setting. Original 0x92 */
6d0f6bcf JCPV	356	#define CONFIG_SYS_SDRAM_DSCD 0x30
61525f2f GL	357
	358	/* Memory bank settings.
	359	* Only bits 20-29 are actually used from these vales to set the
	360	* start/end addresses. The upper two bits will always be 0, and the lower
	361	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	362	* address. Refer to the MPC8240 book.
	363	*/
	364
6d0f6bcf JCPV	365	#define CONFIG_SYS_BANK0_START 0x00000000
	366	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	367	#define CONFIG_SYS_BANK0_ENABLE 1
	368	#define CONFIG_SYS_BANK1_START 0x3ff00000
	369	#define CONFIG_SYS_BANK1_END 0x3fffffff
	370	#define CONFIG_SYS_BANK1_ENABLE 0
	371	#define CONFIG_SYS_BANK2_START 0x3ff00000
	372	#define CONFIG_SYS_BANK2_END 0x3fffffff
	373	#define CONFIG_SYS_BANK2_ENABLE 0
	374	#define CONFIG_SYS_BANK3_START 0x3ff00000
	375	#define CONFIG_SYS_BANK3_END 0x3fffffff
	376	#define CONFIG_SYS_BANK3_ENABLE 0
	377	#define CONFIG_SYS_BANK4_START 0x3ff00000
	378	#define CONFIG_SYS_BANK4_END 0x3fffffff
	379	#define CONFIG_SYS_BANK4_ENABLE 0
	380	#define CONFIG_SYS_BANK5_START 0x3ff00000
	381	#define CONFIG_SYS_BANK5_END 0x3fffffff
	382	#define CONFIG_SYS_BANK5_ENABLE 0
	383	#define CONFIG_SYS_BANK6_START 0x3ff00000
	384	#define CONFIG_SYS_BANK6_END 0x3fffffff
	385	#define CONFIG_SYS_BANK6_ENABLE 0
	386	#define CONFIG_SYS_BANK7_START 0x3ff00000
	387	#define CONFIG_SYS_BANK7_END 0x3fffffff
	388	#define CONFIG_SYS_BANK7_ENABLE 0
	389
	390	#define CONFIG_SYS_ODCR 0x15
61525f2f GL	391
	392	/*----------------------------------------------------------------------
	393	* Initial BAT mappings
	394	*/
	395
	396	/* NOTES:
	397	* 1) GUARDED and WRITETHROUGH not allowed in IBATS
	398	* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
	399	*/
	400
	401	/* SDRAM */
6d0f6bcf JCPV	402	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	403	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_128M \| BATU_VS \| BATU_VP)
61525f2f	404
6d0f6bcf JCPV	405	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
6d0f6bcf JCPV	406	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
61525f2f GL	407
61525f2f GL	408	/* EUMB: 1MB of address space */
6d0f6bcf JCPV	409	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_EUMB_ADDR \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	410	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_EUMB_ADDR \| BATU_BL_1M \| BATU_VS \| BATU_VP)
61525f2f	411
6d0f6bcf JCPV	412	#define CONFIG_SYS_DBAT1L (CONFIG_SYS_IBAT1L \| BATL_GUARDEDSTORAGE)
6d0f6bcf JCPV	413	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
61525f2f GL	414
61525f2f GL	415	/* PCI Mem: 256MB of address space */
6d0f6bcf JCPV	416	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI_MEM_ADDR \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	417	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI_MEM_ADDR \| BATU_BL_256M \| BATU_VS \| BATU_VP)
61525f2f	418
6d0f6bcf JCPV	419	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_IBAT2L \| BATL_GUARDEDSTORAGE)
6d0f6bcf JCPV	420	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
61525f2f GL	421
61525f2f GL	422	/* PCI and local ROM/Flash: last 32MB of address space */
6d0f6bcf JCPV	423	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_ADDR \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	424	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_ADDR \| BATU_BL_32M \| BATU_VS \| BATU_VP)
61525f2f	425
6d0f6bcf JCPV	426	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_IBAT3L \| BATL_GUARDEDSTORAGE)
6d0f6bcf JCPV	427	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
61525f2f GL	428
	429	/*
	430	* For booting Linux, the board info and command line data
	431	* have to be in the first 8 MB of memory, since this is
	432	* the maximum mapped by the Linux kernel during initialization.
	433	*
	434	* FIXME: This doesn't appear to be true for the newer kernels
	435	* which map more that 8 MB
	436	*/
6d0f6bcf	437	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
61525f2f GL	438
	439	/*-----------------------------------------------------------------------
	440	* FLASH organization
	441	*/
6d0f6bcf	442	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	443	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
61525f2f	444
6d0f6bcf JCPV	445	#undef CONFIG_SYS_FLASH_PROTECTION
	446	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	447	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	448	#define CONFIG_SYS_MAX_FLASH_SECT 72 /* Max number of sectors per flash */
61525f2f	449
6d0f6bcf JCPV	450	#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
6d0f6bcf JCPV	451	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
61525f2f	452
6d0f6bcf	453	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
61525f2f	454
6d0f6bcf JCPV	455	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	456	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
61525f2f	457
5a1aceb0	458	#define CONFIG_ENV_IS_IN_FLASH
61525f2f GL	459	/*
	460	* The original LinkStation flash organisation uses
	461	* 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
	462	* We use the last sector of this area to store the environment
	463	* which leaves max. 384 kB for the U-Boot itself
	464	*/
0e8d1586 JCPV	465	#define CONFIG_ENV_ADDR 0xFFF60000
	466	#define CONFIG_ENV_SIZE 0x00010000
	467	#define CONFIG_ENV_SECT_SIZE 0x00010000
61525f2f GL	468
	469	/*-----------------------------------------------------------------------
	470	* Cache Configuration
	471	*/
6d0f6bcf	472	#define CONFIG_SYS_CACHELINE_SIZE 32
61525f2f	473	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	474	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
61525f2f GL	475	#endif
	476
	477	/*-----------------------------------------------------------------------
	478	* IDE/ATA definitions
	479	*/
	480	#undef CONFIG_IDE_LED /* No IDE LED */
	481	#define CONFIG_IDE_RESET /* no reset for ide supported */
	482	#define CONFIG_IDE_PREINIT /* check for units */
	483	#define CONFIG_LBA48 /* 48 bit LBA supported */
	484
	485	#if defined(CONFIG_LAN) \|\| defined(CONFIG_HLAN) \|\| defined(CONFIG_HGLAN)
6d0f6bcf JCPV	486	#define CONFIG_SYS_IDE_MAXBUS 1 /* Scan only 1 IDE bus */
6d0f6bcf JCPV	487	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */
61525f2f	488	#elif defined(CONFIG_HGTL)
6d0f6bcf JCPV	489	#define CONFIG_SYS_IDE_MAXBUS 2 /* Max. 2 IDE busses */
6d0f6bcf JCPV	490	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
61525f2f GL	491	#else
	492	#error Config IDE: Unknown LinkStation type
	493	#endif
	494
6d0f6bcf	495	#define CONFIG_SYS_ATA_BASE_ADDR 0
61525f2f	496
6d0f6bcf JCPV	497	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* Offset for data I/O */
	498	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* Offset for normal registers */
	499	#define CONFIG_SYS_ATA_ALT_OFFSET 0 /* Offset for alternate registers */
61525f2f GL	500
	501	/*-----------------------------------------------------------------------
	502	* Partitions and file system
	503	*/
	504	#define CONFIG_DOS_PARTITION
	505
61525f2f	506	#endif /* __CONFIG_H */