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61525f2f GL |
1 | /* |
2 | * Copyright (C) 2006 Mihai Georgian <[email protected]> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | #if 0 | |
24 | #define DEBUG | |
25 | #endif | |
26 | ||
27 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
28 | ||
29 | /*----------------------------------------------------------------------- | |
30 | * User configurable settings: | |
31 | * Mandatory settings: | |
32 | * CONFIG_IPADDR_LS - the IP address of the LinkStation | |
33 | * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP | |
34 | * Optional settins: | |
35 | * CONFIG_NCIP_LS - the adress of the computer running net console | |
36 | * if not configured, it will be set to | |
37 | * CONFIG_SERVERIP_LS | |
38 | */ | |
39 | ||
40 | ||
41 | #define CONFIG_IPADDR_LS 192.168.11.150 | |
42 | #define CONFIG_SERVERIP_LS 192.168.11.149 | |
43 | ||
44 | #if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) | |
45 | #error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined | |
46 | #endif | |
47 | ||
48 | #if !defined(CONFIG_NCIP_LS) | |
49 | #define CONFIG_NCIP_LS CONFIG_SERVERIP_LS | |
50 | #endif | |
51 | ||
52 | /*---------------------------------------------------------------------- | |
53 | * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING | |
54 | *---------------------------------------------------------------------*/ | |
55 | ||
56 | #define CONFIG_MPC8245 1 | |
57 | #define CONFIG_LINKSTATION 1 | |
58 | ||
59 | /*--------------------------------------- | |
60 | * Supported models | |
61 | * | |
62 | * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) | |
63 | * LinkStation old model (CONFIG_LAN) - totally untested | |
64 | * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) | |
65 | * | |
66 | * Models not supported yet | |
67 | * TeraStatin (CONFIG_HTGL) | |
68 | */ | |
69 | ||
70 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
71 | #define CONFIG_IDENT_STRING " LinkStation / KuroBox" | |
72 | #elif defined(CONFIG_HGLAN) | |
73 | #define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" | |
74 | #elif defined(CONFIG_HTGL) | |
75 | #define CONFIG_IDENT_STRING " TeraStation" | |
76 | #else | |
77 | #error No LinkStation model defined | |
78 | #endif | |
79 | ||
80 | #define CONFIG_BOOTDELAY 5 | |
81 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
82 | #undef CONFIG_BOOT_RETRY_TIME | |
83 | ||
84 | #define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
85 | #define CONFIG_AUTOBOOT_PROMPT \ |
86 | "Boot in %02d seconds ('s' to stop)...", bootdelay | |
61525f2f GL |
87 | #define CONFIG_AUTOBOOT_STOP_STR "s" |
88 | ||
89 | #define CONFIG_CMD_IDE | |
90 | #define CONFIG_CMD_PCI | |
91 | #define CONFIG_CMD_DHCP | |
92 | #define CONFIG_CMD_PING | |
93 | #define CONFIG_CMD_EXT2 | |
94 | ||
95 | #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL | |
96 | ||
97 | #define CONFIG_OF_LIBFDT 1 | |
98 | ||
61525f2f GL |
99 | #define OF_STDOUT_PATH "/soc10x/serial@80004600" |
100 | ||
101 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
102 | #include <config_cmd_default.h> | |
103 | ||
104 | /* | |
105 | * Miscellaneous configurable options | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
108 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
109 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
61525f2f | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
112 | #define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ | |
113 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
114 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ | |
61525f2f | 115 | |
53677ef1 | 116 | #define CONFIG_BOOTCOMMAND "run bootcmd1" |
61525f2f | 117 | #define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 [email protected]/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug" |
53677ef1 | 118 | #define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" |
61525f2f | 119 | |
6d0f6bcf | 120 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
61525f2f GL |
121 | |
122 | #define XMK_STR(x) #x | |
123 | #define MK_STR(x) XMK_STR(x) | |
124 | ||
125 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
126 | #define UBFILE "share/u-boot/u-boot-hd.flash.bin" | |
127 | #elif defined(CONFIG_HGLAN) | |
128 | #define UBFILE "share/u-boot/u-boot-hg.flash.bin" | |
129 | #elif defined(CONFIG_HTGL) | |
130 | #define UBFILE "share/u-boot/u-boot-ht.flash.bin" | |
131 | #else | |
132 | #error No LinkStation model defined | |
133 | #endif | |
134 | ||
135 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
136 | "autoload=no\0" \ | |
137 | "stdin=nc\0" \ | |
138 | "stdout=nc\0" \ | |
139 | "stderr=nc\0" \ | |
140 | "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \ | |
141 | "netmask=255.255.255.0\0" \ | |
142 | "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \ | |
143 | "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \ | |
144 | "netretry=no\0" \ | |
145 | "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ | |
146 | "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ | |
147 | "ldaddr=800000\0" \ | |
148 | "hdpart=0:1\0" \ | |
149 | "hdfile=boot/uImage\0" \ | |
150 | "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \ | |
151 | "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ | |
152 | "hdboot=run hdload;run boothd\0" \ | |
153 | "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ | |
154 | "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ | |
155 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
156 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ | |
157 | "bootretry=30\0" \ | |
158 | "bootcmd1=run hdboot;run flboot\0" \ | |
159 | "bootcmd2=run flboot\0" \ | |
160 | "bootcmd3=run emboot\0" \ | |
161 | "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ | |
162 | "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ | |
163 | "ubpart=0:3\0" \ | |
164 | "ubfile="UBFILE"\0" \ | |
165 | "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ | |
166 | "ubsaddr=fff00000\0" \ | |
167 | "ubeaddr=fff2ffff\0" \ | |
168 | "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ | |
169 | "upgrade=run ubload ubflash\0" | |
170 | ||
171 | /*----------------------------------------------------------------------- | |
172 | * PCI stuff | |
173 | */ | |
174 | #define CONFIG_PCI | |
175 | /* Verified: CONFIG_PCI_PNP doesn't work */ | |
176 | #undef CONFIG_PCI_PNP | |
177 | #define CONFIG_PCI_SCAN_SHOW | |
178 | ||
179 | #ifndef CONFIG_PCI_PNP | |
180 | /* Keep the following defines in sync with the BAT mappings */ | |
181 | ||
182 | #define PCI_ETH_IOADDR 0xbfff00 | |
183 | #define PCI_ETH_MEMADDR 0xbffffc00 | |
184 | #define PCI_IDE_IOADDR 0xbffed0 | |
185 | #define PCI_IDE_MEMADDR 0xbffffb00 | |
186 | #define PCI_USB0_IOADDR 0 | |
187 | #define PCI_USB0_MEMADDR 0xbfffe000 | |
188 | #define PCI_USB1_IOADDR 0 | |
189 | #define PCI_USB1_MEMADDR 0xbfffd000 | |
190 | #define PCI_USB2_IOADDR 0 | |
191 | #define PCI_USB2_MEMADDR 0xbfffcf00 | |
192 | ||
193 | #endif | |
194 | ||
195 | /*----------------------------------------------------------------------- | |
196 | * Ethernet stuff | |
197 | */ | |
198 | #define CONFIG_NET_MULTI | |
199 | ||
200 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) | |
201 | #define CONFIG_TULIP | |
202 | #define CONFIG_TULIP_USE_IO | |
203 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) | |
204 | #define CONFIG_RTL8169 | |
205 | #endif | |
206 | ||
207 | #define CONFIG_NET_RETRY_COUNT 5 | |
208 | ||
209 | #define CONFIG_NETCONSOLE | |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * Start addresses for the final memory configuration | |
213 | * (Set up by the startup code) | |
6d0f6bcf | 214 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
61525f2f | 215 | */ |
6d0f6bcf | 216 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
61525f2f | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
219 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 | |
220 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
61525f2f | 221 | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
223 | #define CONFIG_SYS_EUMB_ADDR 0x80000000 | |
224 | #define CONFIG_SYS_PCI_MEM_ADDR 0xB0000000 | |
225 | #define CONFIG_SYS_MISC_REGION_ADDR 0xFE000000 | |
61525f2f | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256 kB */ |
228 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ | |
61525f2f | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
231 | #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ | |
61525f2f GL |
232 | |
233 | /* Maximum amount of RAM */ | |
234 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
6d0f6bcf | 235 | #define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ |
61525f2f | 236 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
6d0f6bcf | 237 | #define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ |
61525f2f GL |
238 | #else |
239 | #error Unknown LinkStation type | |
240 | #endif | |
241 | ||
242 | /*----------------------------------------------------------------------- | |
243 | * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build | |
244 | * | |
245 | * RAM based builds are for testing purposes. A Linux module, uloader.o, | |
246 | * exists to load U-Boot and pass control to it | |
247 | * | |
248 | * Always do "make clean" after changing the build type | |
249 | */ | |
6d0f6bcf JCPV |
250 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE |
251 | #define CONFIG_SYS_RAMBOOT | |
61525f2f GL |
252 | #endif |
253 | ||
254 | /*----------------------------------------------------------------------- | |
255 | * Definitions for initial stack pointer and data area | |
256 | */ | |
257 | #if 1 /* RAM is available when the first C function is called */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000) |
61525f2f | 259 | #else |
6d0f6bcf | 260 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
61525f2f | 261 | #endif |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_INIT_RAM_END 0x1000 |
263 | #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
264 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
61525f2f GL |
265 | |
266 | /*---------------------------------------------------------------------- | |
267 | * Serial configuration | |
268 | */ | |
269 | #define CONFIG_CONS_INDEX 1 | |
270 | #define CONFIG_BAUDRATE 57600 | |
6d0f6bcf | 271 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
61525f2f | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_NS16550 |
274 | #define CONFIG_SYS_NS16550_SERIAL | |
61525f2f | 275 | |
6d0f6bcf | 276 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
61525f2f | 277 | |
6d0f6bcf | 278 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
61525f2f | 279 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4600) /* Console port */ |
281 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) /* AVR port */ | |
61525f2f GL |
282 | |
283 | /* | |
284 | * Low Level Configuration Settings | |
285 | * (address mappings, register initial values, etc.) | |
286 | * You should know what you are doing if you make changes here. | |
287 | * For the detail description refer to the MPC8245 user's manual. | |
288 | * | |
289 | * Unless indicated otherwise, the values are | |
290 | * taken from the orignal Linkstation boot code | |
291 | * | |
292 | * Most of the low level configuration setttings are normally used | |
8d1f2682 | 293 | * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation. |
61525f2f GL |
294 | * Low level initialisation is done in board/linkstation/early_init.S |
295 | * The values below are included for reference purpose only | |
296 | */ | |
297 | ||
298 | /* FIXME: 32.768 MHz is the crystal frequency but */ | |
299 | /* the real frequency is lower by about 0.75% */ | |
300 | #define CONFIG_SYS_CLK_FREQ 32768000 | |
6d0f6bcf | 301 | #define CONFIG_SYS_HZ 1000 |
61525f2f GL |
302 | |
303 | /* Bit-field values for MCCR1. */ | |
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_ROMNAL 0 |
305 | #define CONFIG_SYS_ROMFAL 11 | |
306 | ||
307 | #define CONFIG_SYS_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ | |
308 | #define CONFIG_SYS_BANK1_ROW 0 | |
309 | #define CONFIG_SYS_BANK2_ROW 0 | |
310 | #define CONFIG_SYS_BANK3_ROW 0 | |
311 | #define CONFIG_SYS_BANK4_ROW 0 | |
312 | #define CONFIG_SYS_BANK5_ROW 0 | |
313 | #define CONFIG_SYS_BANK6_ROW 0 | |
314 | #define CONFIG_SYS_BANK7_ROW 0 | |
61525f2f GL |
315 | |
316 | /* Bit-field values for MCCR2. */ | |
6d0f6bcf | 317 | #define CONFIG_SYS_TSWAIT 0 |
61525f2f | 318 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) |
6d0f6bcf | 319 | #define CONFIG_SYS_REFINT 0x15e0 |
61525f2f | 320 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
6d0f6bcf | 321 | #define CONFIG_SYS_REFINT 0x1580 |
61525f2f GL |
322 | #endif |
323 | ||
324 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ | |
6d0f6bcf | 325 | #define CONFIG_SYS_BSTOPRE 0x91c |
61525f2f GL |
326 | |
327 | /* Bit-field values for MCCR3. */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_REFREC 7 |
61525f2f GL |
329 | |
330 | /* Bit-field values for MCCR4. */ | |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_PRETOACT 2 |
332 | #define CONFIG_SYS_ACTTOPRE 2 /* Original value was 2 */ | |
333 | #define CONFIG_SYS_ACTORW 2 | |
61525f2f | 334 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* For 100MHz bus */ |
336 | /*#define CONFIG_SYS_SDMODE_BURSTLEN 3*/ | |
61525f2f | 337 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* For 133MHz bus */ |
339 | /*#define CONFIG_SYS_SDMODE_BURSTLEN 2*/ | |
61525f2f | 340 | #endif |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
342 | #define CONFIG_SYS_EXTROM 1 /* Original setting but there is no EXTROM */ | |
343 | #define CONFIG_SYS_REGDIMM 0 | |
344 | #define CONFIG_SYS_DBUS_SIZE2 1 | |
345 | #define CONFIG_SYS_SDMODE_WRAP 0 | |
61525f2f | 346 | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ |
348 | #define CONFIG_SYS_SDRAM_DSCD 0x30 | |
61525f2f GL |
349 | |
350 | /* Memory bank settings. | |
351 | * Only bits 20-29 are actually used from these vales to set the | |
352 | * start/end addresses. The upper two bits will always be 0, and the lower | |
353 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
354 | * address. Refer to the MPC8240 book. | |
355 | */ | |
356 | ||
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_BANK0_START 0x00000000 |
358 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
359 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
360 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
361 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
362 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
363 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
364 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
365 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
366 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
367 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
368 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
369 | #define CONFIG_SYS_BANK4_START 0x3ff00000 | |
370 | #define CONFIG_SYS_BANK4_END 0x3fffffff | |
371 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
372 | #define CONFIG_SYS_BANK5_START 0x3ff00000 | |
373 | #define CONFIG_SYS_BANK5_END 0x3fffffff | |
374 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
375 | #define CONFIG_SYS_BANK6_START 0x3ff00000 | |
376 | #define CONFIG_SYS_BANK6_END 0x3fffffff | |
377 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
378 | #define CONFIG_SYS_BANK7_START 0x3ff00000 | |
379 | #define CONFIG_SYS_BANK7_END 0x3fffffff | |
380 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
381 | ||
382 | #define CONFIG_SYS_ODCR 0x15 | |
61525f2f GL |
383 | |
384 | /*---------------------------------------------------------------------- | |
385 | * Initial BAT mappings | |
386 | */ | |
387 | ||
388 | /* NOTES: | |
389 | * 1) GUARDED and WRITETHROUGH not allowed in IBATS | |
390 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
391 | */ | |
392 | ||
393 | /* SDRAM */ | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
395 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) | |
61525f2f | 396 | |
6d0f6bcf JCPV |
397 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
398 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
61525f2f GL |
399 | |
400 | /* EUMB: 1MB of address space */ | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
402 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) | |
61525f2f | 403 | |
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE) |
405 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
61525f2f GL |
406 | |
407 | /* PCI Mem: 256MB of address space */ | |
6d0f6bcf JCPV |
408 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
409 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) | |
61525f2f | 410 | |
6d0f6bcf JCPV |
411 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE) |
412 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
61525f2f GL |
413 | |
414 | /* PCI and local ROM/Flash: last 32MB of address space */ | |
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
416 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) | |
61525f2f | 417 | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE) |
419 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
61525f2f GL |
420 | |
421 | /* | |
422 | * For booting Linux, the board info and command line data | |
423 | * have to be in the first 8 MB of memory, since this is | |
424 | * the maximum mapped by the Linux kernel during initialization. | |
425 | * | |
426 | * FIXME: This doesn't appear to be true for the newer kernels | |
427 | * which map more that 8 MB | |
428 | */ | |
6d0f6bcf | 429 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
61525f2f GL |
430 | |
431 | /*----------------------------------------------------------------------- | |
432 | * FLASH organization | |
433 | */ | |
6d0f6bcf | 434 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 435 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
61525f2f | 436 | |
6d0f6bcf JCPV |
437 | #undef CONFIG_SYS_FLASH_PROTECTION |
438 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
439 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ | |
440 | #define CONFIG_SYS_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ | |
61525f2f | 441 | |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 |
443 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 | |
61525f2f | 444 | |
6d0f6bcf | 445 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
61525f2f | 446 | |
6d0f6bcf JCPV |
447 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
448 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
61525f2f | 449 | |
5a1aceb0 | 450 | #define CONFIG_ENV_IS_IN_FLASH |
61525f2f GL |
451 | /* |
452 | * The original LinkStation flash organisation uses | |
453 | * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader | |
454 | * We use the last sector of this area to store the environment | |
455 | * which leaves max. 384 kB for the U-Boot itself | |
456 | */ | |
0e8d1586 JCPV |
457 | #define CONFIG_ENV_ADDR 0xFFF60000 |
458 | #define CONFIG_ENV_SIZE 0x00010000 | |
459 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
61525f2f GL |
460 | |
461 | /*----------------------------------------------------------------------- | |
462 | * Cache Configuration | |
463 | */ | |
6d0f6bcf | 464 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
61525f2f | 465 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 466 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
61525f2f GL |
467 | #endif |
468 | ||
469 | /*----------------------------------------------------------------------- | |
470 | * IDE/ATA definitions | |
471 | */ | |
472 | #undef CONFIG_IDE_LED /* No IDE LED */ | |
473 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
474 | #define CONFIG_IDE_PREINIT /* check for units */ | |
475 | #define CONFIG_LBA48 /* 48 bit LBA supported */ | |
476 | ||
477 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) | |
6d0f6bcf JCPV |
478 | #define CONFIG_SYS_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ |
479 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ | |
61525f2f | 480 | #elif defined(CONFIG_HGTL) |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_IDE_MAXBUS 2 /* Max. 2 IDE busses */ |
482 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
61525f2f GL |
483 | #else |
484 | #error Config IDE: Unknown LinkStation type | |
485 | #endif | |
486 | ||
6d0f6bcf | 487 | #define CONFIG_SYS_ATA_BASE_ADDR 0 |
61525f2f | 488 | |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* Offset for data I/O */ |
490 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* Offset for normal registers */ | |
491 | #define CONFIG_SYS_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ | |
61525f2f GL |
492 | |
493 | /*----------------------------------------------------------------------- | |
494 | * Partitions and file system | |
495 | */ | |
496 | #define CONFIG_DOS_PARTITION | |
497 | ||
498 | /*----------------------------------------------------------------------- | |
499 | * Internal Definitions | |
500 | * | |
501 | * Boot Flags | |
502 | */ | |
503 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
504 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
505 | ||
506 | #endif /* __CONFIG_H */ |