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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
7885ea85 RC |
2 | /* |
3 | * Copyright (C) 2017 Andes Technology Corporation | |
4 | * Rick Chen, Andes Technology Corporation <[email protected]> | |
7885ea85 RC |
5 | */ |
6 | ||
7885ea85 | 7 | #include <common.h> |
9b4a205f | 8 | #include <init.h> |
7885ea85 RC |
9 | #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) |
10 | #include <netdev.h> | |
11 | #endif | |
12 | #include <linux/io.h> | |
44199ebc RC |
13 | #include <faraday/ftsmc020.h> |
14 | #include <fdtdec.h> | |
edf0acb3 | 15 | #include <dm.h> |
cd61e86e | 16 | #include <spl.h> |
7885ea85 RC |
17 | |
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
48cbf624 | 20 | extern phys_addr_t prior_stage_fdt_address; |
7885ea85 RC |
21 | /* |
22 | * Miscellaneous platform dependent initializations | |
23 | */ | |
24 | ||
25 | int board_init(void) | |
26 | { | |
7885ea85 RC |
27 | gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; |
28 | ||
29 | return 0; | |
30 | } | |
31 | ||
32 | int dram_init(void) | |
33 | { | |
7e24518c | 34 | return fdtdec_setup_mem_size_base(); |
7885ea85 RC |
35 | } |
36 | ||
37 | int dram_init_banksize(void) | |
38 | { | |
7e24518c | 39 | return fdtdec_setup_memory_banksize(); |
7885ea85 RC |
40 | } |
41 | ||
42 | #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) | |
43 | int board_eth_init(bd_t *bd) | |
44 | { | |
45 | return ftmac100_initialize(bd); | |
46 | } | |
47 | #endif | |
48 | ||
49 | ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) | |
50 | { | |
51 | return 0; | |
52 | } | |
d58717e4 RC |
53 | |
54 | void *board_fdt_blob_setup(void) | |
55 | { | |
d58717e4 RC |
56 | return (void *)CONFIG_SYS_FDT_BASE; |
57 | } | |
44199ebc RC |
58 | |
59 | int smc_init(void) | |
60 | { | |
61 | int node = -1; | |
62 | const char *compat = "andestech,atfsmc020"; | |
63 | void *blob = (void *)gd->fdt_blob; | |
64 | fdt_addr_t addr; | |
65 | struct ftsmc020_bank *regs; | |
66 | ||
67 | node = fdt_node_offset_by_compatible(blob, -1, compat); | |
68 | if (node < 0) | |
69 | return -FDT_ERR_NOTFOUND; | |
70 | ||
71 | addr = fdtdec_get_addr(blob, node, "reg"); | |
72 | ||
73 | if (addr == FDT_ADDR_T_NONE) | |
74 | return -EINVAL; | |
75 | ||
76 | regs = (struct ftsmc020_bank *)addr; | |
77 | regs->cr &= ~FTSMC020_BANK_WPROT; | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
edf0acb3 RC |
82 | static void v5l2_init(void) |
83 | { | |
84 | struct udevice *dev; | |
85 | ||
86 | uclass_get_device(UCLASS_CACHE, 0, &dev); | |
87 | } | |
88 | ||
44199ebc RC |
89 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
90 | int board_early_init_f(void) | |
91 | { | |
92 | smc_init(); | |
edf0acb3 | 93 | v5l2_init(); |
44199ebc RC |
94 | |
95 | return 0; | |
96 | } | |
97 | #endif | |
cd61e86e RC |
98 | |
99 | #ifdef CONFIG_SPL | |
100 | void board_boot_order(u32 *spl_boot_list) | |
101 | { | |
102 | u8 i; | |
103 | u32 boot_devices[] = { | |
104 | #ifdef CONFIG_SPL_RAM_SUPPORT | |
105 | BOOT_DEVICE_RAM, | |
106 | #endif | |
107 | #ifdef CONFIG_SPL_MMC_SUPPORT | |
108 | BOOT_DEVICE_MMC1, | |
109 | #endif | |
110 | }; | |
111 | ||
112 | for (i = 0; i < ARRAY_SIZE(boot_devices); i++) | |
113 | spl_boot_list[i] = boot_devices[i]; | |
114 | } | |
115 | #endif | |
116 | ||
117 | #ifdef CONFIG_SPL_LOAD_FIT | |
118 | int board_fit_config_name_match(const char *name) | |
119 | { | |
120 | /* boot using first FIT config */ | |
121 | return 0; | |
122 | } | |
123 | #endif |