[J-u-boot.git] / drivers / fpga / xilinx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2012-2013, Xilinx, Michal Simek
 *
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, [email protected].
 * Keith Outwater, [email protected]
 */

/*
 *  Xilinx FPGA support
 */

#include <common.h>
#include <fpga.h>
#include <virtex2.h>
#include <spartan2.h>
#include <spartan3.h>
#include <zynqpl.h>

/* Local Static Functions */
static int xilinx_validate(xilinx_desc *desc, char *fn);

/* ------------------------------------------------------------------------- */

int fpga_is_partial_data(int devnum, size_t img_len)
{
	const fpga_desc * const desc = fpga_get_desc(devnum);
	xilinx_desc *desc_xilinx = desc->devdesc;

	/* Check datasize against FPGA size */
	if (img_len >= desc_xilinx->size)
		return 0;

	/* datasize is smaller, must be partial data */
	return 1;
}

int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
		       bitstream_type bstype)
{
	unsigned int length;
	unsigned int swapsize;
	unsigned char *dataptr;
	unsigned int i;
	const fpga_desc *desc;
	xilinx_desc *xdesc;

	dataptr = (unsigned char *)fpgadata;
	/* Find out fpga_description */
	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	/* Assign xilinx device description */
	xdesc = desc->devdesc;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	dataptr += length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	if (*dataptr++ != 0x61) {
		debug("%s: Design name id not recognized in bitstream\n",
		      __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;
	printf("  design filename = \"%s\"\n", dataptr);
	dataptr += length;

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr + 1);
	dataptr += 2;

	if (xdesc->name) {
		i = (ulong)strstr((char *)dataptr, xdesc->name);
		if (!i) {
			printf("%s: Wrong bitstream ID for this device\n",
			       __func__);
			printf("%s: Bitstream ID %s, current device ID %d/%s\n",
			       __func__, dataptr, devnum, xdesc->name);
			return FPGA_FAIL;
		}
	} else {
		printf("%s: Please fill correct device ID to xilinx_desc\n",
		       __func__);
	}
	printf("  part number = \"%s\"\n", dataptr);
	dataptr += length;

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  date = \"%s\"\n", dataptr);
	dataptr += length;

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr += 2;
	printf("  time = \"%s\"\n", dataptr);
	dataptr += length;

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length id not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr << 24) +
		   ((unsigned int) *(dataptr + 1) << 16) +
		   ((unsigned int) *(dataptr + 2) << 8) +
		   ((unsigned int) *(dataptr + 3));
	dataptr += 4;
	printf("  bytes in bitstream = %d\n", swapsize);

	return fpga_load(devnum, dataptr, swapsize, bstype);
}

int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
		bitstream_type bstype)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->load) {
		printf("%s: Missing load operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->load(desc, buf, bsize, bstype);
}

#if defined(CONFIG_CMD_FPGA_LOADFS)
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
		   fpga_fs_info *fpga_fsinfo)
{
	if (!xilinx_validate(desc, (char *)__func__)) {
		printf("%s: Invalid device descriptor\n", __func__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->loadfs) {
		printf("%s: Missing loadfs operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
#endif

#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
		 struct fpga_secure_info *fpga_sec_info)
{
	if (!xilinx_validate(desc, (char *)__func__)) {
		printf("%s: Invalid device descriptor\n", __func__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->loads) {
		printf("%s: Missing loads operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
}
#endif

int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
		return FPGA_FAIL;
	}

	if (!desc->operations || !desc->operations->dump) {
		printf("%s: Missing dump operation\n", __func__);
		return FPGA_FAIL;
	}

	return desc->operations->dump(desc, buf, bsize);
}

int xilinx_info(xilinx_desc *desc)
{
	int ret_val = FPGA_FAIL;

	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
		printf ("Family:        \t");
		switch (desc->family) {
		case xilinx_spartan2:
			printf ("Spartan-II\n");
			break;
		case xilinx_spartan3:
			printf ("Spartan-III\n");
			break;
		case xilinx_virtex2:
			printf ("Virtex-II\n");
			break;
		case xilinx_zynq:
			printf("Zynq PL\n");
			break;
		case xilinx_zynqmp:
			printf("ZynqMP PL\n");
			break;
			/* Add new family types here */
		default:
			printf ("Unknown family type, %d\n", desc->family);
		}

		printf ("Interface type:\t");
		switch (desc->iface) {
		case slave_serial:
			printf ("Slave Serial\n");
			break;
		case master_serial:	/* Not used */
			printf ("Master Serial\n");
			break;
		case slave_parallel:
			printf ("Slave Parallel\n");
			break;
		case jtag_mode:		/* Not used */
			printf ("JTAG Mode\n");
			break;
		case slave_selectmap:
			printf ("Slave SelectMap Mode\n");
			break;
		case master_selectmap:
			printf ("Master SelectMap Mode\n");
			break;
		case devcfg:
			printf("Device configuration interface (Zynq)\n");
			break;
		case csu_dma:
			printf("csu_dma configuration interface (ZynqMP)\n");
			break;
			/* Add new interface types here */
		default:
			printf ("Unsupported interface type, %d\n", desc->iface);
		}

		printf("Device Size:   \t%zd bytes\n"
		       "Cookie:        \t0x%x (%d)\n",
		       desc->size, desc->cookie, desc->cookie);
		if (desc->name)
			printf("Device name:   \t%s\n", desc->name);

		if (desc->iface_fns)
			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
		else
			printf ("No Device Function Table.\n");

		if (desc->operations && desc->operations->info)
			desc->operations->info(desc);

		ret_val = FPGA_SUCCESS;
	} else {
		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	}

	return ret_val;
}

/* ------------------------------------------------------------------------- */

static int xilinx_validate(xilinx_desc *desc, char *fn)
{
	int ret_val = false;

	if (desc) {
		if ((desc->family > min_xilinx_type) &&
			(desc->family < max_xilinx_type)) {
			if ((desc->iface > min_xilinx_iface_type) &&
				(desc->iface < max_xilinx_iface_type)) {
				if (desc->size) {
					ret_val = true;
				} else
					printf ("%s: NULL part size\n", fn);
			} else
				printf ("%s: Invalid Interface type, %d\n",
						fn, desc->iface);
		} else
			printf ("%s: Invalid family type, %d\n", fn, desc->family);
	} else
		printf ("%s: NULL descriptor!\n", fn);

	return ret_val;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5d3207da	2	/*
d5dae85f MS	3	* (C) Copyright 2012-2013, Xilinx, Michal Simek
d5dae85f MS	4	*
5d3207da WD	5	* (C) Copyright 2002
	6	* Rich Ireland, Enterasys Networks, [email protected].
	7	* Keith Outwater, [email protected]
5d3207da WD	8	*/
	9
	10	/*
	11	* Xilinx FPGA support
	12	*/
	13
	14	#include <common.h>
6631db47	15	#include <fpga.h>
5d3207da WD	16	#include <virtex2.h>
5d3207da WD	17	#include <spartan2.h>
875c7893	18	#include <spartan3.h>
d5dae85f	19	#include <zynqpl.h>
5d3207da	20
5d3207da	21	/* Local Static Functions */
f8c1be98	22	static int xilinx_validate(xilinx_desc desc, char fn);
5d3207da WD	23
	24	/* ------------------------------------------------------------------------- */
	25
8b93a92f GS	26	int fpga_is_partial_data(int devnum, size_t img_len)
	27	{
	28	const fpga_desc * const desc = fpga_get_desc(devnum);
	29	xilinx_desc *desc_xilinx = desc->devdesc;
	30
	31	/* Check datasize against FPGA size */
	32	if (img_len >= desc_xilinx->size)
	33	return 0;
	34
	35	/* datasize is smaller, must be partial data */
	36	return 1;
	37	}
	38
7a78bd26 MS	39	int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
7a78bd26 MS	40	bitstream_type bstype)
52c20644 MS	41	{
	42	unsigned int length;
	43	unsigned int swapsize;
52c20644 MS	44	unsigned char *dataptr;
52c20644 MS	45	unsigned int i;
6631db47	46	const fpga_desc *desc;
f8c1be98	47	xilinx_desc *xdesc;
52c20644 MS	48
52c20644 MS	49	dataptr = (unsigned char *)fpgadata;
6631db47 MS	50	/* Find out fpga_description */
	51	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
	52	/* Assign xilinx device description */
	53	xdesc = desc->devdesc;
52c20644 MS	54
	55	/* skip the first bytes of the bitsteam, their meaning is unknown */
	56	length = (dataptr << 8) + (dataptr + 1);
	57	dataptr += 2;
	58	dataptr += length;
	59
	60	/* get design name (identifier, length, string) */
	61	length = (dataptr << 8) + (dataptr + 1);
	62	dataptr += 2;
	63	if (*dataptr++ != 0x61) {
	64	debug("%s: Design name id not recognized in bitstream\n",
	65	__func__);
	66	return FPGA_FAIL;
	67	}
	68
	69	length = (dataptr << 8) + (dataptr + 1);
	70	dataptr += 2;
d863909f SDPP	71	printf(" design filename = \"%s\"\n", dataptr);
d863909f SDPP	72	dataptr += length;
52c20644 MS	73
	74	/* get part number (identifier, length, string) */
	75	if (*dataptr++ != 0x62) {
	76	printf("%s: Part number id not recognized in bitstream\n",
	77	__func__);
	78	return FPGA_FAIL;
	79	}
	80
	81	length = (dataptr << 8) + (dataptr + 1);
	82	dataptr += 2;
6631db47 MS	83
6631db47 MS	84	if (xdesc->name) {
d863909f	85	i = (ulong)strstr((char *)dataptr, xdesc->name);
f7213267	86	if (!i) {
6631db47 MS	87	printf("%s: Wrong bitstream ID for this device\n",
	88	__func__);
	89	printf("%s: Bitstream ID %s, current device ID %d/%s\n",
d863909f	90	__func__, dataptr, devnum, xdesc->name);
6631db47 MS	91	return FPGA_FAIL;
	92	}
	93	} else {
f8c1be98	94	printf("%s: Please fill correct device ID to xilinx_desc\n",
6631db47 MS	95	__func__);
6631db47 MS	96	}
d863909f SDPP	97	printf(" part number = \"%s\"\n", dataptr);
d863909f SDPP	98	dataptr += length;
52c20644 MS	99
	100	/* get date (identifier, length, string) */
	101	if (*dataptr++ != 0x63) {
	102	printf("%s: Date identifier not recognized in bitstream\n",
	103	__func__);
	104	return FPGA_FAIL;
	105	}
	106
	107	length = (dataptr << 8) + (dataptr+1);
	108	dataptr += 2;
d863909f SDPP	109	printf(" date = \"%s\"\n", dataptr);
d863909f SDPP	110	dataptr += length;
52c20644 MS	111
	112	/* get time (identifier, length, string) */
	113	if (*dataptr++ != 0x64) {
	114	printf("%s: Time identifier not recognized in bitstream\n",
	115	__func__);
	116	return FPGA_FAIL;
	117	}
	118
	119	length = (dataptr << 8) + (dataptr+1);
	120	dataptr += 2;
d863909f SDPP	121	printf(" time = \"%s\"\n", dataptr);
d863909f SDPP	122	dataptr += length;
52c20644 MS	123
	124	/* get fpga data length (identifier, length) */
	125	if (*dataptr++ != 0x65) {
	126	printf("%s: Data length id not recognized in bitstream\n",
	127	__func__);
	128	return FPGA_FAIL;
	129	}
	130	swapsize = ((unsigned int) *dataptr << 24) +
	131	((unsigned int) *(dataptr + 1) << 16) +
	132	((unsigned int) *(dataptr + 2) << 8) +
	133	((unsigned int) *(dataptr + 3));
	134	dataptr += 4;
	135	printf(" bytes in bitstream = %d\n", swapsize);
	136
7a78bd26	137	return fpga_load(devnum, dataptr, swapsize, bstype);
52c20644 MS	138	}
52c20644 MS	139
7a78bd26 MS	140	int xilinx_load(xilinx_desc desc, const void buf, size_t bsize,
7a78bd26 MS	141	bitstream_type bstype)
5d3207da	142	{
77ddac94	143	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	144	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	145	return FPGA_FAIL;
14cfc4f3 MS	146	}
5d3207da	147
6cd68c81 MS	148	if (!desc->operations \|\| !desc->operations->load) {
	149	printf("%s: Missing load operation\n", __func__);
	150	return FPGA_FAIL;
	151	}
	152
7a78bd26	153	return desc->operations->load(desc, buf, bsize, bstype);
5d3207da WD	154	}
5d3207da WD	155
1a897668 SDPP	156	#if defined(CONFIG_CMD_FPGA_LOADFS)
	157	int xilinx_loadfs(xilinx_desc desc, const void buf, size_t bsize,
	158	fpga_fs_info *fpga_fsinfo)
	159	{
	160	if (!xilinx_validate(desc, (char *)__func__)) {
	161	printf("%s: Invalid device descriptor\n", __func__);
	162	return FPGA_FAIL;
	163	}
	164
6cd68c81 MS	165	if (!desc->operations \|\| !desc->operations->loadfs) {
6cd68c81 MS	166	printf("%s: Missing loadfs operation\n", __func__);
1a897668	167	return FPGA_FAIL;
6cd68c81	168	}
1a897668 SDPP	169
	170	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
	171	}
	172	#endif
	173
a18d09ea SDPP	174	#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
	175	int xilinx_loads(xilinx_desc desc, const void buf, size_t bsize,
	176	struct fpga_secure_info *fpga_sec_info)
	177	{
	178	if (!xilinx_validate(desc, (char *)__func__)) {
	179	printf("%s: Invalid device descriptor\n", __func__);
	180	return FPGA_FAIL;
	181	}
	182
	183	if (!desc->operations \|\| !desc->operations->loads) {
	184	printf("%s: Missing loads operation\n", __func__);
	185	return FPGA_FAIL;
	186	}
	187
	188	return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
	189	}
	190	#endif
	191
f8c1be98	192	int xilinx_dump(xilinx_desc desc, const void buf, size_t bsize)
5d3207da	193	{
77ddac94	194	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da	195	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
14cfc4f3 MS	196	return FPGA_FAIL;
14cfc4f3 MS	197	}
5d3207da	198
6cd68c81 MS	199	if (!desc->operations \|\| !desc->operations->dump) {
	200	printf("%s: Missing dump operation\n", __func__);
	201	return FPGA_FAIL;
	202	}
	203
14cfc4f3	204	return desc->operations->dump(desc, buf, bsize);
5d3207da WD	205	}
5d3207da WD	206
f8c1be98	207	int xilinx_info(xilinx_desc *desc)
5d3207da WD	208	{
	209	int ret_val = FPGA_FAIL;
	210
77ddac94	211	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
5d3207da WD	212	printf ("Family: \t");
5d3207da WD	213	switch (desc->family) {
b625b9ae	214	case xilinx_spartan2:
5d3207da WD	215	printf ("Spartan-II\n");
5d3207da WD	216	break;
2a6e3869	217	case xilinx_spartan3:
875c7893 WD	218	printf ("Spartan-III\n");
875c7893 WD	219	break;
d9071ce0	220	case xilinx_virtex2:
5d3207da WD	221	printf ("Virtex-II\n");
5d3207da WD	222	break;
d5dae85f MS	223	case xilinx_zynq:
	224	printf("Zynq PL\n");
	225	break;
6b245014 SDPP	226	case xilinx_zynqmp:
	227	printf("ZynqMP PL\n");
	228	break;
5d3207da WD	229	/* Add new family types here */
	230	default:
	231	printf ("Unknown family type, %d\n", desc->family);
	232	}
	233
	234	printf ("Interface type:\t");
	235	switch (desc->iface) {
	236	case slave_serial:
	237	printf ("Slave Serial\n");
	238	break;
	239	case master_serial: /* Not used */
	240	printf ("Master Serial\n");
	241	break;
	242	case slave_parallel:
	243	printf ("Slave Parallel\n");
	244	break;
	245	case jtag_mode: /* Not used */
	246	printf ("JTAG Mode\n");
	247	break;
	248	case slave_selectmap:
	249	printf ("Slave SelectMap Mode\n");
	250	break;
	251	case master_selectmap:
	252	printf ("Master SelectMap Mode\n");
	253	break;
d5dae85f MS	254	case devcfg:
	255	printf("Device configuration interface (Zynq)\n");
	256	break;
6b245014 SDPP	257	case csu_dma:
	258	printf("csu_dma configuration interface (ZynqMP)\n");
	259	break;
5d3207da WD	260	/* Add new interface types here */
	261	default:
	262	printf ("Unsupported interface type, %d\n", desc->iface);
	263	}
	264
ddc94378 SG	265	printf("Device Size: \t%zd bytes\n"
	266	"Cookie: \t0x%x (%d)\n",
	267	desc->size, desc->cookie, desc->cookie);
6631db47 MS	268	if (desc->name)
6631db47 MS	269	printf("Device name: \t%s\n", desc->name);
5d3207da	270
e136eaeb	271	if (desc->iface_fns)
5d3207da	272	printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
e136eaeb	273	else
5d3207da WD	274	printf ("No Device Function Table.\n");
5d3207da WD	275
e136eaeb MS	276	if (desc->operations && desc->operations->info)
	277	desc->operations->info(desc);
	278
5d3207da WD	279	ret_val = FPGA_SUCCESS;
	280	} else {
	281	printf ("%s: Invalid device descriptor\n", __FUNCTION__);
	282	}
	283
	284	return ret_val;
	285	}
	286
5d3207da WD	287	/* ------------------------------------------------------------------------- */
5d3207da WD	288
f8c1be98	289	static int xilinx_validate(xilinx_desc desc, char fn)
5d3207da	290	{
472d5460	291	int ret_val = false;
5d3207da WD	292
	293	if (desc) {
	294	if ((desc->family > min_xilinx_type) &&
	295	(desc->family < max_xilinx_type)) {
	296	if ((desc->iface > min_xilinx_iface_type) &&
	297	(desc->iface < max_xilinx_iface_type)) {
	298	if (desc->size) {
472d5460	299	ret_val = true;
5d3207da WD	300	} else
	301	printf ("%s: NULL part size\n", fn);
	302	} else
	303	printf ("%s: Invalid Interface type, %d\n",
	304	fn, desc->iface);
	305	} else
	306	printf ("%s: Invalid family type, %d\n", fn, desc->family);
	307	} else
	308	printf ("%s: NULL descriptor!\n", fn);
	309
	310	return ret_val;
	311	}