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Commit | Line | Data |
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5d3207da | 1 | /* |
d5dae85f MS |
2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek |
3 | * | |
5d3207da WD |
4 | * (C) Copyright 2002 |
5 | * Rich Ireland, Enterasys Networks, [email protected]. | |
6 | * Keith Outwater, [email protected] | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5d3207da WD |
9 | */ |
10 | ||
11 | /* | |
12 | * Xilinx FPGA support | |
13 | */ | |
14 | ||
15 | #include <common.h> | |
6631db47 | 16 | #include <fpga.h> |
5d3207da WD |
17 | #include <virtex2.h> |
18 | #include <spartan2.h> | |
875c7893 | 19 | #include <spartan3.h> |
d5dae85f | 20 | #include <zynqpl.h> |
5d3207da | 21 | |
5d3207da | 22 | /* Local Static Functions */ |
f8c1be98 | 23 | static int xilinx_validate(xilinx_desc *desc, char *fn); |
5d3207da WD |
24 | |
25 | /* ------------------------------------------------------------------------- */ | |
26 | ||
7a78bd26 MS |
27 | int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, |
28 | bitstream_type bstype) | |
52c20644 MS |
29 | { |
30 | unsigned int length; | |
31 | unsigned int swapsize; | |
32 | char buffer[80]; | |
33 | unsigned char *dataptr; | |
34 | unsigned int i; | |
6631db47 | 35 | const fpga_desc *desc; |
f8c1be98 | 36 | xilinx_desc *xdesc; |
52c20644 MS |
37 | |
38 | dataptr = (unsigned char *)fpgadata; | |
6631db47 MS |
39 | /* Find out fpga_description */ |
40 | desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); | |
41 | /* Assign xilinx device description */ | |
42 | xdesc = desc->devdesc; | |
52c20644 MS |
43 | |
44 | /* skip the first bytes of the bitsteam, their meaning is unknown */ | |
45 | length = (*dataptr << 8) + *(dataptr + 1); | |
46 | dataptr += 2; | |
47 | dataptr += length; | |
48 | ||
49 | /* get design name (identifier, length, string) */ | |
50 | length = (*dataptr << 8) + *(dataptr + 1); | |
51 | dataptr += 2; | |
52 | if (*dataptr++ != 0x61) { | |
53 | debug("%s: Design name id not recognized in bitstream\n", | |
54 | __func__); | |
55 | return FPGA_FAIL; | |
56 | } | |
57 | ||
58 | length = (*dataptr << 8) + *(dataptr + 1); | |
59 | dataptr += 2; | |
60 | for (i = 0; i < length; i++) | |
61 | buffer[i] = *dataptr++; | |
62 | ||
63 | printf(" design filename = \"%s\"\n", buffer); | |
64 | ||
65 | /* get part number (identifier, length, string) */ | |
66 | if (*dataptr++ != 0x62) { | |
67 | printf("%s: Part number id not recognized in bitstream\n", | |
68 | __func__); | |
69 | return FPGA_FAIL; | |
70 | } | |
71 | ||
72 | length = (*dataptr << 8) + *(dataptr + 1); | |
73 | dataptr += 2; | |
74 | for (i = 0; i < length; i++) | |
75 | buffer[i] = *dataptr++; | |
6631db47 MS |
76 | |
77 | if (xdesc->name) { | |
78 | i = strncmp(buffer, xdesc->name, strlen(xdesc->name)); | |
79 | if (i) { | |
80 | printf("%s: Wrong bitstream ID for this device\n", | |
81 | __func__); | |
82 | printf("%s: Bitstream ID %s, current device ID %d/%s\n", | |
83 | __func__, buffer, devnum, xdesc->name); | |
84 | return FPGA_FAIL; | |
85 | } | |
86 | } else { | |
f8c1be98 | 87 | printf("%s: Please fill correct device ID to xilinx_desc\n", |
6631db47 MS |
88 | __func__); |
89 | } | |
52c20644 MS |
90 | printf(" part number = \"%s\"\n", buffer); |
91 | ||
92 | /* get date (identifier, length, string) */ | |
93 | if (*dataptr++ != 0x63) { | |
94 | printf("%s: Date identifier not recognized in bitstream\n", | |
95 | __func__); | |
96 | return FPGA_FAIL; | |
97 | } | |
98 | ||
99 | length = (*dataptr << 8) + *(dataptr+1); | |
100 | dataptr += 2; | |
101 | for (i = 0; i < length; i++) | |
102 | buffer[i] = *dataptr++; | |
103 | printf(" date = \"%s\"\n", buffer); | |
104 | ||
105 | /* get time (identifier, length, string) */ | |
106 | if (*dataptr++ != 0x64) { | |
107 | printf("%s: Time identifier not recognized in bitstream\n", | |
108 | __func__); | |
109 | return FPGA_FAIL; | |
110 | } | |
111 | ||
112 | length = (*dataptr << 8) + *(dataptr+1); | |
113 | dataptr += 2; | |
114 | for (i = 0; i < length; i++) | |
115 | buffer[i] = *dataptr++; | |
116 | printf(" time = \"%s\"\n", buffer); | |
117 | ||
118 | /* get fpga data length (identifier, length) */ | |
119 | if (*dataptr++ != 0x65) { | |
120 | printf("%s: Data length id not recognized in bitstream\n", | |
121 | __func__); | |
122 | return FPGA_FAIL; | |
123 | } | |
124 | swapsize = ((unsigned int) *dataptr << 24) + | |
125 | ((unsigned int) *(dataptr + 1) << 16) + | |
126 | ((unsigned int) *(dataptr + 2) << 8) + | |
127 | ((unsigned int) *(dataptr + 3)); | |
128 | dataptr += 4; | |
129 | printf(" bytes in bitstream = %d\n", swapsize); | |
130 | ||
7a78bd26 | 131 | return fpga_load(devnum, dataptr, swapsize, bstype); |
52c20644 MS |
132 | } |
133 | ||
7a78bd26 MS |
134 | int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, |
135 | bitstream_type bstype) | |
5d3207da | 136 | { |
77ddac94 | 137 | if (!xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da | 138 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
14cfc4f3 MS |
139 | return FPGA_FAIL; |
140 | } | |
5d3207da | 141 | |
7a78bd26 | 142 | return desc->operations->load(desc, buf, bsize, bstype); |
5d3207da WD |
143 | } |
144 | ||
1a897668 SDPP |
145 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
146 | int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, | |
147 | fpga_fs_info *fpga_fsinfo) | |
148 | { | |
149 | if (!xilinx_validate(desc, (char *)__func__)) { | |
150 | printf("%s: Invalid device descriptor\n", __func__); | |
151 | return FPGA_FAIL; | |
152 | } | |
153 | ||
154 | if (!desc->operations->loadfs) | |
155 | return FPGA_FAIL; | |
156 | ||
157 | return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); | |
158 | } | |
159 | #endif | |
160 | ||
f8c1be98 | 161 | int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
5d3207da | 162 | { |
77ddac94 | 163 | if (!xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da | 164 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
14cfc4f3 MS |
165 | return FPGA_FAIL; |
166 | } | |
5d3207da | 167 | |
14cfc4f3 | 168 | return desc->operations->dump(desc, buf, bsize); |
5d3207da WD |
169 | } |
170 | ||
f8c1be98 | 171 | int xilinx_info(xilinx_desc *desc) |
5d3207da WD |
172 | { |
173 | int ret_val = FPGA_FAIL; | |
174 | ||
77ddac94 | 175 | if (xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da WD |
176 | printf ("Family: \t"); |
177 | switch (desc->family) { | |
b625b9ae | 178 | case xilinx_spartan2: |
5d3207da WD |
179 | printf ("Spartan-II\n"); |
180 | break; | |
2a6e3869 | 181 | case xilinx_spartan3: |
875c7893 WD |
182 | printf ("Spartan-III\n"); |
183 | break; | |
d9071ce0 | 184 | case xilinx_virtex2: |
5d3207da WD |
185 | printf ("Virtex-II\n"); |
186 | break; | |
d5dae85f MS |
187 | case xilinx_zynq: |
188 | printf("Zynq PL\n"); | |
189 | break; | |
5d3207da WD |
190 | /* Add new family types here */ |
191 | default: | |
192 | printf ("Unknown family type, %d\n", desc->family); | |
193 | } | |
194 | ||
195 | printf ("Interface type:\t"); | |
196 | switch (desc->iface) { | |
197 | case slave_serial: | |
198 | printf ("Slave Serial\n"); | |
199 | break; | |
200 | case master_serial: /* Not used */ | |
201 | printf ("Master Serial\n"); | |
202 | break; | |
203 | case slave_parallel: | |
204 | printf ("Slave Parallel\n"); | |
205 | break; | |
206 | case jtag_mode: /* Not used */ | |
207 | printf ("JTAG Mode\n"); | |
208 | break; | |
209 | case slave_selectmap: | |
210 | printf ("Slave SelectMap Mode\n"); | |
211 | break; | |
212 | case master_selectmap: | |
213 | printf ("Master SelectMap Mode\n"); | |
214 | break; | |
d5dae85f MS |
215 | case devcfg: |
216 | printf("Device configuration interface (Zynq)\n"); | |
217 | break; | |
5d3207da WD |
218 | /* Add new interface types here */ |
219 | default: | |
220 | printf ("Unsupported interface type, %d\n", desc->iface); | |
221 | } | |
222 | ||
223 | printf ("Device Size: \t%d bytes\n" | |
224 | "Cookie: \t0x%x (%d)\n", | |
225 | desc->size, desc->cookie, desc->cookie); | |
6631db47 MS |
226 | if (desc->name) |
227 | printf("Device name: \t%s\n", desc->name); | |
5d3207da WD |
228 | |
229 | if (desc->iface_fns) { | |
230 | printf ("Device Function Table @ 0x%p\n", desc->iface_fns); | |
14cfc4f3 | 231 | desc->operations->info(desc); |
5d3207da WD |
232 | } else |
233 | printf ("No Device Function Table.\n"); | |
234 | ||
235 | ret_val = FPGA_SUCCESS; | |
236 | } else { | |
237 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); | |
238 | } | |
239 | ||
240 | return ret_val; | |
241 | } | |
242 | ||
5d3207da WD |
243 | /* ------------------------------------------------------------------------- */ |
244 | ||
f8c1be98 | 245 | static int xilinx_validate(xilinx_desc *desc, char *fn) |
5d3207da | 246 | { |
472d5460 | 247 | int ret_val = false; |
5d3207da WD |
248 | |
249 | if (desc) { | |
250 | if ((desc->family > min_xilinx_type) && | |
251 | (desc->family < max_xilinx_type)) { | |
252 | if ((desc->iface > min_xilinx_iface_type) && | |
253 | (desc->iface < max_xilinx_iface_type)) { | |
254 | if (desc->size) { | |
472d5460 | 255 | ret_val = true; |
5d3207da WD |
256 | } else |
257 | printf ("%s: NULL part size\n", fn); | |
258 | } else | |
259 | printf ("%s: Invalid Interface type, %d\n", | |
260 | fn, desc->iface); | |
261 | } else | |
262 | printf ("%s: Invalid family type, %d\n", fn, desc->family); | |
263 | } else | |
264 | printf ("%s: NULL descriptor!\n", fn); | |
265 | ||
266 | return ret_val; | |
267 | } |