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[J-u-boot.git] / drivers / serial / ns16550.c
CommitLineData
e85390dc
WD
1/*
2 * COM1 NS16550 support
a47a12be 3 * originally from linux source (arch/powerpc/boot/ns16550.c)
6d0f6bcf 4 * modified to use CONFIG_SYS_ISA_MEM and new defines
e85390dc
WD
5 */
6
d96c2604 7#include <clock_legacy.h>
03de305e 8#include <config.h>
50fce1d5 9#include <clk.h>
12e431b2
SG
10#include <dm.h>
11#include <errno.h>
f7ae49fc 12#include <log.h>
e85390dc 13#include <ns16550.h>
b051eecb 14#include <reset.h>
7f5ff034 15#include <spl.h>
a1b322a9 16#include <watchdog.h>
401d1c4f 17#include <asm/global_data.h>
61b29b82 18#include <linux/err.h>
167cdad1
GR
19#include <linux/types.h>
20#include <asm/io.h>
e85390dc 21
12e431b2
SG
22DECLARE_GLOBAL_DATA_PTR;
23
200779e3
DZ
24#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
25#define UART_MCRVAL (UART_MCR_DTR | \
26 UART_MCR_RTS) /* RTS/DTR */
12e431b2 27
2e2c514a 28#if !CONFIG_IS_ENABLED(DM_SERIAL)
167cdad1 29#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
f8df9d0d
SG
30#define serial_out(x, y) outb(x, (ulong)y)
31#define serial_in(y) inb((ulong)y)
79df1208 32#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
f8df9d0d
SG
33#define serial_out(x, y) out_be32(y, x)
34#define serial_in(y) in_be32(y)
79df1208 35#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
f8df9d0d
SG
36#define serial_out(x, y) out_le32(y, x)
37#define serial_in(y) in_le32(y)
167cdad1 38#else
f8df9d0d
SG
39#define serial_out(x, y) writeb(x, y)
40#define serial_in(y) readb(y)
167cdad1 41#endif
12e431b2 42#endif /* !CONFIG_DM_SERIAL */
e85390dc 43
f899cc14 44#if defined(CONFIG_ARCH_KEYSTONE)
ef509b90
VA
45#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
46#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
d57dee57
KM
47#undef UART_MCRVAL
48#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
49#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
50#else
51#define UART_MCRVAL (UART_MCR_RTS)
52#endif
ef509b90
VA
53#endif
54
6e7df1d1
TR
55#ifndef CFG_SYS_NS16550_IER
56#define CFG_SYS_NS16550_IER 0x00
57#endif /* CFG_SYS_NS16550_IER */
a160ea0b 58
363e6da1 59static inline void serial_out_shift(void *addr, int shift, int value)
76571674 60{
12e431b2 61#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
1f77690e 62 outb(value, (ulong)addr);
78b7d37b 63#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
12e431b2
SG
64 out_le32(addr, value);
65#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
66 out_be32(addr, value);
90914008
SG
67#elif defined(CONFIG_SYS_NS16550_MEM32)
68 writel(value, addr);
12e431b2 69#elif defined(CONFIG_SYS_BIG_ENDIAN)
76571674 70 writeb(value, addr + (1 << shift) - 1);
12e431b2
SG
71#else
72 writeb(value, addr);
73#endif
74}
75
363e6da1 76static inline int serial_in_shift(void *addr, int shift)
12e431b2 77{
12e431b2 78#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
1f77690e 79 return inb((ulong)addr);
78b7d37b 80#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
12e431b2
SG
81 return in_le32(addr);
82#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
83 return in_be32(addr);
90914008
SG
84#elif defined(CONFIG_SYS_NS16550_MEM32)
85 return readl(addr);
12e431b2 86#elif defined(CONFIG_SYS_BIG_ENDIAN)
20379c11 87 return readb(addr + (1 << shift) - 1);
12e431b2
SG
88#else
89 return readb(addr);
90#endif
91}
92
2e2c514a 93#if CONFIG_IS_ENABLED(DM_SERIAL)
fa4ce723 94
91092132
TR
95#ifndef CFG_SYS_NS16550_CLK
96#define CFG_SYS_NS16550_CLK 0
fa4ce723
MV
97#endif
98
62cbde4c
SG
99/*
100 * Use this #ifdef for now since many platforms don't define in(), out(),
101 * out_le32(), etc. but we don't have #defines to indicate this.
102 *
103 * TODO([email protected]): Add CONFIG options to indicate what I/O is available
104 * on a platform
105 */
106#ifdef CONFIG_NS16550_DYNAMIC
8a8d24bd 107static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
62cbde4c
SG
108 int value)
109{
110 if (plat->flags & NS16550_FLAG_IO) {
111 outb(value, addr);
112 } else if (plat->reg_width == 4) {
113 if (plat->flags & NS16550_FLAG_ENDIAN) {
114 if (plat->flags & NS16550_FLAG_BE)
115 out_be32(addr, value);
116 else
117 out_le32(addr, value);
118 } else {
119 writel(value, addr);
120 }
121 } else if (plat->flags & NS16550_FLAG_BE) {
122 writeb(value, addr + (1 << plat->reg_shift) - 1);
123 } else {
124 writeb(value, addr);
125 }
126}
127
8a8d24bd 128static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
62cbde4c
SG
129{
130 if (plat->flags & NS16550_FLAG_IO) {
131 return inb(addr);
132 } else if (plat->reg_width == 4) {
133 if (plat->flags & NS16550_FLAG_ENDIAN) {
134 if (plat->flags & NS16550_FLAG_BE)
135 return in_be32(addr);
136 else
137 return in_le32(addr);
138 } else {
139 return readl(addr);
140 }
141 } else if (plat->flags & NS16550_FLAG_BE) {
142 return readb(addr + (1 << plat->reg_shift) - 1);
143 } else {
144 return readb(addr);
145 }
146}
147#else
8a8d24bd 148static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
62cbde4c
SG
149 int value)
150{
151}
152
8a8d24bd 153static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
62cbde4c
SG
154{
155 return 0;
156}
157
158#endif /* CONFIG_NS16550_DYNAMIC */
159
a9c61ac0 160void ns16550_writeb(struct ns16550 *port, int offset, int value)
76571674 161{
8a8d24bd 162 struct ns16550_plat *plat = port->plat;
76571674
SG
163 unsigned char *addr;
164
165 offset *= 1 << plat->reg_shift;
62cbde4c 166 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
df8ec55d 167
62cbde4c
SG
168 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
169 serial_out_dynamic(plat, addr, value);
170 else
171 serial_out_shift(addr, plat->reg_shift, value);
76571674
SG
172}
173
d30c7209 174static int ns16550_readb(struct ns16550 *port, int offset)
76571674 175{
8a8d24bd 176 struct ns16550_plat *plat = port->plat;
76571674
SG
177 unsigned char *addr;
178
179 offset *= 1 << plat->reg_shift;
62cbde4c 180 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
76571674 181
62cbde4c
SG
182 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
183 return serial_in_dynamic(plat, addr);
184 else
185 return serial_in_shift(addr, plat->reg_shift);
76571674
SG
186}
187
d30c7209 188static u32 ns16550_getfcr(struct ns16550 *port)
65f83802 189{
8a8d24bd 190 struct ns16550_plat *plat = port->plat;
65f83802
MV
191
192 return plat->fcr;
193}
194
65f83802 195#else
d30c7209 196static u32 ns16550_getfcr(struct ns16550 *port)
65f83802 197{
17fa0326 198 return UART_FCR_DEFVAL;
65f83802 199}
12e431b2
SG
200#endif
201
d30c7209 202int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
fa54eb12
SG
203{
204 const unsigned int mode_x_div = 16;
205
21d00436
SG
206 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
207}
208
a9c61ac0 209void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
8bbe33c8 210{
9ad3b049
SG
211 /* to keep serial format, read lcr before writing BKSE */
212 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
213
214 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
8bbe33c8
SG
215 serial_out(baud_divisor & 0xff, &com_port->dll);
216 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
9ad3b049 217 serial_out(lcr_val, &com_port->lcr);
8bbe33c8
SG
218}
219
2d6bf754 220void ns16550_init(struct ns16550 *com_port, int baud_divisor)
e85390dc 221{
371dc068 222#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_OMAP34XX)
fd2aeac5 223 /*
956a8bae
GG
224 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
225 * before SPL starts only THRE bit is set. We have to empty the
226 * transmitter before initialization starts.
fd2aeac5
MH
227 */
228 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
229 == UART_LSR_THRE) {
12e431b2 230 if (baud_divisor != -1)
2d6bf754 231 ns16550_setbrg(com_port, baud_divisor);
1c16606a
PD
232 else {
233 // Re-use old baud rate divisor to flush transmit reg.
234 const int dll = serial_in(&com_port->dll);
235 const int dlm = serial_in(&com_port->dlm);
236 const int divisor = dll | (dlm << 8);
2d6bf754 237 ns16550_setbrg(com_port, divisor);
1c16606a 238 }
fd2aeac5
MH
239 serial_out(0, &com_port->mdr1);
240 }
241#endif
242
cb55b332
SW
243 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
244 ;
245
6e7df1d1 246 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
5d754197 247#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
167cdad1 248 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
945af8d7 249#endif
b051eecb 250
167cdad1 251 serial_out(UART_MCRVAL, &com_port->mcr);
65f83802 252 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
9ad3b049
SG
253 /* initialize serial config to 8N1 before writing baudrate */
254 serial_out(UART_LCRVAL, &com_port->lcr);
12e431b2 255 if (baud_divisor != -1)
2d6bf754 256 ns16550_setbrg(com_port, baud_divisor);
5d754197
LV
257#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
258 defined(CONFIG_OMAP_SERIAL)
f8df9d0d
SG
259 /* /16 is proper to hit 115200 with 48MHz */
260 serial_out(0, &com_port->mdr1);
89024ddc 261#endif
f899cc14 262#if defined(CONFIG_ARCH_KEYSTONE)
ef509b90
VA
263 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
264#endif
e85390dc
WD
265}
266
57c3afbc 267#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
2d6bf754 268void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
e85390dc 269{
6e7df1d1 270 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
2d6bf754 271 ns16550_setbrg(com_port, 0);
167cdad1 272 serial_out(UART_MCRVAL, &com_port->mcr);
65f83802 273 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
2d6bf754 274 ns16550_setbrg(com_port, baud_divisor);
e85390dc 275}
57c3afbc 276#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
e85390dc 277
2d6bf754 278void ns16550_putc(struct ns16550 *com_port, char c)
e85390dc 279{
f8df9d0d
SG
280 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
281 ;
167cdad1 282 serial_out(c, &com_port->thr);
1a2d9b30
SR
283
284 /*
945fc278 285 * Call schedule() upon newline. This is done here in putc
1a2d9b30 286 * since the environment code uses a single puts() to print the complete
945fc278 287 * environment upon "printenv". So we can't put this schedule call
1a2d9b30
SR
288 * in puts().
289 */
290 if (c == '\n')
29caf930 291 schedule();
e85390dc
WD
292}
293
57c3afbc 294#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
2d6bf754 295char ns16550_getc(struct ns16550 *com_port)
e85390dc 296{
167cdad1 297 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
371dc068 298#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_TTY)
232c150a
WD
299 extern void usbtty_poll(void);
300 usbtty_poll();
301#endif
29caf930 302 schedule();
232c150a 303 }
167cdad1 304 return serial_in(&com_port->rbr);
e85390dc
WD
305}
306
2d6bf754 307int ns16550_tstc(struct ns16550 *com_port)
e85390dc 308{
f8df9d0d 309 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
e85390dc
WD
310}
311
57c3afbc 312#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
12e431b2 313
21d00436
SG
314#ifdef CONFIG_DEBUG_UART_NS16550
315
316#include <debug_uart.h>
317
97b05973 318static inline void _debug_uart_init(void)
21d00436 319{
d293759d 320 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
21d00436
SG
321 int baud_divisor;
322
5e998b4d
T
323 /* Wait until tx buffer is empty */
324 while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT))
325 ;
326
21d00436
SG
327 /*
328 * We copy the code from above because it is already horribly messy.
329 * Trying to refactor to nicely remove the duplication doesn't seem
330 * feasible. The better fix is to move all users of this driver to
331 * driver model.
332 */
03c6f176
MV
333 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
334 CONFIG_BAUDRATE);
6e7df1d1 335 serial_dout(&com_port->ier, CFG_SYS_NS16550_IER);
6e780c7a 336 serial_dout(&com_port->mcr, UART_MCRVAL);
17fa0326 337 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
6e780c7a
SG
338
339 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
340 serial_dout(&com_port->dll, baud_divisor & 0xff);
341 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
342 serial_dout(&com_port->lcr, UART_LCRVAL);
21d00436
SG
343}
344
d30c7209 345static inline int NS16550_read_baud_divisor(struct ns16550 *com_port)
c4448bdc
SG
346{
347 int ret;
348
349 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
350 ret = serial_din(&com_port->dll) & 0xff;
351 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
352 serial_dout(&com_port->lcr, UART_LCRVAL);
353
354 return ret;
355}
356
21d00436
SG
357static inline void _debug_uart_putc(int ch)
358{
d293759d 359 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
21d00436 360
c4448bdc
SG
361 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
362#ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
363 if (!NS16550_read_baud_divisor(com_port))
364 return;
365#endif
366 }
6e780c7a 367 serial_dout(&com_port->thr, ch);
21d00436
SG
368}
369
370DEBUG_UART_FUNCS
371
372#endif
373
2e2c514a 374#if CONFIG_IS_ENABLED(DM_SERIAL)
a9c61ac0 375int ns16550_serial_putc(struct udevice *dev, const char ch)
12e431b2 376{
d30c7209 377 struct ns16550 *const com_port = dev_get_priv(dev);
12e431b2
SG
378
379 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
380 return -EAGAIN;
381 serial_out(ch, &com_port->thr);
382
383 /*
945fc278 384 * Call schedule() upon newline. This is done here in putc
12e431b2 385 * since the environment code uses a single puts() to print the complete
945fc278 386 * environment upon "printenv". So we can't put this schedule call
12e431b2
SG
387 * in puts().
388 */
389 if (ch == '\n')
29caf930 390 schedule();
12e431b2
SG
391
392 return 0;
393}
394
a9c61ac0 395int ns16550_serial_pending(struct udevice *dev, bool input)
12e431b2 396{
d30c7209 397 struct ns16550 *const com_port = dev_get_priv(dev);
12e431b2
SG
398
399 if (input)
4dbf9bed 400 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
12e431b2 401 else
4dbf9bed 402 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
12e431b2
SG
403}
404
a9c61ac0 405int ns16550_serial_getc(struct udevice *dev)
12e431b2 406{
d30c7209 407 struct ns16550 *const com_port = dev_get_priv(dev);
7fded0ce
SR
408
409 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
12e431b2
SG
410 return -EAGAIN;
411
7fded0ce 412 return serial_in(&com_port->rbr);
12e431b2
SG
413}
414
a9c61ac0 415int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
12e431b2 416{
d30c7209 417 struct ns16550 *const com_port = dev_get_priv(dev);
8a8d24bd 418 struct ns16550_plat *plat = com_port->plat;
12e431b2
SG
419 int clock_divisor;
420
421 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
422
2d6bf754 423 ns16550_setbrg(com_port, clock_divisor);
12e431b2
SG
424
425 return 0;
426}
427
a9c61ac0 428int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
9ad3b049 429{
d30c7209 430 struct ns16550 *const com_port = dev_get_priv(dev);
9ad3b049
SG
431 int lcr_val = UART_LCR_WLS_8;
432 uint parity = SERIAL_GET_PARITY(serial_config);
433 uint bits = SERIAL_GET_BITS(serial_config);
434 uint stop = SERIAL_GET_STOP(serial_config);
435
436 /*
437 * only parity config is implemented, check if other serial settings
438 * are the default one.
439 */
440 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
441 return -ENOTSUPP; /* not supported in driver*/
442
443 switch (parity) {
444 case SERIAL_PAR_NONE:
445 /* no bits to add */
446 break;
447 case SERIAL_PAR_ODD:
448 lcr_val |= UART_LCR_PEN;
449 break;
450 case SERIAL_PAR_EVEN:
451 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
452 break;
453 default:
454 return -ENOTSUPP; /* not supported in driver*/
455 }
456
457 serial_out(lcr_val, &com_port->lcr);
458 return 0;
459}
460
a9c61ac0 461int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info)
50bf7d03 462{
d30c7209 463 struct ns16550 *const com_port = dev_get_priv(dev);
8a8d24bd 464 struct ns16550_plat *plat = com_port->plat;
50bf7d03 465
7f5ff034 466 /* save code size */
f86580fc 467 if (!not_xpl())
7f5ff034
SG
468 return -ENOSYS;
469
50bf7d03
AS
470 info->type = SERIAL_CHIP_16550_COMPATIBLE;
471#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
472 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
473#else
474 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
475#endif
476 info->addr = plat->base;
f69d3d6d 477 info->size = plat->size;
50bf7d03
AS
478 info->reg_width = plat->reg_width;
479 info->reg_shift = plat->reg_shift;
480 info->reg_offset = plat->reg_offset;
5db92a0e
AS
481 info->clock = plat->clock;
482
50bf7d03
AS
483 return 0;
484}
485
f69d3d6d
SG
486static int ns16550_serial_assign_base(struct ns16550_plat *plat,
487 fdt_addr_t base, fdt_size_t size)
720f9e1f 488{
9e6ce621 489 if (base == FDT_ADDR_T_NONE)
720f9e1f
WW
490 return -EINVAL;
491
492#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
9e6ce621 493 plat->base = base;
720f9e1f 494#else
9e6ce621 495 plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
720f9e1f 496#endif
f69d3d6d 497 plat->size = size;
720f9e1f
WW
498
499 return 0;
500}
720f9e1f 501
12e431b2
SG
502int ns16550_serial_probe(struct udevice *dev)
503{
0fd3d911 504 struct ns16550_plat *plat = dev_get_plat(dev);
d30c7209 505 struct ns16550 *const com_port = dev_get_priv(dev);
b051eecb 506 struct reset_ctl_bulk reset_bulk;
9e6ce621 507 fdt_addr_t addr;
f69d3d6d 508 fdt_addr_t size;
b051eecb
LFT
509 int ret;
510
9e6ce621
BM
511 /*
512 * If we are on PCI bus, either directly attached to a PCI root port,
caa4daa2 513 * or via a PCI bridge, assign plat->base before probing hardware.
9e6ce621
BM
514 */
515 if (device_is_on_pci_bus(dev)) {
f69d3d6d
SG
516 addr = devfdt_get_addr_pci(dev, &size);
517 ret = ns16550_serial_assign_base(plat, addr, size);
9e6ce621
BM
518 if (ret)
519 return ret;
520 }
720f9e1f 521
b051eecb
LFT
522 ret = reset_get_bulk(dev, &reset_bulk);
523 if (!ret)
524 reset_deassert_bulk(&reset_bulk);
12e431b2 525
c69cda25 526 com_port->plat = dev_get_plat(dev);
2d6bf754 527 ns16550_init(com_port, -1);
12e431b2
SG
528
529 return 0;
530}
531
79fd9281
MV
532#if CONFIG_IS_ENABLED(OF_CONTROL)
533enum {
534 PORT_NS16550 = 0,
0b060eef 535 PORT_JZ4780,
79fd9281
MV
536};
537#endif
538
414cc151 539#if CONFIG_IS_ENABLED(OF_REAL)
d1998a9f 540int ns16550_serial_of_to_plat(struct udevice *dev)
12e431b2 541{
0fd3d911 542 struct ns16550_plat *plat = dev_get_plat(dev);
0b060eef 543 const u32 port_type = dev_get_driver_data(dev);
f69d3d6d 544 fdt_size_t size = 0;
9e6ce621 545 fdt_addr_t addr;
021abf69
MY
546 struct clk clk;
547 int err;
12e431b2 548
f86580fc 549 addr = not_xpl() ? dev_read_addr_size(dev, &size) :
f69d3d6d
SG
550 dev_read_addr(dev);
551 err = ns16550_serial_assign_base(plat, addr, size);
9e6ce621
BM
552 if (err && !device_is_on_pci_bus(dev))
553 return err;
554
3d40479f
PT
555 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
556 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
4e720779 557 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
50fce1d5 558
50fce1d5 559 if (!plat->clock)
556ea53c
JK
560 plat->clock = dev_read_u32_default(dev, "clock-frequency", 0);
561 if (!plat->clock) {
562 err = clk_get_by_index(dev, 0, &clk);
563 if (!err) {
564 err = clk_get_rate(&clk);
565 if (!IS_ERR_VALUE(err))
566 plat->clock = err;
567 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
568 debug("ns16550 failed to get clock\n");
569 return err;
570 }
571 }
384b62c0 572 if (!plat->clock)
91092132 573 plat->clock = CFG_SYS_NS16550_CLK;
8e62d32e
TC
574 if (!plat->clock) {
575 debug("ns16550 clock not defined\n");
576 return -EINVAL;
577 }
12e431b2 578
17fa0326 579 plat->fcr = UART_FCR_DEFVAL;
0b060eef
MV
580 if (port_type == PORT_JZ4780)
581 plat->fcr |= UART_FCR_UME;
65f83802 582
12e431b2
SG
583 return 0;
584}
11c1a878 585#endif
12e431b2
SG
586
587const struct dm_serial_ops ns16550_serial_ops = {
588 .putc = ns16550_serial_putc,
589 .pending = ns16550_serial_pending,
590 .getc = ns16550_serial_getc,
591 .setbrg = ns16550_serial_setbrg,
50bf7d03
AS
592 .setconfig = ns16550_serial_setconfig,
593 .getinfo = ns16550_serial_getinfo,
12e431b2 594};
8e62d32e 595
414cc151 596#if CONFIG_IS_ENABLED(OF_REAL)
cc4228f9
TC
597/*
598 * Please consider existing compatible strings before adding a new
599 * one to keep this table compact. Or you may add a generic "ns16550"
600 * compatible string to your dts.
601 */
8e62d32e 602static const struct udevice_id ns16550_serial_ids[] = {
79fd9281
MV
603 { .compatible = "ns16550", .data = PORT_NS16550 },
604 { .compatible = "ns16550a", .data = PORT_NS16550 },
0b060eef 605 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
79fd9281
MV
606 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
607 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
8e62d32e
TC
608 {}
609};
414cc151 610#endif /* OF_REAL */
8e62d32e 611
b7e29834 612#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
6f8c351e
AG
613
614/* TODO([email protected]): Integrate this into a macro like CONFIG_IS_ENABLED */
615#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
8e62d32e
TC
616U_BOOT_DRIVER(ns16550_serial) = {
617 .name = "ns16550_serial",
618 .id = UCLASS_SERIAL,
414cc151 619#if CONFIG_IS_ENABLED(OF_REAL)
8e62d32e 620 .of_match = ns16550_serial_ids,
d1998a9f 621 .of_to_plat = ns16550_serial_of_to_plat,
8a8d24bd 622 .plat_auto = sizeof(struct ns16550_plat),
8e62d32e 623#endif
d30c7209 624 .priv_auto = sizeof(struct ns16550),
8e62d32e
TC
625 .probe = ns16550_serial_probe,
626 .ops = &ns16550_serial_ops,
46879196 627#if !CONFIG_IS_ENABLED(OF_CONTROL)
b7e5a643 628 .flags = DM_FLAG_PRE_RELOC,
46879196 629#endif
8e62d32e 630};
addf358b 631
bdf8fd76 632DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
b7e29834 633#endif
6f8c351e
AG
634#endif /* SERIAL_PRESENT */
635
12e431b2 636#endif /* CONFIG_DM_SERIAL */
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