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Commit | Line | Data |
---|---|---|
e85390dc WD |
1 | /* |
2 | * COM1 NS16550 support | |
a47a12be | 3 | * originally from linux source (arch/powerpc/boot/ns16550.c) |
6d0f6bcf | 4 | * modified to use CONFIG_SYS_ISA_MEM and new defines |
e85390dc WD |
5 | */ |
6 | ||
d96c2604 | 7 | #include <clock_legacy.h> |
03de305e | 8 | #include <config.h> |
50fce1d5 | 9 | #include <clk.h> |
12e431b2 SG |
10 | #include <dm.h> |
11 | #include <errno.h> | |
f7ae49fc | 12 | #include <log.h> |
e85390dc | 13 | #include <ns16550.h> |
b051eecb | 14 | #include <reset.h> |
12e431b2 | 15 | #include <serial.h> |
7f5ff034 | 16 | #include <spl.h> |
a1b322a9 | 17 | #include <watchdog.h> |
401d1c4f | 18 | #include <asm/global_data.h> |
61b29b82 | 19 | #include <linux/err.h> |
167cdad1 GR |
20 | #include <linux/types.h> |
21 | #include <asm/io.h> | |
e85390dc | 22 | |
12e431b2 SG |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
200779e3 DZ |
25 | #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ |
26 | #define UART_MCRVAL (UART_MCR_DTR | \ | |
27 | UART_MCR_RTS) /* RTS/DTR */ | |
12e431b2 | 28 | |
2e2c514a | 29 | #if !CONFIG_IS_ENABLED(DM_SERIAL) |
167cdad1 | 30 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
f8df9d0d SG |
31 | #define serial_out(x, y) outb(x, (ulong)y) |
32 | #define serial_in(y) inb((ulong)y) | |
79df1208 | 33 | #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) |
f8df9d0d SG |
34 | #define serial_out(x, y) out_be32(y, x) |
35 | #define serial_in(y) in_be32(y) | |
79df1208 | 36 | #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) |
f8df9d0d SG |
37 | #define serial_out(x, y) out_le32(y, x) |
38 | #define serial_in(y) in_le32(y) | |
167cdad1 | 39 | #else |
f8df9d0d SG |
40 | #define serial_out(x, y) writeb(x, y) |
41 | #define serial_in(y) readb(y) | |
167cdad1 | 42 | #endif |
12e431b2 | 43 | #endif /* !CONFIG_DM_SERIAL */ |
e85390dc | 44 | |
f899cc14 | 45 | #if defined(CONFIG_ARCH_KEYSTONE) |
ef509b90 VA |
46 | #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 |
47 | #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) | |
d57dee57 KM |
48 | #undef UART_MCRVAL |
49 | #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL | |
50 | #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) | |
51 | #else | |
52 | #define UART_MCRVAL (UART_MCR_RTS) | |
53 | #endif | |
ef509b90 VA |
54 | #endif |
55 | ||
6e7df1d1 TR |
56 | #ifndef CFG_SYS_NS16550_IER |
57 | #define CFG_SYS_NS16550_IER 0x00 | |
58 | #endif /* CFG_SYS_NS16550_IER */ | |
a160ea0b | 59 | |
363e6da1 | 60 | static inline void serial_out_shift(void *addr, int shift, int value) |
76571674 | 61 | { |
12e431b2 | 62 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
1f77690e | 63 | outb(value, (ulong)addr); |
78b7d37b | 64 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) |
12e431b2 SG |
65 | out_le32(addr, value); |
66 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) | |
67 | out_be32(addr, value); | |
90914008 SG |
68 | #elif defined(CONFIG_SYS_NS16550_MEM32) |
69 | writel(value, addr); | |
12e431b2 | 70 | #elif defined(CONFIG_SYS_BIG_ENDIAN) |
76571674 | 71 | writeb(value, addr + (1 << shift) - 1); |
12e431b2 SG |
72 | #else |
73 | writeb(value, addr); | |
74 | #endif | |
75 | } | |
76 | ||
363e6da1 | 77 | static inline int serial_in_shift(void *addr, int shift) |
12e431b2 | 78 | { |
12e431b2 | 79 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
1f77690e | 80 | return inb((ulong)addr); |
78b7d37b | 81 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) |
12e431b2 SG |
82 | return in_le32(addr); |
83 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) | |
84 | return in_be32(addr); | |
90914008 SG |
85 | #elif defined(CONFIG_SYS_NS16550_MEM32) |
86 | return readl(addr); | |
12e431b2 | 87 | #elif defined(CONFIG_SYS_BIG_ENDIAN) |
20379c11 | 88 | return readb(addr + (1 << shift) - 1); |
12e431b2 SG |
89 | #else |
90 | return readb(addr); | |
91 | #endif | |
92 | } | |
93 | ||
2e2c514a | 94 | #if CONFIG_IS_ENABLED(DM_SERIAL) |
fa4ce723 | 95 | |
91092132 TR |
96 | #ifndef CFG_SYS_NS16550_CLK |
97 | #define CFG_SYS_NS16550_CLK 0 | |
fa4ce723 MV |
98 | #endif |
99 | ||
62cbde4c SG |
100 | /* |
101 | * Use this #ifdef for now since many platforms don't define in(), out(), | |
102 | * out_le32(), etc. but we don't have #defines to indicate this. | |
103 | * | |
104 | * TODO([email protected]): Add CONFIG options to indicate what I/O is available | |
105 | * on a platform | |
106 | */ | |
107 | #ifdef CONFIG_NS16550_DYNAMIC | |
8a8d24bd | 108 | static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr, |
62cbde4c SG |
109 | int value) |
110 | { | |
111 | if (plat->flags & NS16550_FLAG_IO) { | |
112 | outb(value, addr); | |
113 | } else if (plat->reg_width == 4) { | |
114 | if (plat->flags & NS16550_FLAG_ENDIAN) { | |
115 | if (plat->flags & NS16550_FLAG_BE) | |
116 | out_be32(addr, value); | |
117 | else | |
118 | out_le32(addr, value); | |
119 | } else { | |
120 | writel(value, addr); | |
121 | } | |
122 | } else if (plat->flags & NS16550_FLAG_BE) { | |
123 | writeb(value, addr + (1 << plat->reg_shift) - 1); | |
124 | } else { | |
125 | writeb(value, addr); | |
126 | } | |
127 | } | |
128 | ||
8a8d24bd | 129 | static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) |
62cbde4c SG |
130 | { |
131 | if (plat->flags & NS16550_FLAG_IO) { | |
132 | return inb(addr); | |
133 | } else if (plat->reg_width == 4) { | |
134 | if (plat->flags & NS16550_FLAG_ENDIAN) { | |
135 | if (plat->flags & NS16550_FLAG_BE) | |
136 | return in_be32(addr); | |
137 | else | |
138 | return in_le32(addr); | |
139 | } else { | |
140 | return readl(addr); | |
141 | } | |
142 | } else if (plat->flags & NS16550_FLAG_BE) { | |
143 | return readb(addr + (1 << plat->reg_shift) - 1); | |
144 | } else { | |
145 | return readb(addr); | |
146 | } | |
147 | } | |
148 | #else | |
8a8d24bd | 149 | static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr, |
62cbde4c SG |
150 | int value) |
151 | { | |
152 | } | |
153 | ||
8a8d24bd | 154 | static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) |
62cbde4c SG |
155 | { |
156 | return 0; | |
157 | } | |
158 | ||
159 | #endif /* CONFIG_NS16550_DYNAMIC */ | |
160 | ||
d30c7209 | 161 | static void ns16550_writeb(struct ns16550 *port, int offset, int value) |
76571674 | 162 | { |
8a8d24bd | 163 | struct ns16550_plat *plat = port->plat; |
76571674 SG |
164 | unsigned char *addr; |
165 | ||
166 | offset *= 1 << plat->reg_shift; | |
62cbde4c | 167 | addr = (unsigned char *)plat->base + offset + plat->reg_offset; |
df8ec55d | 168 | |
62cbde4c SG |
169 | if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) |
170 | serial_out_dynamic(plat, addr, value); | |
171 | else | |
172 | serial_out_shift(addr, plat->reg_shift, value); | |
76571674 SG |
173 | } |
174 | ||
d30c7209 | 175 | static int ns16550_readb(struct ns16550 *port, int offset) |
76571674 | 176 | { |
8a8d24bd | 177 | struct ns16550_plat *plat = port->plat; |
76571674 SG |
178 | unsigned char *addr; |
179 | ||
180 | offset *= 1 << plat->reg_shift; | |
62cbde4c | 181 | addr = (unsigned char *)plat->base + offset + plat->reg_offset; |
76571674 | 182 | |
62cbde4c SG |
183 | if (IS_ENABLED(CONFIG_NS16550_DYNAMIC)) |
184 | return serial_in_dynamic(plat, addr); | |
185 | else | |
186 | return serial_in_shift(addr, plat->reg_shift); | |
76571674 SG |
187 | } |
188 | ||
d30c7209 | 189 | static u32 ns16550_getfcr(struct ns16550 *port) |
65f83802 | 190 | { |
8a8d24bd | 191 | struct ns16550_plat *plat = port->plat; |
65f83802 MV |
192 | |
193 | return plat->fcr; | |
194 | } | |
195 | ||
12e431b2 SG |
196 | /* We can clean these up once everything is moved to driver model */ |
197 | #define serial_out(value, addr) \ | |
363e6da1 SG |
198 | ns16550_writeb(com_port, \ |
199 | (unsigned char *)addr - (unsigned char *)com_port, value) | |
12e431b2 | 200 | #define serial_in(addr) \ |
363e6da1 SG |
201 | ns16550_readb(com_port, \ |
202 | (unsigned char *)addr - (unsigned char *)com_port) | |
65f83802 | 203 | #else |
d30c7209 | 204 | static u32 ns16550_getfcr(struct ns16550 *port) |
65f83802 | 205 | { |
17fa0326 | 206 | return UART_FCR_DEFVAL; |
65f83802 | 207 | } |
12e431b2 SG |
208 | #endif |
209 | ||
d30c7209 | 210 | int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate) |
fa54eb12 SG |
211 | { |
212 | const unsigned int mode_x_div = 16; | |
213 | ||
21d00436 SG |
214 | return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); |
215 | } | |
216 | ||
2d6bf754 | 217 | static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) |
8bbe33c8 | 218 | { |
9ad3b049 SG |
219 | /* to keep serial format, read lcr before writing BKSE */ |
220 | int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; | |
221 | ||
222 | serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); | |
8bbe33c8 SG |
223 | serial_out(baud_divisor & 0xff, &com_port->dll); |
224 | serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); | |
9ad3b049 | 225 | serial_out(lcr_val, &com_port->lcr); |
8bbe33c8 SG |
226 | } |
227 | ||
2d6bf754 | 228 | void ns16550_init(struct ns16550 *com_port, int baud_divisor) |
e85390dc | 229 | { |
956a8bae GG |
230 | #if (defined(CONFIG_SPL_BUILD) && \ |
231 | (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) | |
fd2aeac5 | 232 | /* |
956a8bae GG |
233 | * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode |
234 | * before SPL starts only THRE bit is set. We have to empty the | |
235 | * transmitter before initialization starts. | |
fd2aeac5 MH |
236 | */ |
237 | if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) | |
238 | == UART_LSR_THRE) { | |
12e431b2 | 239 | if (baud_divisor != -1) |
2d6bf754 | 240 | ns16550_setbrg(com_port, baud_divisor); |
1c16606a PD |
241 | else { |
242 | // Re-use old baud rate divisor to flush transmit reg. | |
243 | const int dll = serial_in(&com_port->dll); | |
244 | const int dlm = serial_in(&com_port->dlm); | |
245 | const int divisor = dll | (dlm << 8); | |
2d6bf754 | 246 | ns16550_setbrg(com_port, divisor); |
1c16606a | 247 | } |
fd2aeac5 MH |
248 | serial_out(0, &com_port->mdr1); |
249 | } | |
250 | #endif | |
251 | ||
cb55b332 SW |
252 | while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) |
253 | ; | |
254 | ||
6e7df1d1 | 255 | serial_out(CFG_SYS_NS16550_IER, &com_port->ier); |
5d754197 | 256 | #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL) |
167cdad1 | 257 | serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ |
945af8d7 | 258 | #endif |
b051eecb | 259 | |
167cdad1 | 260 | serial_out(UART_MCRVAL, &com_port->mcr); |
65f83802 | 261 | serial_out(ns16550_getfcr(com_port), &com_port->fcr); |
9ad3b049 SG |
262 | /* initialize serial config to 8N1 before writing baudrate */ |
263 | serial_out(UART_LCRVAL, &com_port->lcr); | |
12e431b2 | 264 | if (baud_divisor != -1) |
2d6bf754 | 265 | ns16550_setbrg(com_port, baud_divisor); |
5d754197 LV |
266 | #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ |
267 | defined(CONFIG_OMAP_SERIAL) | |
f8df9d0d SG |
268 | /* /16 is proper to hit 115200 with 48MHz */ |
269 | serial_out(0, &com_port->mdr1); | |
89024ddc | 270 | #endif |
f899cc14 | 271 | #if defined(CONFIG_ARCH_KEYSTONE) |
ef509b90 VA |
272 | serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); |
273 | #endif | |
e85390dc WD |
274 | } |
275 | ||
57c3afbc | 276 | #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) |
2d6bf754 | 277 | void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) |
e85390dc | 278 | { |
6e7df1d1 | 279 | serial_out(CFG_SYS_NS16550_IER, &com_port->ier); |
2d6bf754 | 280 | ns16550_setbrg(com_port, 0); |
167cdad1 | 281 | serial_out(UART_MCRVAL, &com_port->mcr); |
65f83802 | 282 | serial_out(ns16550_getfcr(com_port), &com_port->fcr); |
2d6bf754 | 283 | ns16550_setbrg(com_port, baud_divisor); |
e85390dc | 284 | } |
57c3afbc | 285 | #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ |
e85390dc | 286 | |
2d6bf754 | 287 | void ns16550_putc(struct ns16550 *com_port, char c) |
e85390dc | 288 | { |
f8df9d0d SG |
289 | while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) |
290 | ; | |
167cdad1 | 291 | serial_out(c, &com_port->thr); |
1a2d9b30 SR |
292 | |
293 | /* | |
294 | * Call watchdog_reset() upon newline. This is done here in putc | |
295 | * since the environment code uses a single puts() to print the complete | |
296 | * environment upon "printenv". So we can't put this watchdog call | |
297 | * in puts(). | |
298 | */ | |
299 | if (c == '\n') | |
29caf930 | 300 | schedule(); |
e85390dc WD |
301 | } |
302 | ||
57c3afbc | 303 | #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) |
2d6bf754 | 304 | char ns16550_getc(struct ns16550 *com_port) |
e85390dc | 305 | { |
167cdad1 | 306 | while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { |
f2041388 | 307 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) |
232c150a WD |
308 | extern void usbtty_poll(void); |
309 | usbtty_poll(); | |
310 | #endif | |
29caf930 | 311 | schedule(); |
232c150a | 312 | } |
167cdad1 | 313 | return serial_in(&com_port->rbr); |
e85390dc WD |
314 | } |
315 | ||
2d6bf754 | 316 | int ns16550_tstc(struct ns16550 *com_port) |
e85390dc | 317 | { |
f8df9d0d | 318 | return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; |
e85390dc WD |
319 | } |
320 | ||
57c3afbc | 321 | #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ |
12e431b2 | 322 | |
21d00436 SG |
323 | #ifdef CONFIG_DEBUG_UART_NS16550 |
324 | ||
325 | #include <debug_uart.h> | |
326 | ||
97b05973 | 327 | static inline void _debug_uart_init(void) |
21d00436 | 328 | { |
d293759d | 329 | struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); |
21d00436 SG |
330 | int baud_divisor; |
331 | ||
5e998b4d T |
332 | /* Wait until tx buffer is empty */ |
333 | while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT)) | |
334 | ; | |
335 | ||
21d00436 SG |
336 | /* |
337 | * We copy the code from above because it is already horribly messy. | |
338 | * Trying to refactor to nicely remove the duplication doesn't seem | |
339 | * feasible. The better fix is to move all users of this driver to | |
340 | * driver model. | |
341 | */ | |
03c6f176 MV |
342 | baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, |
343 | CONFIG_BAUDRATE); | |
6e7df1d1 | 344 | serial_dout(&com_port->ier, CFG_SYS_NS16550_IER); |
6e780c7a | 345 | serial_dout(&com_port->mcr, UART_MCRVAL); |
17fa0326 | 346 | serial_dout(&com_port->fcr, UART_FCR_DEFVAL); |
6e780c7a SG |
347 | |
348 | serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); | |
349 | serial_dout(&com_port->dll, baud_divisor & 0xff); | |
350 | serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); | |
351 | serial_dout(&com_port->lcr, UART_LCRVAL); | |
21d00436 SG |
352 | } |
353 | ||
d30c7209 | 354 | static inline int NS16550_read_baud_divisor(struct ns16550 *com_port) |
c4448bdc SG |
355 | { |
356 | int ret; | |
357 | ||
358 | serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); | |
359 | ret = serial_din(&com_port->dll) & 0xff; | |
360 | ret |= (serial_din(&com_port->dlm) & 0xff) << 8; | |
361 | serial_dout(&com_port->lcr, UART_LCRVAL); | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
21d00436 SG |
366 | static inline void _debug_uart_putc(int ch) |
367 | { | |
d293759d | 368 | struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); |
21d00436 | 369 | |
c4448bdc SG |
370 | while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) { |
371 | #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED | |
372 | if (!NS16550_read_baud_divisor(com_port)) | |
373 | return; | |
374 | #endif | |
375 | } | |
6e780c7a | 376 | serial_dout(&com_port->thr, ch); |
21d00436 SG |
377 | } |
378 | ||
379 | DEBUG_UART_FUNCS | |
380 | ||
381 | #endif | |
382 | ||
2e2c514a | 383 | #if CONFIG_IS_ENABLED(DM_SERIAL) |
12e431b2 SG |
384 | static int ns16550_serial_putc(struct udevice *dev, const char ch) |
385 | { | |
d30c7209 | 386 | struct ns16550 *const com_port = dev_get_priv(dev); |
12e431b2 SG |
387 | |
388 | if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) | |
389 | return -EAGAIN; | |
390 | serial_out(ch, &com_port->thr); | |
391 | ||
392 | /* | |
393 | * Call watchdog_reset() upon newline. This is done here in putc | |
394 | * since the environment code uses a single puts() to print the complete | |
395 | * environment upon "printenv". So we can't put this watchdog call | |
396 | * in puts(). | |
397 | */ | |
398 | if (ch == '\n') | |
29caf930 | 399 | schedule(); |
12e431b2 SG |
400 | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static int ns16550_serial_pending(struct udevice *dev, bool input) | |
405 | { | |
d30c7209 | 406 | struct ns16550 *const com_port = dev_get_priv(dev); |
12e431b2 SG |
407 | |
408 | if (input) | |
4dbf9bed | 409 | return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0; |
12e431b2 | 410 | else |
4dbf9bed | 411 | return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; |
12e431b2 SG |
412 | } |
413 | ||
414 | static int ns16550_serial_getc(struct udevice *dev) | |
415 | { | |
d30c7209 | 416 | struct ns16550 *const com_port = dev_get_priv(dev); |
7fded0ce SR |
417 | |
418 | if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) | |
12e431b2 SG |
419 | return -EAGAIN; |
420 | ||
7fded0ce | 421 | return serial_in(&com_port->rbr); |
12e431b2 SG |
422 | } |
423 | ||
424 | static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) | |
425 | { | |
d30c7209 | 426 | struct ns16550 *const com_port = dev_get_priv(dev); |
8a8d24bd | 427 | struct ns16550_plat *plat = com_port->plat; |
12e431b2 SG |
428 | int clock_divisor; |
429 | ||
430 | clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); | |
431 | ||
2d6bf754 | 432 | ns16550_setbrg(com_port, clock_divisor); |
12e431b2 SG |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
9ad3b049 SG |
437 | static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) |
438 | { | |
d30c7209 | 439 | struct ns16550 *const com_port = dev_get_priv(dev); |
9ad3b049 SG |
440 | int lcr_val = UART_LCR_WLS_8; |
441 | uint parity = SERIAL_GET_PARITY(serial_config); | |
442 | uint bits = SERIAL_GET_BITS(serial_config); | |
443 | uint stop = SERIAL_GET_STOP(serial_config); | |
444 | ||
445 | /* | |
446 | * only parity config is implemented, check if other serial settings | |
447 | * are the default one. | |
448 | */ | |
449 | if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP) | |
450 | return -ENOTSUPP; /* not supported in driver*/ | |
451 | ||
452 | switch (parity) { | |
453 | case SERIAL_PAR_NONE: | |
454 | /* no bits to add */ | |
455 | break; | |
456 | case SERIAL_PAR_ODD: | |
457 | lcr_val |= UART_LCR_PEN; | |
458 | break; | |
459 | case SERIAL_PAR_EVEN: | |
460 | lcr_val |= UART_LCR_PEN | UART_LCR_EPS; | |
461 | break; | |
462 | default: | |
463 | return -ENOTSUPP; /* not supported in driver*/ | |
464 | } | |
465 | ||
466 | serial_out(lcr_val, &com_port->lcr); | |
467 | return 0; | |
468 | } | |
469 | ||
50bf7d03 AS |
470 | static int ns16550_serial_getinfo(struct udevice *dev, |
471 | struct serial_device_info *info) | |
472 | { | |
d30c7209 | 473 | struct ns16550 *const com_port = dev_get_priv(dev); |
8a8d24bd | 474 | struct ns16550_plat *plat = com_port->plat; |
50bf7d03 | 475 | |
7f5ff034 SG |
476 | /* save code size */ |
477 | if (!spl_in_proper()) | |
478 | return -ENOSYS; | |
479 | ||
50bf7d03 AS |
480 | info->type = SERIAL_CHIP_16550_COMPATIBLE; |
481 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED | |
482 | info->addr_space = SERIAL_ADDRESS_SPACE_IO; | |
483 | #else | |
484 | info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY; | |
485 | #endif | |
486 | info->addr = plat->base; | |
f69d3d6d | 487 | info->size = plat->size; |
50bf7d03 AS |
488 | info->reg_width = plat->reg_width; |
489 | info->reg_shift = plat->reg_shift; | |
490 | info->reg_offset = plat->reg_offset; | |
5db92a0e AS |
491 | info->clock = plat->clock; |
492 | ||
50bf7d03 AS |
493 | return 0; |
494 | } | |
495 | ||
f69d3d6d SG |
496 | static int ns16550_serial_assign_base(struct ns16550_plat *plat, |
497 | fdt_addr_t base, fdt_size_t size) | |
720f9e1f | 498 | { |
9e6ce621 | 499 | if (base == FDT_ADDR_T_NONE) |
720f9e1f WW |
500 | return -EINVAL; |
501 | ||
502 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED | |
9e6ce621 | 503 | plat->base = base; |
720f9e1f | 504 | #else |
9e6ce621 | 505 | plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); |
720f9e1f | 506 | #endif |
f69d3d6d | 507 | plat->size = size; |
720f9e1f WW |
508 | |
509 | return 0; | |
510 | } | |
720f9e1f | 511 | |
12e431b2 SG |
512 | int ns16550_serial_probe(struct udevice *dev) |
513 | { | |
0fd3d911 | 514 | struct ns16550_plat *plat = dev_get_plat(dev); |
d30c7209 | 515 | struct ns16550 *const com_port = dev_get_priv(dev); |
b051eecb | 516 | struct reset_ctl_bulk reset_bulk; |
9e6ce621 | 517 | fdt_addr_t addr; |
f69d3d6d | 518 | fdt_addr_t size; |
b051eecb LFT |
519 | int ret; |
520 | ||
9e6ce621 BM |
521 | /* |
522 | * If we are on PCI bus, either directly attached to a PCI root port, | |
caa4daa2 | 523 | * or via a PCI bridge, assign plat->base before probing hardware. |
9e6ce621 BM |
524 | */ |
525 | if (device_is_on_pci_bus(dev)) { | |
f69d3d6d SG |
526 | addr = devfdt_get_addr_pci(dev, &size); |
527 | ret = ns16550_serial_assign_base(plat, addr, size); | |
9e6ce621 BM |
528 | if (ret) |
529 | return ret; | |
530 | } | |
720f9e1f | 531 | |
b051eecb LFT |
532 | ret = reset_get_bulk(dev, &reset_bulk); |
533 | if (!ret) | |
534 | reset_deassert_bulk(&reset_bulk); | |
12e431b2 | 535 | |
c69cda25 | 536 | com_port->plat = dev_get_plat(dev); |
2d6bf754 | 537 | ns16550_init(com_port, -1); |
12e431b2 SG |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
79fd9281 MV |
542 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
543 | enum { | |
544 | PORT_NS16550 = 0, | |
0b060eef | 545 | PORT_JZ4780, |
79fd9281 MV |
546 | }; |
547 | #endif | |
548 | ||
414cc151 | 549 | #if CONFIG_IS_ENABLED(OF_REAL) |
d1998a9f | 550 | int ns16550_serial_of_to_plat(struct udevice *dev) |
12e431b2 | 551 | { |
0fd3d911 | 552 | struct ns16550_plat *plat = dev_get_plat(dev); |
0b060eef | 553 | const u32 port_type = dev_get_driver_data(dev); |
f69d3d6d | 554 | fdt_size_t size = 0; |
9e6ce621 | 555 | fdt_addr_t addr; |
021abf69 MY |
556 | struct clk clk; |
557 | int err; | |
12e431b2 | 558 | |
f69d3d6d SG |
559 | addr = spl_in_proper() ? dev_read_addr_size(dev, &size) : |
560 | dev_read_addr(dev); | |
561 | err = ns16550_serial_assign_base(plat, addr, size); | |
9e6ce621 BM |
562 | if (err && !device_is_on_pci_bus(dev)) |
563 | return err; | |
564 | ||
3d40479f PT |
565 | plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); |
566 | plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); | |
4e720779 | 567 | plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); |
50fce1d5 PB |
568 | |
569 | err = clk_get_by_index(dev, 0, &clk); | |
570 | if (!err) { | |
571 | err = clk_get_rate(&clk); | |
572 | if (!IS_ERR_VALUE(err)) | |
573 | plat->clock = err; | |
ab895d6a | 574 | } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { |
50fce1d5 PB |
575 | debug("ns16550 failed to get clock\n"); |
576 | return err; | |
577 | } | |
578 | ||
579 | if (!plat->clock) | |
3d40479f | 580 | plat->clock = dev_read_u32_default(dev, "clock-frequency", |
91092132 | 581 | CFG_SYS_NS16550_CLK); |
384b62c0 | 582 | if (!plat->clock) |
91092132 | 583 | plat->clock = CFG_SYS_NS16550_CLK; |
8e62d32e TC |
584 | if (!plat->clock) { |
585 | debug("ns16550 clock not defined\n"); | |
586 | return -EINVAL; | |
587 | } | |
12e431b2 | 588 | |
17fa0326 | 589 | plat->fcr = UART_FCR_DEFVAL; |
0b060eef MV |
590 | if (port_type == PORT_JZ4780) |
591 | plat->fcr |= UART_FCR_UME; | |
65f83802 | 592 | |
12e431b2 SG |
593 | return 0; |
594 | } | |
11c1a878 | 595 | #endif |
12e431b2 SG |
596 | |
597 | const struct dm_serial_ops ns16550_serial_ops = { | |
598 | .putc = ns16550_serial_putc, | |
599 | .pending = ns16550_serial_pending, | |
600 | .getc = ns16550_serial_getc, | |
601 | .setbrg = ns16550_serial_setbrg, | |
50bf7d03 AS |
602 | .setconfig = ns16550_serial_setconfig, |
603 | .getinfo = ns16550_serial_getinfo, | |
12e431b2 | 604 | }; |
8e62d32e | 605 | |
414cc151 | 606 | #if CONFIG_IS_ENABLED(OF_REAL) |
cc4228f9 TC |
607 | /* |
608 | * Please consider existing compatible strings before adding a new | |
609 | * one to keep this table compact. Or you may add a generic "ns16550" | |
610 | * compatible string to your dts. | |
611 | */ | |
8e62d32e | 612 | static const struct udevice_id ns16550_serial_ids[] = { |
79fd9281 MV |
613 | { .compatible = "ns16550", .data = PORT_NS16550 }, |
614 | { .compatible = "ns16550a", .data = PORT_NS16550 }, | |
0b060eef | 615 | { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, |
79fd9281 MV |
616 | { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, |
617 | { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, | |
8e62d32e TC |
618 | {} |
619 | }; | |
414cc151 | 620 | #endif /* OF_REAL */ |
8e62d32e | 621 | |
b7e29834 | 622 | #if CONFIG_IS_ENABLED(SERIAL_PRESENT) |
6f8c351e AG |
623 | |
624 | /* TODO([email protected]): Integrate this into a macro like CONFIG_IS_ENABLED */ | |
625 | #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) | |
8e62d32e TC |
626 | U_BOOT_DRIVER(ns16550_serial) = { |
627 | .name = "ns16550_serial", | |
628 | .id = UCLASS_SERIAL, | |
414cc151 | 629 | #if CONFIG_IS_ENABLED(OF_REAL) |
8e62d32e | 630 | .of_match = ns16550_serial_ids, |
d1998a9f | 631 | .of_to_plat = ns16550_serial_of_to_plat, |
8a8d24bd | 632 | .plat_auto = sizeof(struct ns16550_plat), |
8e62d32e | 633 | #endif |
d30c7209 | 634 | .priv_auto = sizeof(struct ns16550), |
8e62d32e TC |
635 | .probe = ns16550_serial_probe, |
636 | .ops = &ns16550_serial_ops, | |
46879196 | 637 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
b7e5a643 | 638 | .flags = DM_FLAG_PRE_RELOC, |
46879196 | 639 | #endif |
8e62d32e | 640 | }; |
addf358b | 641 | |
bdf8fd76 | 642 | DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart) |
b7e29834 | 643 | #endif |
6f8c351e AG |
644 | #endif /* SERIAL_PRESENT */ |
645 | ||
12e431b2 | 646 | #endif /* CONFIG_DM_SERIAL */ |