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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # Multifunction miscellaneous devices | |
3 | # | |
4 | ||
5 | menu "Multifunction device drivers" | |
6 | ||
4395e06e TC |
7 | config MISC |
8 | bool "Enable Driver Model for Misc drivers" | |
9 | depends on DM | |
10 | help | |
11 | Enable driver model for miscellaneous devices. This class is | |
12 | used only for those do not fit other more general classes. A | |
13 | set of generic read, write and ioctl methods may be used to | |
14 | access the device. | |
15 | ||
aaba703f SG |
16 | config SPL_MISC |
17 | bool "Enable Driver Model for Misc drivers in SPL" | |
18 | depends on SPL_DM | |
38127741 | 19 | default MISC |
aaba703f SG |
20 | help |
21 | Enable driver model for miscellaneous devices. This class is | |
22 | used only for those do not fit other more general classes. A | |
23 | set of generic read, write and ioctl methods may be used to | |
24 | access the device. | |
25 | ||
26 | config TPL_MISC | |
27 | bool "Enable Driver Model for Misc drivers in TPL" | |
28 | depends on TPL_DM | |
38127741 SA |
29 | default MISC |
30 | help | |
31 | Enable driver model for miscellaneous devices. This class is | |
32 | used only for those do not fit other more general classes. A | |
33 | set of generic read, write and ioctl methods may be used to | |
34 | access the device. | |
35 | ||
36 | config VPL_MISC | |
37 | bool "Enable Driver Model for Misc drivers in VPL" | |
38 | depends on VPL_DM | |
39 | default MISC | |
aaba703f SG |
40 | help |
41 | Enable driver model for miscellaneous devices. This class is | |
42 | used only for those do not fit other more general classes. A | |
43 | set of generic read, write and ioctl methods may be used to | |
44 | access the device. | |
45 | ||
c8ce7ba8 SA |
46 | config NVMEM |
47 | bool "NVMEM support" | |
48 | help | |
49 | This adds support for a common interface to different types of | |
50 | non-volatile memory. Consumers can use nvmem-cells properties to look | |
51 | up hardware configuration data such as MAC addresses and calibration | |
52 | settings. | |
53 | ||
54 | config SPL_NVMEM | |
55 | bool "NVMEM support in SPL" | |
56 | help | |
57 | This adds support for a common interface to different types of | |
58 | non-volatile memory. Consumers can use nvmem-cells properties to look | |
59 | up hardware configuration data such as MAC addresses and calibration | |
60 | settings. | |
61 | ||
ca844dd8 TC |
62 | config ALTERA_SYSID |
63 | bool "Altera Sysid support" | |
64 | depends on MISC | |
65 | help | |
66 | Select this to enable a sysid for Altera devices. Please find | |
67 | details on the "Embedded Peripherals IP User Guide" of Altera. | |
68 | ||
aa5eb9a3 MB |
69 | config ATSHA204A |
70 | bool "Support for Atmel ATSHA204A module" | |
467f0c4d | 71 | select BITREVERSE |
aa5eb9a3 MB |
72 | depends on MISC |
73 | help | |
74 | Enable support for I2C connected Atmel's ATSHA204A | |
75 | CryptoAuthentication module found for example on the Turris Omnia | |
76 | board. | |
77 | ||
8479b9e6 TH |
78 | config GATEWORKS_SC |
79 | bool "Gateworks System Controller Support" | |
80 | depends on MISC | |
81 | help | |
82 | Enable access for the Gateworks System Controller used on Gateworks | |
83 | boards to provide a boot watchdog, power control, temperature monitor, | |
84 | voltage ADCs, and EEPROM. | |
85 | ||
49cd8e85 PT |
86 | config ROCKCHIP_EFUSE |
87 | bool "Rockchip e-fuse support" | |
88 | depends on MISC | |
89 | help | |
90 | Enable (read-only) access for the e-fuse block found in Rockchip | |
91 | SoCs: accesses can either be made using byte addressing and a length | |
92 | or through child-nodes that are generated based on the e-fuse map | |
93 | retrieved from the DTS. | |
94 | ||
a907dc3f FX |
95 | config ROCKCHIP_OTP |
96 | bool "Rockchip OTP Support" | |
97 | depends on MISC | |
98 | help | |
99 | Enable (read-only) access for the one-time-programmable memory block | |
100 | found in Rockchip SoCs: accesses can either be made using byte | |
101 | addressing and a length or through child-nodes that are generated | |
102 | based on the e-fuse map retrieved from the DTS. | |
103 | ||
09329df2 JK |
104 | config ROCKCHIP_IODOMAIN |
105 | bool "Rockchip IO-domain driver support" | |
106 | depends on DM_REGULATOR && ARCH_ROCKCHIP | |
f43b6d47 | 107 | default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568 |
09329df2 JK |
108 | help |
109 | Enable support for IO-domains in Rockchip SoCs. It is necessary | |
110 | for the IO-domain setting of the SoC to match the voltage supplied | |
111 | by the regulators. | |
112 | ||
05307213 PP |
113 | config SIFIVE_OTP |
114 | bool "SiFive eMemory OTP driver" | |
115 | depends on MISC | |
116 | help | |
117 | Enable support for reading and writing the eMemory OTP on the | |
118 | SiFive SoCs. | |
119 | ||
d9136520 TR |
120 | config SMSC_LPC47M |
121 | bool "LPC47M SMSC driver" | |
122 | ||
123 | config SMSC_SIO1007 | |
124 | bool "SIO1007 SMSC driver" | |
125 | ||
0fabfeb2 LD |
126 | config VEXPRESS_CONFIG |
127 | bool "Enable support for Arm Versatile Express config bus" | |
128 | depends on MISC | |
129 | help | |
130 | If you say Y here, you will get support for accessing the | |
131 | configuration bus on the Arm Versatile Express boards via | |
132 | a sysreg driver. | |
133 | ||
fb5cfbe1 SG |
134 | config CBMEM_CONSOLE |
135 | bool "Write console output to coreboot cbmem" | |
136 | depends on X86 | |
137 | help | |
138 | Enables console output to the cbmem console, which is a memory | |
139 | region set up by coreboot to hold a record of all console output. | |
140 | Enable this only if booting from coreboot. | |
141 | ||
6fb9ac15 SG |
142 | config CMD_CROS_EC |
143 | bool "Enable crosec command" | |
144 | depends on CROS_EC | |
145 | help | |
146 | Enable command-line access to the Chrome OS EC (Embedded | |
147 | Controller). This provides the 'crosec' command which has | |
148 | a number of sub-commands for performing EC tasks such as | |
149 | updating its flash, accessing a small saved context area | |
150 | and talking to the I2C bus behind the EC (if there is one). | |
151 | ||
152 | config CROS_EC | |
153 | bool "Enable Chrome OS EC" | |
154 | help | |
155 | Enable access to the Chrome OS EC. This is a separate | |
156 | microcontroller typically available on a SPI bus on Chromebooks. It | |
157 | provides access to the keyboard, some internal storage and may | |
158 | control access to the battery and main PMIC depending on the | |
159 | device. You can use the 'crosec' command to access it. | |
160 | ||
aaba703f SG |
161 | config SPL_CROS_EC |
162 | bool "Enable Chrome OS EC in SPL" | |
8a1ab5e8 | 163 | depends on SPL_MISC |
aaba703f SG |
164 | help |
165 | Enable access to the Chrome OS EC in SPL. This is a separate | |
166 | microcontroller typically available on a SPI bus on Chromebooks. It | |
167 | provides access to the keyboard, some internal storage and may | |
168 | control access to the battery and main PMIC depending on the | |
169 | device. You can use the 'crosec' command to access it. | |
170 | ||
171 | config TPL_CROS_EC | |
172 | bool "Enable Chrome OS EC in TPL" | |
8a1ab5e8 | 173 | depends on TPL_MISC |
aaba703f SG |
174 | help |
175 | Enable access to the Chrome OS EC in TPL. This is a separate | |
176 | microcontroller typically available on a SPI bus on Chromebooks. It | |
177 | provides access to the keyboard, some internal storage and may | |
178 | control access to the battery and main PMIC depending on the | |
179 | device. You can use the 'crosec' command to access it. | |
180 | ||
747093dd SG |
181 | config VPL_CROS_EC |
182 | bool "Enable Chrome OS EC in VPL" | |
8a1ab5e8 | 183 | depends on VPL_MISC |
747093dd SG |
184 | help |
185 | Enable access to the Chrome OS EC in VPL. This is a separate | |
186 | microcontroller typically available on a SPI bus on Chromebooks. It | |
187 | provides access to the keyboard, some internal storage and may | |
188 | control access to the battery and main PMIC depending on the | |
189 | device. You can use the 'crosec' command to access it. | |
190 | ||
6fb9ac15 SG |
191 | config CROS_EC_I2C |
192 | bool "Enable Chrome OS EC I2C driver" | |
193 | depends on CROS_EC | |
194 | help | |
195 | Enable I2C access to the Chrome OS EC. This is used on older | |
196 | ARM Chromebooks such as snow and spring before the standard bus | |
197 | changed to SPI. The EC will accept commands across the I2C using | |
198 | a special message protocol, and provide responses. | |
199 | ||
200 | config CROS_EC_LPC | |
201 | bool "Enable Chrome OS EC LPC driver" | |
202 | depends on CROS_EC | |
203 | help | |
204 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
205 | Chromebooks such as link and falco. The keyboard is provided | |
206 | through a legacy port interface, so on x86 machines the main | |
207 | function of the EC is power and thermal management. | |
208 | ||
aaba703f SG |
209 | config SPL_CROS_EC_LPC |
210 | bool "Enable Chrome OS EC LPC driver in SPL" | |
8a1ab5e8 | 211 | depends on CROS_EC && SPL_MISC |
aaba703f SG |
212 | help |
213 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
214 | Chromebooks such as link and falco. The keyboard is provided | |
215 | through a legacy port interface, so on x86 machines the main | |
216 | function of the EC is power and thermal management. | |
217 | ||
218 | config TPL_CROS_EC_LPC | |
219 | bool "Enable Chrome OS EC LPC driver in TPL" | |
8a1ab5e8 | 220 | depends on CROS_EC && TPL_MISC |
aaba703f SG |
221 | help |
222 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
223 | Chromebooks such as link and falco. The keyboard is provided | |
224 | through a legacy port interface, so on x86 machines the main | |
225 | function of the EC is power and thermal management. | |
226 | ||
747093dd SG |
227 | config VPL_CROS_EC_LPC |
228 | bool "Enable Chrome OS EC LPC driver in VPL" | |
8a1ab5e8 | 229 | depends on CROS_EC && VPL_MISC |
747093dd SG |
230 | help |
231 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
232 | Chromebooks such as link and falco. The keyboard is provided | |
233 | through a legacy port interface, so on x86 machines the main | |
234 | function of the EC is power and thermal management. | |
235 | ||
47cb8c65 SG |
236 | config CROS_EC_SANDBOX |
237 | bool "Enable Chrome OS EC sandbox driver" | |
238 | depends on CROS_EC && SANDBOX | |
239 | help | |
240 | Enable a sandbox emulation of the Chrome OS EC. This supports | |
241 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
242 | EC flash read/write/erase support and a few other things. It is | |
243 | enough to perform a Chrome OS verified boot on sandbox. | |
244 | ||
aaba703f SG |
245 | config SPL_CROS_EC_SANDBOX |
246 | bool "Enable Chrome OS EC sandbox driver in SPL" | |
247 | depends on SPL_CROS_EC && SANDBOX | |
248 | help | |
249 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports | |
250 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
251 | EC flash read/write/erase support and a few other things. It is | |
252 | enough to perform a Chrome OS verified boot on sandbox. | |
253 | ||
254 | config TPL_CROS_EC_SANDBOX | |
255 | bool "Enable Chrome OS EC sandbox driver in TPL" | |
256 | depends on TPL_CROS_EC && SANDBOX | |
257 | help | |
258 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports | |
259 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
260 | EC flash read/write/erase support and a few other things. It is | |
261 | enough to perform a Chrome OS verified boot on sandbox. | |
262 | ||
747093dd SG |
263 | config VPL_CROS_EC_SANDBOX |
264 | bool "Enable Chrome OS EC sandbox driver in VPL" | |
265 | depends on VPL_CROS_EC && SANDBOX | |
266 | help | |
267 | Enable a sandbox emulation of the Chrome OS EC in VPL. This supports | |
268 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
269 | EC flash read/write/erase support and a few other things. It is | |
270 | enough to perform a Chrome OS verified boot on sandbox. | |
271 | ||
6fb9ac15 SG |
272 | config CROS_EC_SPI |
273 | bool "Enable Chrome OS EC SPI driver" | |
274 | depends on CROS_EC | |
275 | help | |
276 | Enable SPI access to the Chrome OS EC. This is used on newer | |
277 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface | |
278 | provides a faster and more robust interface than I2C but the bugs | |
279 | are less interesting. | |
280 | ||
879704d8 SG |
281 | config DS4510 |
282 | bool "Enable support for DS4510 CPU supervisor" | |
283 | help | |
284 | Enable support for the Maxim DS4510 CPU supervisor. It has an | |
285 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins | |
286 | and a configurable timer for the supervisor function. The device is | |
287 | connected over I2C. | |
288 | ||
060613f1 TR |
289 | config FSL_IIM |
290 | bool "Enable FSL IC Identification Module (IIM) driver" | |
291 | depends on ARCH_MX31 || ARCH_MX5 | |
292 | ||
c12e0d93 | 293 | config FSL_SEC_MON |
fe78378d | 294 | bool "Enable FSL SEC_MON Driver" |
295 | help | |
296 | Freescale Security Monitor block is responsible for monitoring | |
297 | system states. | |
298 | Security Monitor can be transitioned on any security failures, | |
299 | like software violations or hardware security violations. | |
1cdd9412 | 300 | |
c9f85187 TR |
301 | choice |
302 | prompt "Security monitor interaction endianess" | |
303 | depends on FSL_SEC_MON | |
304 | default SYS_FSL_SEC_MON_BE if PPC | |
305 | default SYS_FSL_SEC_MON_LE | |
306 | ||
307 | config SYS_FSL_SEC_MON_LE | |
308 | bool "Security monitor interactions are little endian" | |
309 | ||
310 | config SYS_FSL_SEC_MON_BE | |
311 | bool "Security monitor interactions are big endian" | |
312 | ||
313 | endchoice | |
314 | ||
79d66a6a | 315 | config IRQ |
182c5f1e | 316 | bool "Interrupt controller" |
79d66a6a | 317 | help |
182c5f1e | 318 | This enables support for interrupt controllers, including ITSS. |
79d66a6a SG |
319 | Some devices have extra features, such as Apollo Lake. The |
320 | device has its own uclass since there are several operations | |
321 | involved. | |
322 | ||
b5392c50 PB |
323 | config JZ4780_EFUSE |
324 | bool "Ingenic JZ4780 eFUSE support" | |
325 | depends on ARCH_JZ47XX | |
326 | help | |
327 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. | |
328 | ||
2645bc0e SA |
329 | config LS2_SFP |
330 | bool "Layerscape Security Fuse Processor" | |
331 | depends on FSL_LSCH2 || ARCH_LS1021A | |
332 | depends on MISC | |
333 | imply DM_REGULATOR | |
334 | help | |
335 | This adds support for the Security Fuse Processor found on Layerscape | |
336 | SoCs. It contains various fuses related to secure boot, including the | |
337 | Super Root Key hash, One-Time-Programmable Master Key, Debug | |
338 | Challenge/Response values, and others. Fuses are numbered according | |
339 | to their four-byte offset from the start of the bank. | |
340 | ||
341 | If you don't need to read/program fuses, say 'n'. | |
342 | ||
3e020f03 PF |
343 | config MXC_OCOTP |
344 | bool "Enable MXC OCOTP Driver" | |
994ab731 | 345 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
0a6f625d | 346 | default y |
3e020f03 PF |
347 | help |
348 | If you say Y here, you will get support for the One Time | |
349 | Programmable memory pages that are stored on the some | |
350 | Freescale i.MX processors. | |
351 | ||
6c03a652 TR |
352 | config MXS_OCOTP |
353 | bool "Enable MXS OCOTP Driver" | |
354 | depends on ARCH_MX23 || ARCH_MX28 | |
355 | help | |
356 | If you say Y here, you will get support for the One Time | |
357 | Programmable memory pages that are stored on the | |
358 | Freescale i.MXS family of processors. | |
359 | ||
847505a3 JL |
360 | config NPCM_HOST |
361 | bool "Enable support espi or LPC for Host" | |
362 | depends on REGMAP && SYSCON | |
363 | help | |
364 | Enable NPCM BMC espi or LPC support for Host reading and writing. | |
365 | ||
33e9a695 MS |
366 | config SPL_MXC_OCOTP |
367 | bool "Enable MXC OCOTP driver in SPL" | |
251a3053 | 368 | depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) |
33e9a695 MS |
369 | default y |
370 | help | |
371 | If you say Y here, you will get support for the One Time | |
372 | Programmable memory pages, that are stored on some | |
373 | Freescale i.MX processors, in SPL. | |
374 | ||
0ae1c771 JL |
375 | config NPCM_OTP |
376 | bool "Nnvoton NPCM BMC On-Chip OTP Memory Support" | |
377 | depends on (ARM && ARCH_NPCM) | |
0ae1c771 JL |
378 | help |
379 | Support NPCM BMC OTP memory (fuse). | |
380 | To compile this driver as a module, choose M here: the module | |
381 | will be called npcm_otp. | |
382 | ||
d3ee9dbd PF |
383 | config IMX_ELE |
384 | bool "Enable i.MX EdgeLock Enclave MU driver and API" | |
03fcf966 YL |
385 | depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) |
386 | help | |
387 | If you say Y here to enable Message Unit driver to work with | |
388 | Sentinel core on some NXP i.MX processors. | |
389 | ||
4cf9e464 SR |
390 | config NUVOTON_NCT6102D |
391 | bool "Enable Nuvoton NCT6102D Super I/O driver" | |
392 | help | |
393 | If you say Y here, you will get support for the Nuvoton | |
394 | NCT6102D Super I/O driver. This can be used to enable or | |
395 | disable the legacy UART, the watchdog or other devices | |
396 | in the Nuvoton Super IO chips on X86 platforms. | |
397 | ||
5bee27aa | 398 | config P2SB |
d872e7da | 399 | bool "Intel Primary to Sideband Bridge" |
5bee27aa SG |
400 | depends on X86 || SANDBOX |
401 | help | |
d872e7da | 402 | This enables support for the Intel Primary to Sideband Bridge, |
5bee27aa SG |
403 | abbreviated to P2SB. The P2SB is used to access various peripherals |
404 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI | |
405 | space. The space is segmented into different channels and peripherals | |
406 | are accessed by device-specific means within those channels. Devices | |
407 | should be added in the device tree as subnodes of the P2SB. A | |
408 | Peripheral Channel Register? (PCR) API is provided to access those | |
409 | devices - see pcr_readl(), etc. | |
410 | ||
411 | config SPL_P2SB | |
d872e7da | 412 | bool "Intel Primary to Sideband Bridge in SPL" |
8a1ab5e8 | 413 | depends on SPL_MISC && (X86 || SANDBOX) |
5bee27aa | 414 | help |
d872e7da | 415 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
416 | through memory-mapped I/O in a large chunk of PCI space. The space is |
417 | segmented into different channels and peripherals are accessed by | |
418 | device-specific means within those channels. Devices should be added | |
419 | in the device tree as subnodes of the p2sb. | |
420 | ||
421 | config TPL_P2SB | |
d872e7da | 422 | bool "Intel Primary to Sideband Bridge in TPL" |
8a1ab5e8 | 423 | depends on TPL_MISC && (X86 || SANDBOX) |
5bee27aa | 424 | help |
d872e7da | 425 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
426 | through memory-mapped I/O in a large chunk of PCI space. The space is |
427 | segmented into different channels and peripherals are accessed by | |
428 | device-specific means within those channels. Devices should be added | |
429 | in the device tree as subnodes of the p2sb. | |
430 | ||
5fd6badb SG |
431 | config PWRSEQ |
432 | bool "Enable power-sequencing drivers" | |
433 | depends on DM | |
434 | help | |
435 | Power-sequencing drivers provide support for controlling power for | |
436 | devices. They are typically referenced by a phandle from another | |
437 | device. When the device is started up, its power sequence can be | |
438 | initiated. | |
439 | ||
440 | config SPL_PWRSEQ | |
441 | bool "Enable power-sequencing drivers for SPL" | |
8a1ab5e8 | 442 | depends on SPL_MISC && PWRSEQ |
5fd6badb SG |
443 | help |
444 | Power-sequencing drivers provide support for controlling power for | |
445 | devices. They are typically referenced by a phandle from another | |
446 | device. When the device is started up, its power sequence can be | |
447 | initiated. | |
448 | ||
1cdd9412 SR |
449 | config PCA9551_LED |
450 | bool "Enable PCA9551 LED driver" | |
451 | help | |
452 | Enable driver for PCA9551 LED controller. This controller | |
453 | is connected via I2C. So I2C needs to be enabled. | |
454 | ||
455 | config PCA9551_I2C_ADDR | |
456 | hex "I2C address of PCA9551 LED controller" | |
457 | depends on PCA9551_LED | |
458 | default 0x60 | |
459 | help | |
460 | The I2C address of the PCA9551 LED controller. | |
f9917454 | 461 | |
c3600e1f PD |
462 | config STM32MP_FUSE |
463 | bool "Enable STM32MP fuse wrapper providing the fuse API" | |
464 | depends on ARCH_STM32MP && MISC | |
465 | default y if CMD_FUSE | |
466 | help | |
467 | If you say Y here, you will get support for the fuse API (OTP) | |
468 | for STM32MP architecture. | |
469 | This API is needed for CMD_FUSE. | |
470 | ||
4e280b91 CK |
471 | config STM32_RCC |
472 | bool "Enable RCC driver for the STM32 SoC's family" | |
71f6354b | 473 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
4e280b91 CK |
474 | help |
475 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control | |
476 | block) is responsible of the management of the clock and reset | |
477 | generation. | |
478 | This driver is similar to an MFD driver in the Linux kernel. | |
479 | ||
bd3ee84a SW |
480 | config TEGRA_CAR |
481 | bool "Enable support for the Tegra CAR driver" | |
482 | depends on TEGRA_NO_BPMP | |
483 | help | |
484 | The Tegra CAR (Clock and Reset Controller) is a HW module that | |
485 | controls almost all clocks and resets in a Tegra SoC. | |
486 | ||
73dd5c4c SW |
487 | config TEGRA186_BPMP |
488 | bool "Enable support for the Tegra186 BPMP driver" | |
489 | depends on TEGRA186 | |
490 | help | |
491 | The Tegra BPMP (Boot and Power Management Processor) is a separate | |
492 | auxiliary CPU embedded into Tegra to perform power management work, | |
493 | and controls related features such as clocks, resets, power domains, | |
494 | PMIC I2C bus, etc. This driver provides the core low-level | |
495 | communication path by which feature-specific drivers (such as clock) | |
496 | can make requests to the BPMP. This driver is similar to an MFD | |
497 | driver in the Linux kernel. | |
498 | ||
079ac595 SG |
499 | config TEST_DRV |
500 | bool "Enable support for test drivers" | |
501 | default y if SANDBOX | |
502 | help | |
503 | This enables drivers and uclasses that provides a way of testing the | |
504 | operations of memory allocation and driver/uclass methods in driver | |
505 | model. This should only be enabled for testing as it is not useful for | |
506 | anything else. | |
507 | ||
a5505de0 MB |
508 | config TURRIS_OMNIA_MCU |
509 | bool "Enable Turris Omnia MCU driver" | |
510 | depends on DM_I2C | |
511 | depends on DM_GPIO | |
8593e2e9 | 512 | depends on DM_RNG |
a5505de0 MB |
513 | depends on SYSRESET |
514 | default y if TARGET_TURRIS_OMNIA | |
515 | help | |
516 | This enables support for Turris Omnia MCU connected GPIOs and | |
517 | board power off. | |
518 | ||
02544db9 MV |
519 | config USB_HUB_USB251XB |
520 | tristate "USB251XB Hub Controller Configuration Driver" | |
521 | depends on I2C | |
522 | help | |
523 | This option enables support for configuration via SMBus of the | |
524 | Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration | |
525 | parameters may be set in devicetree or platform data. | |
526 | Say Y or M here if you need to configure such a device via SMBus. | |
527 | ||
cc3fedb2 AF |
528 | config TWL4030_LED |
529 | bool "Enable TWL4030 LED controller" | |
530 | help | |
531 | Enable this to add support for the TWL4030 LED controller. | |
532 | ||
85056932 SR |
533 | config WINBOND_W83627 |
534 | bool "Enable Winbond Super I/O driver" | |
535 | help | |
536 | If you say Y here, you will get support for the Winbond | |
537 | W83627 Super I/O driver. This can be used to enable the | |
538 | legacy UART or other devices in the Winbond Super IO chips | |
539 | on X86 platforms. | |
540 | ||
fcf5c041 MY |
541 | config QFW |
542 | bool | |
543 | help | |
5b0b43e0 AC |
544 | Hidden option to enable QEMU fw_cfg interface and uclass. This will |
545 | be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. | |
546 | ||
b2f088c1 HS |
547 | config QFW_ACPI |
548 | bool | |
549 | default y | |
550 | depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX | |
551 | help | |
552 | Hidden option to read ACPI tables from QEMU. | |
553 | ||
5b0b43e0 AC |
554 | config QFW_PIO |
555 | bool | |
556 | depends on QFW | |
557 | help | |
558 | Hidden option to enable PIO QEMU fw_cfg interface. This will be | |
559 | selected by the appropriate QEMU board. | |
fcf5c041 | 560 | |
5830b57b AC |
561 | config QFW_MMIO |
562 | bool | |
563 | depends on QFW | |
564 | help | |
565 | Hidden option to enable MMIO QEMU fw_cfg interface. This will be | |
566 | selected by the appropriate QEMU board. | |
567 | ||
1c5aab80 HS |
568 | config QFW_SMBIOS |
569 | bool | |
570 | default y | |
571 | depends on QFW && SMBIOS && !SANDBOX | |
572 | help | |
573 | Hidden option to read SMBIOS tables from QEMU. | |
574 | ||
d7e28918 | 575 | config I2C_EEPROM |
576 | bool "Enable driver for generic I2C-attached EEPROMs" | |
577 | depends on MISC | |
578 | help | |
579 | Enable a generic driver for EEPROMs attached via I2C. | |
e3f24d4f | 580 | |
d81a1de9 WY |
581 | |
582 | config SPL_I2C_EEPROM | |
583 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" | |
8a1ab5e8 | 584 | depends on SPL_MISC |
d81a1de9 WY |
585 | help |
586 | This option is an SPL-variant of the I2C_EEPROM option. | |
587 | See the help of I2C_EEPROM for details. | |
588 | ||
e3f24d4f AF |
589 | config SYS_I2C_EEPROM_ADDR |
590 | hex "Chip address of the EEPROM device" | |
88cd7d0e | 591 | depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM |
a077ac13 | 592 | default 0x0 |
e3f24d4f | 593 | |
88cd7d0e | 594 | if I2C_EEPROM |
e3f24d4f AF |
595 | |
596 | config SYS_I2C_EEPROM_ADDR_OVERFLOW | |
597 | hex "EEPROM Address Overflow" | |
5fd4a7ed | 598 | default 0x0 |
e3f24d4f AF |
599 | help |
600 | EEPROM chips that implement "address overflow" are ones | |
601 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
602 | address and the extra bits end up in the "chip address" bit | |
603 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 | |
604 | byte chips. | |
605 | ||
606 | endif | |
607 | ||
86da8c12 MS |
608 | config GDSYS_RXAUI_CTRL |
609 | bool "Enable gdsys RXAUI control driver" | |
610 | depends on MISC | |
611 | help | |
612 | Support gdsys FPGA's RXAUI control. | |
7e86242b MS |
613 | |
614 | config GDSYS_IOEP | |
615 | bool "Enable gdsys IOEP driver" | |
616 | depends on MISC | |
617 | help | |
618 | Support gdsys FPGA's IO endpoint driver. | |
d2166319 MS |
619 | |
620 | config MPC83XX_SERDES | |
621 | bool "Enable MPC83xx serdes driver" | |
622 | depends on MISC | |
623 | help | |
624 | Support for serdes found on MPC83xx SoCs. | |
625 | ||
62030004 TFC |
626 | config FS_LOADER |
627 | bool "Enable loader driver for file system" | |
628 | help | |
629 | This is file system generic loader which can be used to load | |
630 | the file image from the storage into target such as memory. | |
631 | ||
632 | The consumer driver would then use this loader to program whatever, | |
633 | ie. the FPGA device. | |
634 | ||
b071a077 | 635 | config SPL_FS_LOADER |
b68d2865 | 636 | bool "Enable loader driver for file system in SPL" |
8a1ab5e8 | 637 | depends on SPL |
b071a077 K |
638 | help |
639 | This is file system generic loader which can be used to load | |
640 | the file image from the storage into target such as memory. | |
641 | ||
642 | The consumer driver would then use this loader to program whatever, | |
643 | ie. the FPGA device. | |
644 | ||
c0a2b086 MS |
645 | config GDSYS_SOC |
646 | bool "Enable gdsys SOC driver" | |
647 | depends on MISC | |
648 | help | |
649 | Support for gdsys IHS SOC, a simple bus associated with each gdsys | |
650 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose | |
651 | register maps are contained within the FPGA's register map. | |
652 | ||
ab88bd2b MS |
653 | config IHS_FPGA |
654 | bool "Enable IHS FPGA driver" | |
655 | depends on MISC | |
656 | help | |
657 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on | |
658 | gdsys devices, which supply the majority of the functionality offered | |
659 | by the devices. This driver supports both CON and CPU variants of the | |
660 | devices, depending on the device tree entry. | |
344eb6d5 TK |
661 | config ESM_K3 |
662 | bool "Enable K3 ESM driver" | |
663 | depends on ARCH_K3 | |
664 | help | |
665 | Support ESM (Error Signaling Module) on TI K3 SoCs. | |
ab88bd2b | 666 | |
f8164958 EH |
667 | config MICROCHIP_FLEXCOM |
668 | bool "Enable Microchip Flexcom driver" | |
669 | depends on MISC | |
670 | help | |
671 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, | |
672 | an I2C controller and an USART. | |
673 | Only one function can be used at a time and is chosen at boot time | |
674 | according to the device tree. | |
675 | ||
9d233b4e TK |
676 | config K3_AVS0 |
677 | depends on ARCH_K3 && SPL_DM_REGULATOR | |
678 | bool "AVS class 0 support for K3 devices" | |
679 | help | |
680 | K3 devices have the optimized voltage values for the main voltage | |
681 | domains stored in efuse within the VTM IP. This driver reads the | |
682 | optimized voltage from the efuse, so that it can be programmed | |
683 | to the PMIC on board. | |
684 | ||
3b36b38f TK |
685 | config ESM_PMIC |
686 | bool "Enable PMIC ESM driver" | |
687 | depends on DM_PMIC | |
688 | help | |
689 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used | |
690 | typically to reboot the board in error condition. | |
691 | ||
98ab831d TR |
692 | config FSL_IFC |
693 | bool | |
694 | ||
42595eb7 MW |
695 | config SL28CPLD |
696 | bool "Enable Kontron sl28cpld multi-function driver" | |
697 | depends on DM_I2C | |
698 | help | |
699 | Support for the Kontron sl28cpld management controller. This is | |
700 | the base driver which provides common access methods for the | |
701 | sub-drivers. | |
702 | ||
3f190c55 WYL |
703 | config SPL_SOCFPGA_DT_REG |
704 | bool "Enable register setting from device tree in SPL" | |
705 | depends on SPL | |
706 | help | |
707 | Enable register setting from device tree. This also | |
708 | provides user a clean interface and all register settings are | |
709 | centralized in one place, device tree. | |
0b11dbf7 | 710 | endmenu |