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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # Multifunction miscellaneous devices | |
3 | # | |
4 | ||
5 | menu "Multifunction device drivers" | |
6 | ||
4395e06e TC |
7 | config MISC |
8 | bool "Enable Driver Model for Misc drivers" | |
9 | depends on DM | |
10 | help | |
11 | Enable driver model for miscellaneous devices. This class is | |
12 | used only for those do not fit other more general classes. A | |
13 | set of generic read, write and ioctl methods may be used to | |
14 | access the device. | |
15 | ||
aaba703f SG |
16 | config SPL_MISC |
17 | bool "Enable Driver Model for Misc drivers in SPL" | |
18 | depends on SPL_DM | |
38127741 | 19 | default MISC |
aaba703f SG |
20 | help |
21 | Enable driver model for miscellaneous devices. This class is | |
22 | used only for those do not fit other more general classes. A | |
23 | set of generic read, write and ioctl methods may be used to | |
24 | access the device. | |
25 | ||
26 | config TPL_MISC | |
27 | bool "Enable Driver Model for Misc drivers in TPL" | |
28 | depends on TPL_DM | |
38127741 SA |
29 | default MISC |
30 | help | |
31 | Enable driver model for miscellaneous devices. This class is | |
32 | used only for those do not fit other more general classes. A | |
33 | set of generic read, write and ioctl methods may be used to | |
34 | access the device. | |
35 | ||
36 | config VPL_MISC | |
37 | bool "Enable Driver Model for Misc drivers in VPL" | |
38 | depends on VPL_DM | |
39 | default MISC | |
aaba703f SG |
40 | help |
41 | Enable driver model for miscellaneous devices. This class is | |
42 | used only for those do not fit other more general classes. A | |
43 | set of generic read, write and ioctl methods may be used to | |
44 | access the device. | |
45 | ||
c8ce7ba8 SA |
46 | config NVMEM |
47 | bool "NVMEM support" | |
48 | help | |
49 | This adds support for a common interface to different types of | |
50 | non-volatile memory. Consumers can use nvmem-cells properties to look | |
51 | up hardware configuration data such as MAC addresses and calibration | |
52 | settings. | |
53 | ||
54 | config SPL_NVMEM | |
55 | bool "NVMEM support in SPL" | |
56 | help | |
57 | This adds support for a common interface to different types of | |
58 | non-volatile memory. Consumers can use nvmem-cells properties to look | |
59 | up hardware configuration data such as MAC addresses and calibration | |
60 | settings. | |
61 | ||
ca844dd8 TC |
62 | config ALTERA_SYSID |
63 | bool "Altera Sysid support" | |
64 | depends on MISC | |
65 | help | |
66 | Select this to enable a sysid for Altera devices. Please find | |
67 | details on the "Embedded Peripherals IP User Guide" of Altera. | |
68 | ||
aa5eb9a3 MB |
69 | config ATSHA204A |
70 | bool "Support for Atmel ATSHA204A module" | |
467f0c4d | 71 | select BITREVERSE |
aa5eb9a3 MB |
72 | depends on MISC |
73 | help | |
74 | Enable support for I2C connected Atmel's ATSHA204A | |
75 | CryptoAuthentication module found for example on the Turris Omnia | |
76 | board. | |
77 | ||
8479b9e6 TH |
78 | config GATEWORKS_SC |
79 | bool "Gateworks System Controller Support" | |
80 | depends on MISC | |
81 | help | |
82 | Enable access for the Gateworks System Controller used on Gateworks | |
83 | boards to provide a boot watchdog, power control, temperature monitor, | |
84 | voltage ADCs, and EEPROM. | |
85 | ||
49cd8e85 PT |
86 | config ROCKCHIP_EFUSE |
87 | bool "Rockchip e-fuse support" | |
88 | depends on MISC | |
89 | help | |
90 | Enable (read-only) access for the e-fuse block found in Rockchip | |
91 | SoCs: accesses can either be made using byte addressing and a length | |
92 | or through child-nodes that are generated based on the e-fuse map | |
93 | retrieved from the DTS. | |
94 | ||
a907dc3f FX |
95 | config ROCKCHIP_OTP |
96 | bool "Rockchip OTP Support" | |
97 | depends on MISC | |
98 | help | |
99 | Enable (read-only) access for the one-time-programmable memory block | |
100 | found in Rockchip SoCs: accesses can either be made using byte | |
101 | addressing and a length or through child-nodes that are generated | |
102 | based on the e-fuse map retrieved from the DTS. | |
103 | ||
05307213 PP |
104 | config SIFIVE_OTP |
105 | bool "SiFive eMemory OTP driver" | |
106 | depends on MISC | |
107 | help | |
108 | Enable support for reading and writing the eMemory OTP on the | |
109 | SiFive SoCs. | |
110 | ||
d9136520 TR |
111 | config SMSC_LPC47M |
112 | bool "LPC47M SMSC driver" | |
113 | ||
114 | config SMSC_SIO1007 | |
115 | bool "SIO1007 SMSC driver" | |
116 | ||
0fabfeb2 LD |
117 | config VEXPRESS_CONFIG |
118 | bool "Enable support for Arm Versatile Express config bus" | |
119 | depends on MISC | |
120 | help | |
121 | If you say Y here, you will get support for accessing the | |
122 | configuration bus on the Arm Versatile Express boards via | |
123 | a sysreg driver. | |
124 | ||
6fb9ac15 SG |
125 | config CMD_CROS_EC |
126 | bool "Enable crosec command" | |
127 | depends on CROS_EC | |
128 | help | |
129 | Enable command-line access to the Chrome OS EC (Embedded | |
130 | Controller). This provides the 'crosec' command which has | |
131 | a number of sub-commands for performing EC tasks such as | |
132 | updating its flash, accessing a small saved context area | |
133 | and talking to the I2C bus behind the EC (if there is one). | |
134 | ||
135 | config CROS_EC | |
136 | bool "Enable Chrome OS EC" | |
137 | help | |
138 | Enable access to the Chrome OS EC. This is a separate | |
139 | microcontroller typically available on a SPI bus on Chromebooks. It | |
140 | provides access to the keyboard, some internal storage and may | |
141 | control access to the battery and main PMIC depending on the | |
142 | device. You can use the 'crosec' command to access it. | |
143 | ||
aaba703f SG |
144 | config SPL_CROS_EC |
145 | bool "Enable Chrome OS EC in SPL" | |
8a1ab5e8 | 146 | depends on SPL_MISC |
aaba703f SG |
147 | help |
148 | Enable access to the Chrome OS EC in SPL. This is a separate | |
149 | microcontroller typically available on a SPI bus on Chromebooks. It | |
150 | provides access to the keyboard, some internal storage and may | |
151 | control access to the battery and main PMIC depending on the | |
152 | device. You can use the 'crosec' command to access it. | |
153 | ||
154 | config TPL_CROS_EC | |
155 | bool "Enable Chrome OS EC in TPL" | |
8a1ab5e8 | 156 | depends on TPL_MISC |
aaba703f SG |
157 | help |
158 | Enable access to the Chrome OS EC in TPL. This is a separate | |
159 | microcontroller typically available on a SPI bus on Chromebooks. It | |
160 | provides access to the keyboard, some internal storage and may | |
161 | control access to the battery and main PMIC depending on the | |
162 | device. You can use the 'crosec' command to access it. | |
163 | ||
747093dd SG |
164 | config VPL_CROS_EC |
165 | bool "Enable Chrome OS EC in VPL" | |
8a1ab5e8 | 166 | depends on VPL_MISC |
747093dd SG |
167 | help |
168 | Enable access to the Chrome OS EC in VPL. This is a separate | |
169 | microcontroller typically available on a SPI bus on Chromebooks. It | |
170 | provides access to the keyboard, some internal storage and may | |
171 | control access to the battery and main PMIC depending on the | |
172 | device. You can use the 'crosec' command to access it. | |
173 | ||
6fb9ac15 SG |
174 | config CROS_EC_I2C |
175 | bool "Enable Chrome OS EC I2C driver" | |
176 | depends on CROS_EC | |
177 | help | |
178 | Enable I2C access to the Chrome OS EC. This is used on older | |
179 | ARM Chromebooks such as snow and spring before the standard bus | |
180 | changed to SPI. The EC will accept commands across the I2C using | |
181 | a special message protocol, and provide responses. | |
182 | ||
183 | config CROS_EC_LPC | |
184 | bool "Enable Chrome OS EC LPC driver" | |
185 | depends on CROS_EC | |
186 | help | |
187 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
188 | Chromebooks such as link and falco. The keyboard is provided | |
189 | through a legacy port interface, so on x86 machines the main | |
190 | function of the EC is power and thermal management. | |
191 | ||
aaba703f SG |
192 | config SPL_CROS_EC_LPC |
193 | bool "Enable Chrome OS EC LPC driver in SPL" | |
8a1ab5e8 | 194 | depends on CROS_EC && SPL_MISC |
aaba703f SG |
195 | help |
196 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
197 | Chromebooks such as link and falco. The keyboard is provided | |
198 | through a legacy port interface, so on x86 machines the main | |
199 | function of the EC is power and thermal management. | |
200 | ||
201 | config TPL_CROS_EC_LPC | |
202 | bool "Enable Chrome OS EC LPC driver in TPL" | |
8a1ab5e8 | 203 | depends on CROS_EC && TPL_MISC |
aaba703f SG |
204 | help |
205 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
206 | Chromebooks such as link and falco. The keyboard is provided | |
207 | through a legacy port interface, so on x86 machines the main | |
208 | function of the EC is power and thermal management. | |
209 | ||
747093dd SG |
210 | config VPL_CROS_EC_LPC |
211 | bool "Enable Chrome OS EC LPC driver in VPL" | |
8a1ab5e8 | 212 | depends on CROS_EC && VPL_MISC |
747093dd SG |
213 | help |
214 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
215 | Chromebooks such as link and falco. The keyboard is provided | |
216 | through a legacy port interface, so on x86 machines the main | |
217 | function of the EC is power and thermal management. | |
218 | ||
47cb8c65 SG |
219 | config CROS_EC_SANDBOX |
220 | bool "Enable Chrome OS EC sandbox driver" | |
221 | depends on CROS_EC && SANDBOX | |
222 | help | |
223 | Enable a sandbox emulation of the Chrome OS EC. This supports | |
224 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
225 | EC flash read/write/erase support and a few other things. It is | |
226 | enough to perform a Chrome OS verified boot on sandbox. | |
227 | ||
aaba703f SG |
228 | config SPL_CROS_EC_SANDBOX |
229 | bool "Enable Chrome OS EC sandbox driver in SPL" | |
230 | depends on SPL_CROS_EC && SANDBOX | |
231 | help | |
232 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports | |
233 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
234 | EC flash read/write/erase support and a few other things. It is | |
235 | enough to perform a Chrome OS verified boot on sandbox. | |
236 | ||
237 | config TPL_CROS_EC_SANDBOX | |
238 | bool "Enable Chrome OS EC sandbox driver in TPL" | |
239 | depends on TPL_CROS_EC && SANDBOX | |
240 | help | |
241 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports | |
242 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
243 | EC flash read/write/erase support and a few other things. It is | |
244 | enough to perform a Chrome OS verified boot on sandbox. | |
245 | ||
747093dd SG |
246 | config VPL_CROS_EC_SANDBOX |
247 | bool "Enable Chrome OS EC sandbox driver in VPL" | |
248 | depends on VPL_CROS_EC && SANDBOX | |
249 | help | |
250 | Enable a sandbox emulation of the Chrome OS EC in VPL. This supports | |
251 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
252 | EC flash read/write/erase support and a few other things. It is | |
253 | enough to perform a Chrome OS verified boot on sandbox. | |
254 | ||
6fb9ac15 SG |
255 | config CROS_EC_SPI |
256 | bool "Enable Chrome OS EC SPI driver" | |
257 | depends on CROS_EC | |
258 | help | |
259 | Enable SPI access to the Chrome OS EC. This is used on newer | |
260 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface | |
261 | provides a faster and more robust interface than I2C but the bugs | |
262 | are less interesting. | |
263 | ||
879704d8 SG |
264 | config DS4510 |
265 | bool "Enable support for DS4510 CPU supervisor" | |
266 | help | |
267 | Enable support for the Maxim DS4510 CPU supervisor. It has an | |
268 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins | |
269 | and a configurable timer for the supervisor function. The device is | |
270 | connected over I2C. | |
271 | ||
060613f1 TR |
272 | config FSL_IIM |
273 | bool "Enable FSL IC Identification Module (IIM) driver" | |
274 | depends on ARCH_MX31 || ARCH_MX5 | |
275 | ||
c12e0d93 | 276 | config FSL_SEC_MON |
fe78378d | 277 | bool "Enable FSL SEC_MON Driver" |
278 | help | |
279 | Freescale Security Monitor block is responsible for monitoring | |
280 | system states. | |
281 | Security Monitor can be transitioned on any security failures, | |
282 | like software violations or hardware security violations. | |
1cdd9412 | 283 | |
c9f85187 TR |
284 | choice |
285 | prompt "Security monitor interaction endianess" | |
286 | depends on FSL_SEC_MON | |
287 | default SYS_FSL_SEC_MON_BE if PPC | |
288 | default SYS_FSL_SEC_MON_LE | |
289 | ||
290 | config SYS_FSL_SEC_MON_LE | |
291 | bool "Security monitor interactions are little endian" | |
292 | ||
293 | config SYS_FSL_SEC_MON_BE | |
294 | bool "Security monitor interactions are big endian" | |
295 | ||
296 | endchoice | |
297 | ||
79d66a6a | 298 | config IRQ |
182c5f1e | 299 | bool "Interrupt controller" |
79d66a6a | 300 | help |
182c5f1e | 301 | This enables support for interrupt controllers, including ITSS. |
79d66a6a SG |
302 | Some devices have extra features, such as Apollo Lake. The |
303 | device has its own uclass since there are several operations | |
304 | involved. | |
305 | ||
b5392c50 PB |
306 | config JZ4780_EFUSE |
307 | bool "Ingenic JZ4780 eFUSE support" | |
308 | depends on ARCH_JZ47XX | |
309 | help | |
310 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. | |
311 | ||
2645bc0e SA |
312 | config LS2_SFP |
313 | bool "Layerscape Security Fuse Processor" | |
314 | depends on FSL_LSCH2 || ARCH_LS1021A | |
315 | depends on MISC | |
316 | imply DM_REGULATOR | |
317 | help | |
318 | This adds support for the Security Fuse Processor found on Layerscape | |
319 | SoCs. It contains various fuses related to secure boot, including the | |
320 | Super Root Key hash, One-Time-Programmable Master Key, Debug | |
321 | Challenge/Response values, and others. Fuses are numbered according | |
322 | to their four-byte offset from the start of the bank. | |
323 | ||
324 | If you don't need to read/program fuses, say 'n'. | |
325 | ||
3e020f03 PF |
326 | config MXC_OCOTP |
327 | bool "Enable MXC OCOTP Driver" | |
994ab731 | 328 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
0a6f625d | 329 | default y |
3e020f03 PF |
330 | help |
331 | If you say Y here, you will get support for the One Time | |
332 | Programmable memory pages that are stored on the some | |
333 | Freescale i.MX processors. | |
334 | ||
6c03a652 TR |
335 | config MXS_OCOTP |
336 | bool "Enable MXS OCOTP Driver" | |
337 | depends on ARCH_MX23 || ARCH_MX28 | |
338 | help | |
339 | If you say Y here, you will get support for the One Time | |
340 | Programmable memory pages that are stored on the | |
341 | Freescale i.MXS family of processors. | |
342 | ||
847505a3 JL |
343 | config NPCM_HOST |
344 | bool "Enable support espi or LPC for Host" | |
345 | depends on REGMAP && SYSCON | |
346 | help | |
347 | Enable NPCM BMC espi or LPC support for Host reading and writing. | |
348 | ||
33e9a695 MS |
349 | config SPL_MXC_OCOTP |
350 | bool "Enable MXC OCOTP driver in SPL" | |
251a3053 | 351 | depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) |
33e9a695 MS |
352 | default y |
353 | help | |
354 | If you say Y here, you will get support for the One Time | |
355 | Programmable memory pages, that are stored on some | |
356 | Freescale i.MX processors, in SPL. | |
357 | ||
0ae1c771 JL |
358 | config NPCM_OTP |
359 | bool "Nnvoton NPCM BMC On-Chip OTP Memory Support" | |
360 | depends on (ARM && ARCH_NPCM) | |
361 | default n | |
362 | help | |
363 | Support NPCM BMC OTP memory (fuse). | |
364 | To compile this driver as a module, choose M here: the module | |
365 | will be called npcm_otp. | |
366 | ||
d3ee9dbd PF |
367 | config IMX_ELE |
368 | bool "Enable i.MX EdgeLock Enclave MU driver and API" | |
03fcf966 YL |
369 | depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) |
370 | help | |
371 | If you say Y here to enable Message Unit driver to work with | |
372 | Sentinel core on some NXP i.MX processors. | |
373 | ||
4cf9e464 SR |
374 | config NUVOTON_NCT6102D |
375 | bool "Enable Nuvoton NCT6102D Super I/O driver" | |
376 | help | |
377 | If you say Y here, you will get support for the Nuvoton | |
378 | NCT6102D Super I/O driver. This can be used to enable or | |
379 | disable the legacy UART, the watchdog or other devices | |
380 | in the Nuvoton Super IO chips on X86 platforms. | |
381 | ||
5bee27aa | 382 | config P2SB |
d872e7da | 383 | bool "Intel Primary to Sideband Bridge" |
5bee27aa SG |
384 | depends on X86 || SANDBOX |
385 | help | |
d872e7da | 386 | This enables support for the Intel Primary to Sideband Bridge, |
5bee27aa SG |
387 | abbreviated to P2SB. The P2SB is used to access various peripherals |
388 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI | |
389 | space. The space is segmented into different channels and peripherals | |
390 | are accessed by device-specific means within those channels. Devices | |
391 | should be added in the device tree as subnodes of the P2SB. A | |
392 | Peripheral Channel Register? (PCR) API is provided to access those | |
393 | devices - see pcr_readl(), etc. | |
394 | ||
395 | config SPL_P2SB | |
d872e7da | 396 | bool "Intel Primary to Sideband Bridge in SPL" |
8a1ab5e8 | 397 | depends on SPL_MISC && (X86 || SANDBOX) |
5bee27aa | 398 | help |
d872e7da | 399 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
400 | through memory-mapped I/O in a large chunk of PCI space. The space is |
401 | segmented into different channels and peripherals are accessed by | |
402 | device-specific means within those channels. Devices should be added | |
403 | in the device tree as subnodes of the p2sb. | |
404 | ||
405 | config TPL_P2SB | |
d872e7da | 406 | bool "Intel Primary to Sideband Bridge in TPL" |
8a1ab5e8 | 407 | depends on TPL_MISC && (X86 || SANDBOX) |
5bee27aa | 408 | help |
d872e7da | 409 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
410 | through memory-mapped I/O in a large chunk of PCI space. The space is |
411 | segmented into different channels and peripherals are accessed by | |
412 | device-specific means within those channels. Devices should be added | |
413 | in the device tree as subnodes of the p2sb. | |
414 | ||
5fd6badb SG |
415 | config PWRSEQ |
416 | bool "Enable power-sequencing drivers" | |
417 | depends on DM | |
418 | help | |
419 | Power-sequencing drivers provide support for controlling power for | |
420 | devices. They are typically referenced by a phandle from another | |
421 | device. When the device is started up, its power sequence can be | |
422 | initiated. | |
423 | ||
424 | config SPL_PWRSEQ | |
425 | bool "Enable power-sequencing drivers for SPL" | |
8a1ab5e8 | 426 | depends on SPL_MISC && PWRSEQ |
5fd6badb SG |
427 | help |
428 | Power-sequencing drivers provide support for controlling power for | |
429 | devices. They are typically referenced by a phandle from another | |
430 | device. When the device is started up, its power sequence can be | |
431 | initiated. | |
432 | ||
1cdd9412 SR |
433 | config PCA9551_LED |
434 | bool "Enable PCA9551 LED driver" | |
435 | help | |
436 | Enable driver for PCA9551 LED controller. This controller | |
437 | is connected via I2C. So I2C needs to be enabled. | |
438 | ||
439 | config PCA9551_I2C_ADDR | |
440 | hex "I2C address of PCA9551 LED controller" | |
441 | depends on PCA9551_LED | |
442 | default 0x60 | |
443 | help | |
444 | The I2C address of the PCA9551 LED controller. | |
f9917454 | 445 | |
c3600e1f PD |
446 | config STM32MP_FUSE |
447 | bool "Enable STM32MP fuse wrapper providing the fuse API" | |
448 | depends on ARCH_STM32MP && MISC | |
449 | default y if CMD_FUSE | |
450 | help | |
451 | If you say Y here, you will get support for the fuse API (OTP) | |
452 | for STM32MP architecture. | |
453 | This API is needed for CMD_FUSE. | |
454 | ||
4e280b91 CK |
455 | config STM32_RCC |
456 | bool "Enable RCC driver for the STM32 SoC's family" | |
71f6354b | 457 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
4e280b91 CK |
458 | help |
459 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control | |
460 | block) is responsible of the management of the clock and reset | |
461 | generation. | |
462 | This driver is similar to an MFD driver in the Linux kernel. | |
463 | ||
bd3ee84a SW |
464 | config TEGRA_CAR |
465 | bool "Enable support for the Tegra CAR driver" | |
466 | depends on TEGRA_NO_BPMP | |
467 | help | |
468 | The Tegra CAR (Clock and Reset Controller) is a HW module that | |
469 | controls almost all clocks and resets in a Tegra SoC. | |
470 | ||
73dd5c4c SW |
471 | config TEGRA186_BPMP |
472 | bool "Enable support for the Tegra186 BPMP driver" | |
473 | depends on TEGRA186 | |
474 | help | |
475 | The Tegra BPMP (Boot and Power Management Processor) is a separate | |
476 | auxiliary CPU embedded into Tegra to perform power management work, | |
477 | and controls related features such as clocks, resets, power domains, | |
478 | PMIC I2C bus, etc. This driver provides the core low-level | |
479 | communication path by which feature-specific drivers (such as clock) | |
480 | can make requests to the BPMP. This driver is similar to an MFD | |
481 | driver in the Linux kernel. | |
482 | ||
079ac595 SG |
483 | config TEST_DRV |
484 | bool "Enable support for test drivers" | |
485 | default y if SANDBOX | |
486 | help | |
487 | This enables drivers and uclasses that provides a way of testing the | |
488 | operations of memory allocation and driver/uclass methods in driver | |
489 | model. This should only be enabled for testing as it is not useful for | |
490 | anything else. | |
491 | ||
02544db9 MV |
492 | config USB_HUB_USB251XB |
493 | tristate "USB251XB Hub Controller Configuration Driver" | |
494 | depends on I2C | |
495 | help | |
496 | This option enables support for configuration via SMBus of the | |
497 | Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration | |
498 | parameters may be set in devicetree or platform data. | |
499 | Say Y or M here if you need to configure such a device via SMBus. | |
500 | ||
cc3fedb2 AF |
501 | config TWL4030_LED |
502 | bool "Enable TWL4030 LED controller" | |
503 | help | |
504 | Enable this to add support for the TWL4030 LED controller. | |
505 | ||
85056932 SR |
506 | config WINBOND_W83627 |
507 | bool "Enable Winbond Super I/O driver" | |
508 | help | |
509 | If you say Y here, you will get support for the Winbond | |
510 | W83627 Super I/O driver. This can be used to enable the | |
511 | legacy UART or other devices in the Winbond Super IO chips | |
512 | on X86 platforms. | |
513 | ||
1b15483d VZ |
514 | config QCOM_GENI_SE |
515 | bool "Qualcomm GENI Serial Engine Driver" | |
516 | depends on ARCH_SNAPDRAGON | |
517 | help | |
518 | The driver manages Generic Interface (GENI) firmware based | |
519 | Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. | |
520 | ||
fcf5c041 MY |
521 | config QFW |
522 | bool | |
523 | help | |
5b0b43e0 AC |
524 | Hidden option to enable QEMU fw_cfg interface and uclass. This will |
525 | be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. | |
526 | ||
527 | config QFW_PIO | |
528 | bool | |
529 | depends on QFW | |
530 | help | |
531 | Hidden option to enable PIO QEMU fw_cfg interface. This will be | |
532 | selected by the appropriate QEMU board. | |
fcf5c041 | 533 | |
5830b57b AC |
534 | config QFW_MMIO |
535 | bool | |
536 | depends on QFW | |
537 | help | |
538 | Hidden option to enable MMIO QEMU fw_cfg interface. This will be | |
539 | selected by the appropriate QEMU board. | |
540 | ||
d7e28918 | 541 | config I2C_EEPROM |
542 | bool "Enable driver for generic I2C-attached EEPROMs" | |
543 | depends on MISC | |
544 | help | |
545 | Enable a generic driver for EEPROMs attached via I2C. | |
e3f24d4f | 546 | |
d81a1de9 WY |
547 | |
548 | config SPL_I2C_EEPROM | |
549 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" | |
8a1ab5e8 | 550 | depends on SPL_MISC |
d81a1de9 WY |
551 | help |
552 | This option is an SPL-variant of the I2C_EEPROM option. | |
553 | See the help of I2C_EEPROM for details. | |
554 | ||
e3f24d4f AF |
555 | config SYS_I2C_EEPROM_ADDR |
556 | hex "Chip address of the EEPROM device" | |
88cd7d0e | 557 | depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM |
e3f24d4f AF |
558 | default 0 |
559 | ||
88cd7d0e | 560 | if I2C_EEPROM |
e3f24d4f AF |
561 | |
562 | config SYS_I2C_EEPROM_ADDR_OVERFLOW | |
563 | hex "EEPROM Address Overflow" | |
5fd4a7ed | 564 | default 0x0 |
e3f24d4f AF |
565 | help |
566 | EEPROM chips that implement "address overflow" are ones | |
567 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
568 | address and the extra bits end up in the "chip address" bit | |
569 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 | |
570 | byte chips. | |
571 | ||
572 | endif | |
573 | ||
86da8c12 MS |
574 | config GDSYS_RXAUI_CTRL |
575 | bool "Enable gdsys RXAUI control driver" | |
576 | depends on MISC | |
577 | help | |
578 | Support gdsys FPGA's RXAUI control. | |
7e86242b MS |
579 | |
580 | config GDSYS_IOEP | |
581 | bool "Enable gdsys IOEP driver" | |
582 | depends on MISC | |
583 | help | |
584 | Support gdsys FPGA's IO endpoint driver. | |
d2166319 MS |
585 | |
586 | config MPC83XX_SERDES | |
587 | bool "Enable MPC83xx serdes driver" | |
588 | depends on MISC | |
589 | help | |
590 | Support for serdes found on MPC83xx SoCs. | |
591 | ||
62030004 TFC |
592 | config FS_LOADER |
593 | bool "Enable loader driver for file system" | |
594 | help | |
595 | This is file system generic loader which can be used to load | |
596 | the file image from the storage into target such as memory. | |
597 | ||
598 | The consumer driver would then use this loader to program whatever, | |
599 | ie. the FPGA device. | |
600 | ||
b071a077 K |
601 | config SPL_FS_LOADER |
602 | bool "Enable loader driver for file system" | |
8a1ab5e8 | 603 | depends on SPL |
b071a077 K |
604 | help |
605 | This is file system generic loader which can be used to load | |
606 | the file image from the storage into target such as memory. | |
607 | ||
608 | The consumer driver would then use this loader to program whatever, | |
609 | ie. the FPGA device. | |
610 | ||
c0a2b086 MS |
611 | config GDSYS_SOC |
612 | bool "Enable gdsys SOC driver" | |
613 | depends on MISC | |
614 | help | |
615 | Support for gdsys IHS SOC, a simple bus associated with each gdsys | |
616 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose | |
617 | register maps are contained within the FPGA's register map. | |
618 | ||
ab88bd2b MS |
619 | config IHS_FPGA |
620 | bool "Enable IHS FPGA driver" | |
621 | depends on MISC | |
622 | help | |
623 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on | |
624 | gdsys devices, which supply the majority of the functionality offered | |
625 | by the devices. This driver supports both CON and CPU variants of the | |
626 | devices, depending on the device tree entry. | |
344eb6d5 TK |
627 | config ESM_K3 |
628 | bool "Enable K3 ESM driver" | |
629 | depends on ARCH_K3 | |
630 | help | |
631 | Support ESM (Error Signaling Module) on TI K3 SoCs. | |
ab88bd2b | 632 | |
f8164958 EH |
633 | config MICROCHIP_FLEXCOM |
634 | bool "Enable Microchip Flexcom driver" | |
635 | depends on MISC | |
636 | help | |
637 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, | |
638 | an I2C controller and an USART. | |
639 | Only one function can be used at a time and is chosen at boot time | |
640 | according to the device tree. | |
641 | ||
9d233b4e TK |
642 | config K3_AVS0 |
643 | depends on ARCH_K3 && SPL_DM_REGULATOR | |
644 | bool "AVS class 0 support for K3 devices" | |
645 | help | |
646 | K3 devices have the optimized voltage values for the main voltage | |
647 | domains stored in efuse within the VTM IP. This driver reads the | |
648 | optimized voltage from the efuse, so that it can be programmed | |
649 | to the PMIC on board. | |
650 | ||
3b36b38f TK |
651 | config ESM_PMIC |
652 | bool "Enable PMIC ESM driver" | |
653 | depends on DM_PMIC | |
654 | help | |
655 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used | |
656 | typically to reboot the board in error condition. | |
657 | ||
98ab831d TR |
658 | config FSL_IFC |
659 | bool | |
660 | ||
42595eb7 MW |
661 | config SL28CPLD |
662 | bool "Enable Kontron sl28cpld multi-function driver" | |
663 | depends on DM_I2C | |
664 | help | |
665 | Support for the Kontron sl28cpld management controller. This is | |
666 | the base driver which provides common access methods for the | |
667 | sub-drivers. | |
668 | ||
0b11dbf7 | 669 | endmenu |