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31b1e17f SA |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
cd69e8ef | 3 | * Copyright (C) 2018-2019 Toradex AG |
31b1e17f | 4 | */ |
03de305e | 5 | #include <config.h> |
5255932f | 6 | #include <init.h> |
401d1c4f | 7 | #include <asm/global_data.h> |
c05ed00a | 8 | #include <linux/delay.h> |
cd69e8ef | 9 | |
31b1e17f SA |
10 | #include <asm/arch/clock.h> |
11 | #include <asm/arch/crm_regs.h> | |
12 | #include <asm/arch/imx-regs.h> | |
13 | #include <asm/arch-mx6/clock.h> | |
14 | #include <asm/arch-mx6/imx-regs.h> | |
15 | #include <asm/arch-mx6/mx6ull_pins.h> | |
16 | #include <asm/arch/sys_proto.h> | |
17 | #include <asm/gpio.h> | |
18 | #include <asm/mach-imx/boot_mode.h> | |
19 | #include <asm/mach-imx/iomux-v3.h> | |
20 | #include <asm/io.h> | |
31b1e17f SA |
21 | #include <dm.h> |
22 | #include <dm/platform_data/serial_mxc.h> | |
9fb625ce | 23 | #include <env.h> |
31b1e17f | 24 | #include <fdt_support.h> |
31b1e17f SA |
25 | #include <imx_thermal.h> |
26 | #include <jffs2/load_kernel.h> | |
27 | #include <linux/sizes.h> | |
31b1e17f SA |
28 | #include <miiphy.h> |
29 | #include <mtd_node.h> | |
30 | #include <netdev.h> | |
cd69e8ef | 31 | |
31b1e17f | 32 | #include "../common/tdx-common.h" |
1560e12e | 33 | #include "../common/tdx-cfg-block.h" |
31b1e17f SA |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
31b1e17f SA |
37 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ |
38 | PAD_CTL_DSE_48ohm) | |
39 | ||
c2f38bf0 PS |
40 | #define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040 |
41 | ||
31b1e17f SA |
42 | #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) |
43 | ||
44 | #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) | |
45 | ||
80ef6926 MK |
46 | #define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE) |
47 | #define FLASH_DET_GPIO IMX_GPIO_NR(4, 1) | |
48 | static const iomux_v3_cfg_t flash_detection_pads[] = { | |
49 | MX6_PAD_NAND_WE_B__GPIO4_IO01 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), | |
50 | }; | |
51 | ||
52 | static bool is_emmc; | |
53 | ||
31b1e17f SA |
54 | int dram_init(void) |
55 | { | |
56 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); | |
57 | ||
58 | return 0; | |
59 | } | |
60 | ||
31b1e17f | 61 | #ifdef CONFIG_NAND_MXS |
31b1e17f SA |
62 | static void setup_gpmi_nand(void) |
63 | { | |
936bf172 PS |
64 | setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | |
65 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
66 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); | |
31b1e17f | 67 | } |
cd69e8ef | 68 | #endif /* CONFIG_NAND_MXS */ |
31b1e17f | 69 | |
b86986c7 | 70 | #ifdef CONFIG_VIDEO |
80ef6926 | 71 | static const iomux_v3_cfg_t backlight_pads[] = { |
31b1e17f SA |
72 | /* Backlight On */ |
73 | MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
74 | /* Backlight PWM<A> (multiplexed pin) */ | |
75 | MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
76 | }; | |
77 | ||
78 | #define GPIO_BL_ON IMX_GPIO_NR(1, 11) | |
79 | #define GPIO_PWM_A IMX_GPIO_NR(4, 11) | |
80 | ||
81 | static int setup_lcd(void) | |
82 | { | |
31b1e17f SA |
83 | imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); |
84 | ||
85 | /* Set BL_ON */ | |
86 | gpio_request(GPIO_BL_ON, "BL_ON"); | |
87 | gpio_direction_output(GPIO_BL_ON, 1); | |
88 | ||
89 | /* Set PWM<A> to full brightness (assuming inversed polarity) */ | |
90 | gpio_request(GPIO_PWM_A, "PWM<A>"); | |
91 | gpio_direction_output(GPIO_PWM_A, 0); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | #endif | |
96 | ||
31b1e17f | 97 | #ifdef CONFIG_FEC_MXC |
31b1e17f SA |
98 | static int setup_fec(void) |
99 | { | |
100 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
101 | int ret; | |
102 | ||
aa6f57d8 PS |
103 | /* |
104 | * Use 50MHz anatop loopback REF_CLK2 for ENET2, | |
105 | * clear gpr1[14], set gpr1[18]. | |
106 | */ | |
107 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, | |
108 | IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); | |
109 | ||
31b1e17f SA |
110 | ret = enable_fec_anatop_clock(1, ENET_50MHZ); |
111 | if (ret) | |
112 | return ret; | |
113 | ||
aa6f57d8 | 114 | enable_enet_clk(1); |
70a0467b | 115 | |
31b1e17f SA |
116 | return 0; |
117 | } | |
cd69e8ef | 118 | #endif /* CONFIG_FEC_MXC */ |
31b1e17f SA |
119 | |
120 | int board_init(void) | |
121 | { | |
122 | /* address of boot parameters */ | |
123 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
124 | ||
80ef6926 MK |
125 | /* |
126 | * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST | |
127 | * is pulled high with 4.7k for eMMC devices. This allows to reliably | |
128 | * detect eMMC/NAND flash | |
129 | */ | |
130 | imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); | |
131 | gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); | |
132 | is_emmc = gpio_get_value(FLASH_DET_GPIO); | |
133 | gpio_free(FLASH_DET_GPIO); | |
134 | ||
31b1e17f SA |
135 | #ifdef CONFIG_FEC_MXC |
136 | setup_fec(); | |
137 | #endif | |
138 | ||
139 | #ifdef CONFIG_NAND_MXS | |
140 | setup_gpmi_nand(); | |
141 | #endif | |
31b1e17f SA |
142 | return 0; |
143 | } | |
144 | ||
145 | #ifdef CONFIG_CMD_BMODE | |
146 | /* TODO */ | |
147 | static const struct boot_mode board_boot_modes[] = { | |
148 | /* 4 bit bus width */ | |
149 | {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, | |
150 | {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, | |
151 | {NULL, 0}, | |
152 | }; | |
153 | #endif | |
154 | ||
155 | int board_late_init(void) | |
156 | { | |
1560e12e SA |
157 | #ifdef CONFIG_TDX_CFG_BLOCK |
158 | /* | |
159 | * If we have a valid config block and it says we are a module with | |
160 | * Wi-Fi/Bluetooth make sure we use the -wifi device tree. | |
161 | */ | |
162 | if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT || | |
80ef6926 | 163 | tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) { |
31b1e17f | 164 | env_set("variant", "-wifi"); |
80ef6926 MK |
165 | } else { |
166 | if (is_emmc) | |
167 | env_set("variant", "-emmc"); | |
885dcc36 PS |
168 | else |
169 | env_set("variant", ""); | |
80ef6926 MK |
170 | } |
171 | #else | |
172 | if (is_emmc) | |
173 | env_set("variant", "-emmc"); | |
885dcc36 PS |
174 | else |
175 | env_set("variant", ""); | |
1560e12e | 176 | #endif |
31b1e17f | 177 | |
c2f38bf0 PS |
178 | /* |
179 | * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the | |
180 | * SOC to request for a lower voltage during sleep. This is necessary | |
181 | * because the voltage is changing too slow for the SOC to wake up | |
182 | * properly. | |
183 | */ | |
184 | __raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR); | |
185 | ||
31b1e17f SA |
186 | #ifdef CONFIG_CMD_BMODE |
187 | add_board_boot_modes(board_boot_modes); | |
188 | #endif | |
189 | ||
220bb4e1 | 190 | if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { |
31b1e17f | 191 | env_set("bootdelay", "0"); |
220bb4e1 HDF |
192 | if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { |
193 | printf("Serial Downloader recovery mode, using sdp command\n"); | |
194 | env_set("bootcmd", "sdp 0"); | |
195 | } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { | |
196 | printf("Fastboot recovery mode, using fastboot command\n"); | |
197 | env_set("bootcmd", "fastboot usb 0"); | |
198 | } | |
31b1e17f | 199 | } |
31b1e17f | 200 | |
b86986c7 | 201 | #if defined(CONFIG_VIDEO) |
391c712d | 202 | setup_lcd(); |
391c712d IO |
203 | #endif |
204 | ||
31b1e17f SA |
205 | return 0; |
206 | } | |
207 | ||
31b1e17f | 208 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
b75d8dc5 | 209 | int ft_board_setup(void *blob, struct bd_info *bd) |
31b1e17f | 210 | { |
31b1e17f SA |
211 | return ft_common_board_setup(blob, bd); |
212 | } | |
213 | #endif | |
214 | ||
8a8d24bd | 215 | static struct mxc_serial_plat mxc_serial_plat = { |
31b1e17f SA |
216 | .reg = (struct mxc_uart *)UART1_BASE, |
217 | .use_dte = 1, | |
218 | }; | |
219 | ||
20e442ab | 220 | U_BOOT_DRVINFO(mxc_serial) = { |
31b1e17f | 221 | .name = "serial_mxc", |
caa4daa2 | 222 | .plat = &mxc_serial_plat, |
31b1e17f | 223 | }; |