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odroid-c2: enable GPIO
[J-u-boot.git] / board / ti / am57xx / board.c
CommitLineData
1e4ad74b
FB		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
3 *
4 * Author: Felipe Balbi <[email protected]>
5 *
6 * Based on board/ti/dra7xx/evm.c
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <palmas.h>
13#include <sata.h>
14#include <usb.h>
15#include <asm/omap_common.h>
17c29873 16#include <asm/omap_sec_common.h>
1e4ad74b 17#include <asm/emif.h>
334bbb38
LV		 18#include <asm/gpio.h>
19#include <asm/arch/gpio.h>
1e4ad74b 20#include <asm/arch/clock.h>
f91e0c4c 21#include <asm/arch/dra7xx_iodelay.h>
1e4ad74b
FB		 22#include <asm/arch/sys_proto.h>
23#include <asm/arch/mmc_host_def.h>
24#include <asm/arch/sata.h>
25#include <asm/arch/gpio.h>
7c379aaa 26#include <asm/arch/omap.h>
1e4ad74b 27#include <environment.h>
7c379aaa
KVA		 28#include <usb.h>
29#include <linux/usb/gadget.h>
30#include <dwc3-uboot.h>
31#include <dwc3-omap-uboot.h>
32#include <ti-usb-phy-uboot.h>
1e4ad74b 33
212f96f6 34#include "../common/board_detect.h"
1e4ad74b
FB		 35#include "mux_data.h"
36
212f96f6 37#define board_is_x15() board_ti_is("BBRDX15_")
f7f9f6be
LV		 38#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
212f96f6 40#define board_is_am572x_evm() board_ti_is("AM572PM_")
bf43ce6c
NM		 41#define board_is_am572x_evm_reva3() \
42 (board_ti_is("AM572PM_") && \
43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
c020d355 44#define board_is_am572x_idk() board_ti_is("AM572IDK")
4d8397c6 45#define board_is_am571x_idk() board_ti_is("AM571IDK")
212f96f6 46
1e4ad74b
FB		 47#ifdef CONFIG_DRIVER_TI_CPSW
48#include <cpsw.h>
49#endif
50
51DECLARE_GLOBAL_DATA_PTR;
52
37611052 53#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
334bbb38
LV		 54/* GPIO 7_11 */
55#define GPIO_DDR_VTT_EN 203
56
fcb18524
NM		 57/* Touch screen controller to identify the LCD */
58#define OSD_TS_FT_BUS_ADDRESS 0
59#define OSD_TS_FT_CHIP_ADDRESS 0x38
60#define OSD_TS_FT_REG_ID 0xA3
61/*
62 * Touchscreen IDs for various OSD panels
63 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
64 */
65/* Used on newer osd101t2587 Panels */
66#define OSD_TS_FT_ID_5x46 0x54
67/* Used on older osd101t2045 Panels */
68#define OSD_TS_FT_ID_5606 0x08
69
212f96f6
KS		 70#define SYSINFO_BOARD_NAME_MAX_LEN 45
71
385d3632
K		 72#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
73#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
74
1e4ad74b 75const struct omap_sysinfo sysinfo = {
212f96f6 76 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
1e4ad74b
FB		 77};
78
79static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
80 .dmm_lisa_map_3 = 0x80740300,
81 .is_ma_present = 0x1
82};
83
4d8397c6
SK		 84static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
85 .dmm_lisa_map_3 = 0x80640100,
86 .is_ma_present = 0x1
87};
88
1e4ad74b
FB		 89void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
90{
4d8397c6
SK		 91 if (board_is_am571x_idk())
92 *dmm_lisa_regs = &am571x_idk_lisa_regs;
93 else
94 *dmm_lisa_regs = &beagle_x15_lisa_regs;
1e4ad74b
FB		 95}
96
97static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
eafd4644
K		 98 .sdram_config_init = 0x61851b32,
99 .sdram_config = 0x61851b32,
100 .sdram_config2 = 0x08000000,
101 .ref_ctrl = 0x000040F1,
102 .ref_ctrl_final = 0x00001035,
103 .sdram_tim1 = 0xcccf36ab,
104 .sdram_tim2 = 0x308f7fda,
105 .sdram_tim3 = 0x409f88a8,
106 .read_idle_ctrl = 0x00050000,
107 .zq_config = 0x5007190b,
108 .temp_alert_config = 0x00000000,
109 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
110 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
111 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
112 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
113 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
114 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
115 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
116 .emif_rd_wr_lvl_rmp_win = 0x00000000,
117 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
118 .emif_rd_wr_lvl_ctl = 0x00000000,
119 .emif_rd_wr_exec_thresh = 0x00000305
1e4ad74b
FB		 120};
121
6213db78 122/* Ext phy ctrl regs 1-35 */
1e4ad74b 123static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
6213db78 124 0x10040100,
11e2b043
LV		 125 0x00910091,
126 0x00950095,
127 0x009B009B,
128 0x009E009E,
129 0x00980098,
1e4ad74b 130 0x00340034,
1e4ad74b 131 0x00350035,
11e2b043
LV		 132 0x00340034,
133 0x00310031,
134 0x00340034,
135 0x007F007F,
136 0x007F007F,
137 0x007F007F,
138 0x007F007F,
139 0x007F007F,
140 0x00480048,
141 0x004A004A,
142 0x00520052,
143 0x00550055,
144 0x00500050,
1e4ad74b
FB		 145 0x00000000,
146 0x00600020,
6213db78 147 0x40011080,
1e4ad74b 148 0x08102040,
11e2b043
LV		 149 0x0,
150 0x0,
151 0x0,
152 0x0,
153 0x0,
496edffd
LV		 154 0x0,
155 0x0,
156 0x0,
157 0x0,
158 0x0
1e4ad74b
FB		 159};
160
161static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
eafd4644
K		 162 .sdram_config_init = 0x61851b32,
163 .sdram_config = 0x61851b32,
164 .sdram_config2 = 0x08000000,
165 .ref_ctrl = 0x000040F1,
166 .ref_ctrl_final = 0x00001035,
167 .sdram_tim1 = 0xcccf36b3,
168 .sdram_tim2 = 0x308f7fda,
169 .sdram_tim3 = 0x407f88a8,
170 .read_idle_ctrl = 0x00050000,
171 .zq_config = 0x5007190b,
172 .temp_alert_config = 0x00000000,
173 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
174 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
175 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
176 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
177 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
178 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
179 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
180 .emif_rd_wr_lvl_rmp_win = 0x00000000,
181 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
182 .emif_rd_wr_lvl_ctl = 0x00000000,
183 .emif_rd_wr_exec_thresh = 0x00000305
1e4ad74b
FB		 184};
185
186static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
6213db78 187 0x10040100,
11e2b043
LV		 188 0x00910091,
189 0x00950095,
190 0x009B009B,
191 0x009E009E,
192 0x00980098,
193 0x00340034,
1e4ad74b 194 0x00350035,
11e2b043
LV		 195 0x00340034,
196 0x00310031,
197 0x00340034,
198 0x007F007F,
199 0x007F007F,
200 0x007F007F,
201 0x007F007F,
202 0x007F007F,
203 0x00480048,
204 0x004A004A,
205 0x00520052,
206 0x00550055,
207 0x00500050,
1e4ad74b
FB		 208 0x00000000,
209 0x00600020,
6213db78 210 0x40011080,
1e4ad74b 211 0x08102040,
11e2b043
LV		 212 0x0,
213 0x0,
214 0x0,
215 0x0,
216 0x0,
496edffd
LV		 217 0x0,
218 0x0,
219 0x0,
220 0x0,
221 0x0
1e4ad74b
FB		 222};
223
224void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
225{
226 switch (emif_nr) {
227 case 1:
228 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
229 break;
230 case 2:
231 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
232 break;
233 }
234}
235
236void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
237{
238 switch (emif_nr) {
239 case 1:
240 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
241 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
242 break;
243 case 2:
244 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
245 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
246 break;
247 }
248}
249
250struct vcores_data beagle_x15_volts = {
beb71279
LV		 251 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
252 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
1e4ad74b
FB		 253 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
254 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
255 .mpu.pmic = &tps659038,
eafd4644 256 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
1e4ad74b 257
beb71279
LV		 258 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
259 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
260 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
261 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
262 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
263 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
1e4ad74b
FB		 264 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
265 .eve.addr = TPS659038_REG_ADDR_SMPS45,
266 .eve.pmic = &tps659038,
e52e334e 267 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
1e4ad74b 268
beb71279
LV		 269 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
270 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
271 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
272 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
273 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
274 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
1e4ad74b
FB		 275 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
276 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
277 .gpu.pmic = &tps659038,
e52e334e 278 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
1e4ad74b 279
beb71279
LV		 280 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
281 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
1e4ad74b
FB		 282 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
283 .core.addr = TPS659038_REG_ADDR_SMPS6,
284 .core.pmic = &tps659038,
285
beb71279
LV		 286 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
287 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
288 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
289 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
290 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
291 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
1e4ad74b
FB		 292 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
293 .iva.addr = TPS659038_REG_ADDR_SMPS45,
294 .iva.pmic = &tps659038,
e52e334e 295 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
1e4ad74b
FB		 296};
297
d60198da 298struct vcores_data am572x_idk_volts = {
beb71279
LV		 299 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
300 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
d60198da
K		 301 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
302 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
303 .mpu.pmic = &tps659038,
304 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
305
beb71279
LV		 306 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
307 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
308 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
309 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
310 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
311 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
d60198da
K		 312 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
313 .eve.addr = TPS659038_REG_ADDR_SMPS45,
314 .eve.pmic = &tps659038,
315 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
316
beb71279
LV		 317 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
318 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
319 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
320 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
321 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
322 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
d60198da
K		 323 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
324 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
325 .gpu.pmic = &tps659038,
326 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
327
beb71279
LV		 328 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
329 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
d60198da
K		 330 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
331 .core.addr = TPS659038_REG_ADDR_SMPS7,
332 .core.pmic = &tps659038,
333
beb71279
LV		 334 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
335 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
336 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
337 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
338 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
339 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
d60198da
K		 340 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
341 .iva.addr = TPS659038_REG_ADDR_SMPS8,
342 .iva.pmic = &tps659038,
343 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
344};
345
b12550eb
K		 346struct vcores_data am571x_idk_volts = {
347 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
348 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
349 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
350 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
351 .mpu.pmic = &tps659038,
352 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
353
354 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
355 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
356 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
357 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
358 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
359 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
360 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
361 .eve.addr = TPS659038_REG_ADDR_SMPS45,
362 .eve.pmic = &tps659038,
363 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
364
365 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
366 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
367 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
368 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
369 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
370 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
371 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
372 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
373 .gpu.pmic = &tps659038,
374 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
375
376 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
377 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
378 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
379 .core.addr = TPS659038_REG_ADDR_SMPS7,
380 .core.pmic = &tps659038,
381
382 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
383 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
384 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
385 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
386 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
387 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
388 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
389 .iva.addr = TPS659038_REG_ADDR_SMPS45,
390 .iva.pmic = &tps659038,
391 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
392};
393
beb71279
LV		 394int get_voltrail_opp(int rail_offset)
395{
396 int opp;
397
398 switch (rail_offset) {
399 case VOLT_MPU:
400 opp = DRA7_MPU_OPP;
401 break;
402 case VOLT_CORE:
403 opp = DRA7_CORE_OPP;
404 break;
405 case VOLT_GPU:
406 opp = DRA7_GPU_OPP;
407 break;
408 case VOLT_EVE:
409 opp = DRA7_DSPEVE_OPP;
410 break;
411 case VOLT_IVA:
412 opp = DRA7_IVA_OPP;
413 break;
414 default:
415 opp = OPP_NOM;
416 }
417
418 return opp;
419}
420
421
212f96f6
KS		 422#ifdef CONFIG_SPL_BUILD
423/* No env to setup for SPL */
424static inline void setup_board_eeprom_env(void) { }
425
426/* Override function to read eeprom information */
427void do_board_detect(void)
428{
429 int rc;
430
431 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
432 CONFIG_EEPROM_CHIP_ADDRESS);
433 if (rc)
434 printf("ti_i2c_eeprom_init failed %d\n", rc);
435}
436
437#else /* CONFIG_SPL_BUILD */
438
439/* Override function to read eeprom information: actual i2c read done by SPL*/
440void do_board_detect(void)
441{
442 char *bname = NULL;
443 int rc;
444
445 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
446 CONFIG_EEPROM_CHIP_ADDRESS);
447 if (rc)
448 printf("ti_i2c_eeprom_init failed %d\n", rc);
449
450 if (board_is_x15())
451 bname = "BeagleBoard X15";
452 else if (board_is_am572x_evm())
453 bname = "AM572x EVM";
c020d355
SK		 454 else if (board_is_am572x_idk())
455 bname = "AM572x IDK";
4d8397c6
SK		 456 else if (board_is_am571x_idk())
457 bname = "AM571x IDK";
212f96f6
KS		 458
459 if (bname)
460 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
461 "Board: %s REV %s\n", bname, board_ti_get_rev());
462}
463
464static void setup_board_eeprom_env(void)
465{
466 char *name = "beagle_x15";
467 int rc;
468
469 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
470 CONFIG_EEPROM_CHIP_ADDRESS);
471 if (rc)
472 goto invalid_eeprom;
473
bf43ce6c 474 if (board_is_x15()) {
f7f9f6be
LV		 475 if (board_is_x15_revb1())
476 name = "beagle_x15_revb1";
477 else
478 name = "beagle_x15";
bf43ce6c
NM		 479 } else if (board_is_am572x_evm()) {
480 if (board_is_am572x_evm_reva3())
481 name = "am57xx_evm_reva3";
482 else
483 name = "am57xx_evm";
484 } else if (board_is_am572x_idk()) {
c020d355 485 name = "am572x_idk";
4d8397c6
SK		 486 } else if (board_is_am571x_idk()) {
487 name = "am571x_idk";
bf43ce6c 488 } else {
212f96f6
KS		 489 printf("Unidentified board claims %s in eeprom header\n",
490 board_ti_get_name());
bf43ce6c 491 }
212f96f6
KS		 492
493invalid_eeprom:
494 set_board_info_env(name);
495}
496
497#endif /* CONFIG_SPL_BUILD */
498
d60198da
K		 499void vcores_init(void)
500{
501 if (board_is_am572x_idk())
502 *omap_vcores = &am572x_idk_volts;
b12550eb
K		 503 else if (board_is_am571x_idk())
504 *omap_vcores = &am571x_idk_volts;
d60198da
K		 505 else
506 *omap_vcores = &beagle_x15_volts;
507}
508
1e4ad74b
FB		 509void hw_data_init(void)
510{
511 *prcm = &dra7xx_prcm;
512 *dplls_data = &dra7xx_dplls;
1e4ad74b
FB		 513 *ctrl = &dra7xx_ctrl;
514}
515
37611052
RQ		 516bool am571x_idk_needs_lcd(void)
517{
518 bool needs_lcd;
519
520 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
521 if (gpio_get_value(GPIO_ETH_LCD))
522 needs_lcd = false;
523 else
524 needs_lcd = true;
525
526 gpio_free(GPIO_ETH_LCD);
527
528 return needs_lcd;
529}
530
1e4ad74b
FB		 531int board_init(void)
532{
533 gpmc_init();
534 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
535
536 return 0;
537}
538
fcb18524 539void am57x_idk_lcd_detect(void)
1e4ad74b 540{
fcb18524
NM		 541 int r = -ENODEV;
542 char *idk_lcd = "no";
543 uint8_t buf = 0;
544
545 /* Only valid for IDKs */
546 if (board_is_x15() || board_is_am572x_evm())
547 return;
548
549 /* Only AM571x IDK has gpio control detect.. so check that */
550 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
551 goto out;
552
553 r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
554 if (r) {
555 printf("%s: Failed to set bus address to %d: %d\n",
556 __func__, OSD_TS_FT_BUS_ADDRESS, r);
557 goto out;
558 }
559 r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
560 if (r) {
561 /* AM572x IDK has no explicit settings for optional LCD kit */
562 if (board_is_am571x_idk()) {
563 printf("%s: Touch screen detect failed: %d!\n",
564 __func__, r);
565 }
566 goto out;
567 }
568
569 /* Read FT ID */
570 r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
571 if (r) {
572 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
573 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
574 OSD_TS_FT_REG_ID, r);
575 goto out;
576 }
37611052 577
fcb18524
NM		 578 switch (buf) {
579 case OSD_TS_FT_ID_5606:
580 idk_lcd = "osd101t2045";
581 break;
582 case OSD_TS_FT_ID_5x46:
583 idk_lcd = "osd101t2587";
584 break;
585 default:
586 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
587 __func__, buf);
588 /* we will let default be "no lcd" */
589 }
590out:
591 setenv("idk_lcd", idk_lcd);
592 return;
593}
594
595int board_late_init(void)
596{
212f96f6 597 setup_board_eeprom_env();
385d3632 598 u8 val;
212f96f6 599
1e4ad74b
FB		 600 /*
601 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
602 * This is the POWERHOLD-in-Low behavior.
603 */
604 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
82cca5a6
LV		 605
606 /*
607 * Default FIT boot on HS devices. Non FIT images are not allowed
608 * on HS devices.
609 */
610 if (get_device_type() == HS_DEVICE)
611 setenv("boot_fit", "1");
612
385d3632
K		 613 /*
614 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
615 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
616 * PMIC Power off. So to be on the safer side set it back
617 * to POWERHOLD mode irrespective of the current state.
618 */
619 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
620 &val);
621 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
622 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
623 val);
624
7a2af751 625 omap_die_id_serial();
8bd29623 626 omap_set_fastboot_vars();
7a2af751 627
fcb18524 628 am57x_idk_lcd_detect();
37611052
RQ		 629
630#if !defined(CONFIG_SPL_BUILD)
631 board_ti_set_ethaddr(2);
632#endif
633
1e4ad74b
FB		 634 return 0;
635}
636
3ef56e61 637void set_muxconf_regs(void)
1e4ad74b
FB		 638{
639 do_set_mux32((*ctrl)->control_padconf_core_base,
f91e0c4c 640 early_padconf, ARRAY_SIZE(early_padconf));
1e4ad74b
FB		 641}
642
f91e0c4c
LV		 643#ifdef CONFIG_IODELAY_RECALIBRATION
644void recalibrate_iodelay(void)
645{
c020d355 646 const struct pad_conf_entry *pconf;
2d7e9e9d
LV		 647 const struct iodelay_cfg_entry *iod, *delta_iod;
648 int pconf_sz, iod_sz, delta_iod_sz = 0;
89a38953 649 int ret;
c020d355
SK		 650
651 if (board_is_am572x_idk()) {
652 pconf = core_padconf_array_essential_am572x_idk;
653 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
654 iod = iodelay_cfg_array_am572x_idk;
655 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
4d8397c6
SK		 656 } else if (board_is_am571x_idk()) {
657 pconf = core_padconf_array_essential_am571x_idk;
658 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
659 iod = iodelay_cfg_array_am571x_idk;
660 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
c020d355
SK		 661 } else {
662 /* Common for X15/GPEVM */
663 pconf = core_padconf_array_essential_x15;
664 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
89a38953
NM		 665 /* There never was an SR1.0 X15.. So.. */
666 if (omap_revision() == DRA752_ES1_1) {
667 iod = iodelay_cfg_array_x15_sr1_1;
668 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
669 } else {
670 /* Since full production should switch to SR2.0 */
671 iod = iodelay_cfg_array_x15_sr2_0;
672 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
673 }
c020d355
SK		 674 }
675
89a38953
NM		 676 /* Setup I/O isolation */
677 ret = __recalibrate_iodelay_start();
678 if (ret)
679 goto err;
680
681 /* Do the muxing here */
682 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
683
684 /* Now do the weird minor deltas that should be safe */
685 if (board_is_x15() || board_is_am572x_evm()) {
686 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
687 pconf = core_padconf_array_delta_x15_sr2_0;
688 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
689 } else {
690 pconf = core_padconf_array_delta_x15_sr1_1;
691 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
692 }
693 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
694 }
695
37611052
RQ		 696 if (board_is_am571x_idk()) {
697 if (am571x_idk_needs_lcd()) {
698 pconf = core_padconf_array_vout_am571x_idk;
699 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
2d7e9e9d
LV		 700 delta_iod = iodelay_cfg_array_am571x_idk_4port;
701 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
702
37611052
RQ		 703 } else {
704 pconf = core_padconf_array_icss1eth_am571x_idk;
705 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
706 }
707 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
708 }
709
89a38953
NM		 710 /* Setup IOdelay configuration */
711 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
2d7e9e9d
LV		 712 if (delta_iod_sz)
713 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
714 delta_iod_sz);
715
89a38953
NM		 716err:
717 /* Closeup.. remove isolation */
718 __recalibrate_iodelay_end(ret);
f91e0c4c
LV		 719}
720#endif
721
4aa2ba3a 722#if defined(CONFIG_MMC)
1e4ad74b
FB		 723int board_mmc_init(bd_t *bis)
724{
725 omap_mmc_init(0, 0, 0, -1, -1);
726 omap_mmc_init(1, 0, 0, -1, -1);
727 return 0;
728}
729#endif
730
731#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
732int spl_start_uboot(void)
733{
734 /* break into full u-boot on 'c' */
735 if (serial_tstc() && serial_getc() == 'c')
736 return 1;
737
738#ifdef CONFIG_SPL_ENV_SUPPORT
739 env_init();
740 env_relocate_spec();
741 if (getenv_yesno("boot_os") != 1)
742 return 1;
743#endif
744
745 return 0;
746}
747#endif
748
7c379aaa 749#ifdef CONFIG_USB_DWC3
7c379aaa
KVA		 750static struct dwc3_device usb_otg_ss2 = {
751 .maximum_speed = USB_SPEED_HIGH,
752 .base = DRA7_USB_OTG_SS2_BASE,
753 .tx_fifo_resize = false,
754 .index = 1,
755};
756
757static struct dwc3_omap_device usb_otg_ss2_glue = {
758 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
759 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
760 .index = 1,
761};
762
763static struct ti_usb_phy_device usb_phy2_device = {
764 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
765 .index = 1,
766};
767
55efadde
RQ		 768int usb_gadget_handle_interrupts(int index)
769{
770 u32 status;
771
772 status = dwc3_omap_uboot_interrupt_status(index);
773 if (status)
774 dwc3_uboot_handle_interrupt(index);
775
776 return 0;
777}
778#endif /* CONFIG_USB_DWC3 */
779
780#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
1a9a5f7a 781int omap_xhci_board_usb_init(int index, enum usb_init_type init)
7c379aaa 782{
6f1af1e3 783 enable_usb_clocks(index);
7c379aaa
KVA		 784 switch (index) {
785 case 0:
786 if (init == USB_INIT_DEVICE) {
787 printf("port %d can't be used as device\n", index);
6f1af1e3 788 disable_usb_clocks(index);
7c379aaa 789 return -EINVAL;
7c379aaa 790 }
7c379aaa
KVA		 791 break;
792 case 1:
793 if (init == USB_INIT_DEVICE) {
55efadde 794#ifdef CONFIG_USB_DWC3
7c379aaa
KVA		 795 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
796 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
55efadde
RQ		 797 ti_usb_phy_uboot_init(&usb_phy2_device);
798 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
799 dwc3_uboot_init(&usb_otg_ss2);
800#endif
7c379aaa
KVA		 801 } else {
802 printf("port %d can't be used as host\n", index);
6f1af1e3 803 disable_usb_clocks(index);
7c379aaa
KVA		 804 return -EINVAL;
805 }
806
7c379aaa
KVA		 807 break;
808 default:
809 printf("Invalid Controller Index\n");
810 }
811
812 return 0;
813}
814
1a9a5f7a 815int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
7c379aaa 816{
55efadde 817#ifdef CONFIG_USB_DWC3
7c379aaa
KVA		 818 switch (index) {
819 case 0:
820 case 1:
55efadde
RQ		 821 if (init == USB_INIT_DEVICE) {
822 ti_usb_phy_uboot_exit(index);
823 dwc3_uboot_exit(index);
824 dwc3_omap_uboot_exit(index);
825 }
7c379aaa
KVA		 826 break;
827 default:
828 printf("Invalid Controller Index\n");
829 }
55efadde 830#endif
6f1af1e3 831 disable_usb_clocks(index);
7c379aaa
KVA		 832 return 0;
833}
55efadde 834#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
7c379aaa 835
1e4ad74b
FB		 836#ifdef CONFIG_DRIVER_TI_CPSW
837
838/* Delay value to add to calibrated value */
839#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
840#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
841#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
842#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
843#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
844#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
845#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
846#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
847#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
848#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
849
850static void cpsw_control(int enabled)
851{
852 /* VTP can be added here */
853}
854
855static struct cpsw_slave_data cpsw_slaves[] = {
856 {
857 .slave_reg_ofs = 0x208,
858 .sliver_reg_ofs = 0xd80,
859 .phy_addr = 1,
860 },
861 {
862 .slave_reg_ofs = 0x308,
863 .sliver_reg_ofs = 0xdc0,
864 .phy_addr = 2,
865 },
866};
867
868static struct cpsw_platform_data cpsw_data = {
869 .mdio_base = CPSW_MDIO_BASE,
870 .cpsw_base = CPSW_BASE,
871 .mdio_div = 0xff,
872 .channels = 8,
873 .cpdma_reg_ofs = 0x800,
874 .slaves = 1,
875 .slave_data = cpsw_slaves,
876 .ale_reg_ofs = 0xd00,
877 .ale_entries = 1024,
878 .host_port_reg_ofs = 0x108,
879 .hw_stats_reg_ofs = 0x900,
880 .bd_ram_ofs = 0x2000,
881 .mac_control = (1 << 5),
882 .control = cpsw_control,
883 .host_port_num = 0,
884 .version = CPSW_CTRL_VERSION_2,
885};
886
92667e89
RQ		 887static u64 mac_to_u64(u8 mac[6])
888{
889 int i;
890 u64 addr = 0;
891
892 for (i = 0; i < 6; i++) {
893 addr <<= 8;
894 addr |= mac[i];
895 }
896
897 return addr;
898}
899
900static void u64_to_mac(u64 addr, u8 mac[6])
901{
902 mac[5] = addr;
903 mac[4] = addr >> 8;
904 mac[3] = addr >> 16;
905 mac[2] = addr >> 24;
906 mac[1] = addr >> 32;
907 mac[0] = addr >> 40;
908}
909
1e4ad74b
FB		 910int board_eth_init(bd_t *bis)
911{
912 int ret;
913 uint8_t mac_addr[6];
914 uint32_t mac_hi, mac_lo;
915 uint32_t ctrl_val;
92667e89
RQ		 916 int i;
917 u64 mac1, mac2;
918 u8 mac_addr1[6], mac_addr2[6];
919 int num_macs;
1e4ad74b
FB		 920
921 /* try reading mac address from efuse */
922 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
923 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
924 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
925 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
926 mac_addr[2] = mac_hi & 0xFF;
927 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
928 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
929 mac_addr[5] = mac_lo & 0xFF;
930
931 if (!getenv("ethaddr")) {
932 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
933
0adb5b76 934 if (is_valid_ethaddr(mac_addr))
1e4ad74b
FB		 935 eth_setenv_enetaddr("ethaddr", mac_addr);
936 }
937
938 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
939 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
940 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
941 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
942 mac_addr[2] = mac_hi & 0xFF;
943 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
944 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
945 mac_addr[5] = mac_lo & 0xFF;
946
947 if (!getenv("eth1addr")) {
0adb5b76 948 if (is_valid_ethaddr(mac_addr))
1e4ad74b
FB		 949 eth_setenv_enetaddr("eth1addr", mac_addr);
950 }
951
952 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
953 ctrl_val |= 0x22;
954 writel(ctrl_val, (*ctrl)->control_core_control_io1);
955
4d8397c6
SK		 956 /* The phy address for the AM57xx IDK are different than x15 */
957 if (board_is_am572x_idk() || board_is_am571x_idk()) {
c020d355
SK		 958 cpsw_data.slave_data[0].phy_addr = 0;
959 cpsw_data.slave_data[1].phy_addr = 1;
960 }
961
1e4ad74b
FB		 962 ret = cpsw_register(&cpsw_data);
963 if (ret < 0)
964 printf("Error %d registering CPSW switch\n", ret);
965
92667e89
RQ		 966 /*
967 * Export any Ethernet MAC addresses from EEPROM.
968 * On AM57xx the 2 MAC addresses define the address range
969 */
970 board_ti_get_eth_mac_addr(0, mac_addr1);
971 board_ti_get_eth_mac_addr(1, mac_addr2);
972
973 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
974 mac1 = mac_to_u64(mac_addr1);
975 mac2 = mac_to_u64(mac_addr2);
976
977 /* must contain an address range */
978 num_macs = mac2 - mac1 + 1;
979 /* <= 50 to protect against user programming error */
980 if (num_macs > 0 && num_macs <= 50) {
981 for (i = 0; i < num_macs; i++) {
982 u64_to_mac(mac1 + i, mac_addr);
983 if (is_valid_ethaddr(mac_addr)) {
984 eth_setenv_enetaddr_by_index("eth",
985 i + 2,
986 mac_addr);
987 }
988 }
989 }
990 }
991
1e4ad74b
FB		 992 return ret;
993}
994#endif
334bbb38
LV		 995
996#ifdef CONFIG_BOARD_EARLY_INIT_F
997/* VTT regulator enable */
998static inline void vtt_regulator_enable(void)
999{
1000 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1001 return;
1002
1003 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1004 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1005}
1006
1007int board_early_init_f(void)
1008{
1009 vtt_regulator_enable();
1010 return 0;
1011}
1012#endif
62a09f05
DA		 1013
1014#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1015int ft_board_setup(void *blob, bd_t *bd)
1016{
1017 ft_cpu_setup(blob, bd);
1018
1019 return 0;
1020}
1021#endif
7a0ea589
LV		 1022
1023#ifdef CONFIG_SPL_LOAD_FIT
1024int board_fit_config_name_match(const char *name)
1025{
f7f9f6be
LV		 1026 if (board_is_x15()) {
1027 if (board_is_x15_revb1()) {
1028 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1029 return 0;
1030 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1031 return 0;
1032 }
1033 } else if (board_is_am572x_evm() &&
1034 !strcmp(name, "am57xx-beagle-x15")) {
7a0ea589 1035 return 0;
f7f9f6be 1036 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
332dddc6 1037 return 0;
45e7f7e7
SP		 1038 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1039 return 0;
f7f9f6be
LV		 1040 }
1041
1042 return -1;
7a0ea589
LV		 1043}
1044#endif
17c29873
AD		 1045
1046#ifdef CONFIG_TI_SECURE_DEVICE
1047void board_fit_image_post_process(void **p_image, size_t *p_size)
1048{
1049 secure_boot_verify_image(p_image, p_size);
1050}
1b597ada
AD		 1051
1052void board_tee_image_process(ulong tee_image, size_t tee_size)
1053{
1054 secure_tee_install((u32)tee_image);
1055}
1056
1057U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
17c29873 1058#endif
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