[J-u-boot.git] / board / ti / beagle_x15 / board.c

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
 *
 * Author: Felipe Balbi <[email protected]>
 *
 * Based on board/ti/dra7xx/evm.c
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <usb.h>
#include <asm/omap_common.h>
#include <asm/emif.h>
#include <asm/arch/clock.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
#include <environment.h>

#include "mux_data.h"

#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

const struct omap_sysinfo sysinfo = {
	"Board: BeagleBoard x15\n"
};

static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
	.dmm_lisa_map_3 = 0x80740300,
	.is_ma_present  = 0x1
};

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
	*dmm_lisa_regs = &beagle_x15_lisa_regs;
}

static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
	.sdram_config_init	= 0x61851b32,
	.sdram_config		= 0x61851b32,
	.sdram_config2		= 0x00000000,
	.ref_ctrl		= 0x000040F1,
	.ref_ctrl_final		= 0x00001035,
	.sdram_tim1		= 0xceef266b,
	.sdram_tim2		= 0x328f7fda,
	.sdram_tim3		= 0x027f88a8,
	.read_idle_ctrl		= 0x00050000,
	.zq_config		= 0x0007190b,
	.temp_alert_config	= 0x00000000,
	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
	.emif_rd_wr_lvl_ctl	= 0x00000000,
	.emif_rd_wr_exec_thresh	= 0x00000305
};

/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
	0x10040100,
	0x00740074,
	0x00780078,
	0x007c007c,
	0x007b007b,
	0x00800080,
	0x00360036,
	0x00340034,
	0x00360036,
	0x00350035,
	0x00350035,

	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,

	0x00430043,
	0x003e003e,
	0x004a004a,
	0x00470047,
	0x00400040,

	0x00000000,
	0x00600020,
	0x40011080,
	0x08102040,

	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
};

static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
	.sdram_config_init	= 0x61851b32,
	.sdram_config		= 0x61851b32,
	.sdram_config2		= 0x00000000,
	.ref_ctrl		= 0x000040F1,
	.ref_ctrl_final		= 0x00001035,
	.sdram_tim1		= 0xceef266b,
	.sdram_tim2		= 0x328f7fda,
	.sdram_tim3		= 0x027f88a8,
	.read_idle_ctrl		= 0x00050000,
	.zq_config		= 0x0007190b,
	.temp_alert_config	= 0x00000000,
	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
	.emif_rd_wr_lvl_ctl	= 0x00000000,
	.emif_rd_wr_exec_thresh	= 0x00000305
};

static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
	0x10040100,
	0x00820082,
	0x008b008b,
	0x00800080,
	0x007e007e,
	0x00800080,
	0x00370037,
	0x00390039,
	0x00360036,
	0x00370037,
	0x00350035,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x01ff01ff,
	0x00540054,
	0x00540054,
	0x004e004e,
	0x004c004c,
	0x00400040,

	0x00000000,
	0x00600020,
	0x40011080,
	0x08102040,

	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x00400040,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
};

void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
	switch (emif_nr) {
	case 1:
		*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
		break;
	case 2:
		*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
		break;
	}
}

void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
	switch (emif_nr) {
	case 1:
		*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
		*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
		break;
	case 2:
		*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
		*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
		break;
	}
}

struct vcores_data beagle_x15_volts = {
	.mpu.value		= VDD_MPU_DRA752,
	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU_NOM,
	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
	.mpu.pmic		= &tps659038,

	.eve.value		= VDD_EVE_DRA752,
	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
	.eve.pmic		= &tps659038,

	.gpu.value		= VDD_GPU_DRA752,
	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_NOM,
	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
	.gpu.pmic		= &tps659038,

	.core.value		= VDD_CORE_DRA752,
	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.core.addr		= TPS659038_REG_ADDR_SMPS6,
	.core.pmic		= &tps659038,

	.iva.value		= VDD_IVA_DRA752,
	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA_NOM,
	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
	.iva.pmic		= &tps659038,
};

void hw_data_init(void)
{
	*prcm = &dra7xx_prcm;
	*dplls_data = &dra7xx_dplls;
	*omap_vcores = &beagle_x15_volts;
	*ctrl = &dra7xx_ctrl;
}

int board_init(void)
{
	gpmc_init();
	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);

	return 0;
}

int board_late_init(void)
{
	init_sata(0);
	/*
	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
	 * This is the POWERHOLD-in-Low behavior.
	 */
	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
	return 0;
}

void set_muxconf_regs_essential(void)
{
	do_set_mux32((*ctrl)->control_padconf_core_base,
		     early_padconf, ARRAY_SIZE(early_padconf));
}

#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
	__recalibrate_iodelay(core_padconf_array_essential,
			      ARRAY_SIZE(core_padconf_array_essential),
			      iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	if (getenv_yesno("boot_os") != 1)
		return 1;
#endif

	return 0;
}
#endif

#ifdef CONFIG_DRIVER_TI_CPSW

/* Delay value to add to calibrated value */
#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)

static void cpsw_control(int enabled)
{
	/* VTP can be added here */
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 1,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 2,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int ret;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	uint32_t ctrl_val;

	/* try reading mac address from efuse */
	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("eth1addr")) {
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("eth1addr", mac_addr);
	}

	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	ctrl_val |= 0x22;
	writel(ctrl_val, (*ctrl)->control_core_control_io1);

	ret = cpsw_register(&cpsw_data);
	if (ret < 0)
		printf("Error %d registering CPSW switch\n", ret);

	return ret;
}
#endif
Commit	Line	Data
1e4ad74b FB	1	/*
	2	* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
	3	*
	4	* Author: Felipe Balbi <[email protected]>
	5	*
	6	* Based on board/ti/dra7xx/evm.c
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <palmas.h>
	13	#include <sata.h>
	14	#include <usb.h>
	15	#include <asm/omap_common.h>
	16	#include <asm/emif.h>
	17	#include <asm/arch/clock.h>
f91e0c4c	18	#include <asm/arch/dra7xx_iodelay.h>
1e4ad74b FB	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/arch/mmc_host_def.h>
	21	#include <asm/arch/sata.h>
	22	#include <asm/arch/gpio.h>
	23	#include <environment.h>
	24
	25	#include "mux_data.h"
	26
	27	#ifdef CONFIG_DRIVER_TI_CPSW
	28	#include <cpsw.h>
	29	#endif
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	const struct omap_sysinfo sysinfo = {
	34	"Board: BeagleBoard x15\n"
	35	};
	36
	37	static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
	38	.dmm_lisa_map_3 = 0x80740300,
	39	.is_ma_present = 0x1
	40	};
	41
	42	void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	43	{
	44	*dmm_lisa_regs = &beagle_x15_lisa_regs;
	45	}
	46
	47	static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
	48	.sdram_config_init = 0x61851b32,
	49	.sdram_config = 0x61851b32,
	50	.sdram_config2 = 0x00000000,
802bb57a LV	51	.ref_ctrl = 0x000040F1,
802bb57a LV	52	.ref_ctrl_final = 0x00001035,
1e4ad74b FB	53	.sdram_tim1 = 0xceef266b,
	54	.sdram_tim2 = 0x328f7fda,
	55	.sdram_tim3 = 0x027f88a8,
ee4dc259	56	.read_idle_ctrl = 0x00050000,
1e4ad74b FB	57	.zq_config = 0x0007190b,
1e4ad74b FB	58	.temp_alert_config = 0x00000000,
496edffd LV	59	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
496edffd LV	60	.emif_ddr_phy_ctlr_1 = 0x0e24400b,
1e4ad74b FB	61	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	62	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
	63	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
	64	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
	65	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
	66	.emif_rd_wr_lvl_rmp_win = 0x00000000,
496edffd	67	.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
1e4ad74b FB	68	.emif_rd_wr_lvl_ctl = 0x00000000,
	69	.emif_rd_wr_exec_thresh = 0x00000305
	70	};
	71
6213db78	72	/* Ext phy ctrl regs 1-35 */
1e4ad74b	73	static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
6213db78 LV	74	0x10040100,
	75	0x00740074,
	76	0x00780078,
	77	0x007c007c,
	78	0x007b007b,
1e4ad74b FB	79	0x00800080,
	80	0x00360036,
	81	0x00340034,
	82	0x00360036,
	83	0x00350035,
	84	0x00350035,
	85
	86	0x01ff01ff,
	87	0x01ff01ff,
	88	0x01ff01ff,
	89	0x01ff01ff,
	90	0x01ff01ff,
	91
	92	0x00430043,
	93	0x003e003e,
	94	0x004a004a,
	95	0x00470047,
	96	0x00400040,
	97
	98	0x00000000,
	99	0x00600020,
6213db78	100	0x40011080,
1e4ad74b FB	101	0x08102040,
	102
	103	0x00400040,
	104	0x00400040,
	105	0x00400040,
	106	0x00400040,
496edffd LV	107	0x00400040,
	108	0x0,
	109	0x0,
	110	0x0,
	111	0x0,
	112	0x0
1e4ad74b FB	113	};
	114
	115	static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
	116	.sdram_config_init = 0x61851b32,
	117	.sdram_config = 0x61851b32,
	118	.sdram_config2 = 0x00000000,
802bb57a LV	119	.ref_ctrl = 0x000040F1,
802bb57a LV	120	.ref_ctrl_final = 0x00001035,
1e4ad74b FB	121	.sdram_tim1 = 0xceef266b,
	122	.sdram_tim2 = 0x328f7fda,
	123	.sdram_tim3 = 0x027f88a8,
ee4dc259	124	.read_idle_ctrl = 0x00050000,
1e4ad74b FB	125	.zq_config = 0x0007190b,
1e4ad74b FB	126	.temp_alert_config = 0x00000000,
496edffd LV	127	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
496edffd LV	128	.emif_ddr_phy_ctlr_1 = 0x0e24400b,
1e4ad74b FB	129	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	130	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
	131	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
	132	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
	133	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
	134	.emif_rd_wr_lvl_rmp_win = 0x00000000,
496edffd	135	.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
1e4ad74b FB	136	.emif_rd_wr_lvl_ctl = 0x00000000,
	137	.emif_rd_wr_exec_thresh = 0x00000305
	138	};
	139
	140	static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
6213db78 LV	141	0x10040100,
	142	0x00820082,
	143	0x008b008b,
	144	0x00800080,
	145	0x007e007e,
1e4ad74b FB	146	0x00800080,
	147	0x00370037,
	148	0x00390039,
	149	0x00360036,
	150	0x00370037,
	151	0x00350035,
	152	0x01ff01ff,
	153	0x01ff01ff,
	154	0x01ff01ff,
	155	0x01ff01ff,
	156	0x01ff01ff,
	157	0x00540054,
	158	0x00540054,
	159	0x004e004e,
	160	0x004c004c,
	161	0x00400040,
	162
	163	0x00000000,
	164	0x00600020,
6213db78	165	0x40011080,
1e4ad74b FB	166	0x08102040,
	167
	168	0x00400040,
	169	0x00400040,
	170	0x00400040,
	171	0x00400040,
496edffd LV	172	0x00400040,
	173	0x0,
	174	0x0,
	175	0x0,
	176	0x0,
	177	0x0
1e4ad74b FB	178	};
	179
	180	void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	181	{
	182	switch (emif_nr) {
	183	case 1:
	184	*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
	185	break;
	186	case 2:
	187	*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
	188	break;
	189	}
	190	}
	191
	192	void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 *regs, u32 size)
	193	{
	194	switch (emif_nr) {
	195	case 1:
	196	*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
	197	*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
	198	break;
	199	case 2:
	200	*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
	201	*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
	202	break;
	203	}
	204	}
	205
	206	struct vcores_data beagle_x15_volts = {
	207	.mpu.value = VDD_MPU_DRA752,
	208	.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
	209	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
	210	.mpu.addr = TPS659038_REG_ADDR_SMPS12,
	211	.mpu.pmic = &tps659038,
	212
	213	.eve.value = VDD_EVE_DRA752,
	214	.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
	215	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
	216	.eve.addr = TPS659038_REG_ADDR_SMPS45,
	217	.eve.pmic = &tps659038,
	218
	219	.gpu.value = VDD_GPU_DRA752,
	220	.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
	221	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
	222	.gpu.addr = TPS659038_REG_ADDR_SMPS45,
	223	.gpu.pmic = &tps659038,
	224
	225	.core.value = VDD_CORE_DRA752,
	226	.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
	227	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
	228	.core.addr = TPS659038_REG_ADDR_SMPS6,
	229	.core.pmic = &tps659038,
	230
	231	.iva.value = VDD_IVA_DRA752,
	232	.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
	233	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
	234	.iva.addr = TPS659038_REG_ADDR_SMPS45,
	235	.iva.pmic = &tps659038,
	236	};
	237
	238	void hw_data_init(void)
	239	{
	240	*prcm = &dra7xx_prcm;
	241	*dplls_data = &dra7xx_dplls;
242	*omap_vcores = &beagle_x15_volts;
243	*ctrl = &dra7xx_ctrl;
244	}
245
246	int board_init(void)
247	{
248	gpmc_init();
249	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
250
251	return 0;
252	}
253
254	int board_late_init(void)
255	{
256	init_sata(0);
257	/*
258	* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
259	* This is the POWERHOLD-in-Low behavior.
260	*/
261	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
262	return 0;
263	}
264
1e4ad74b FB	265	void set_muxconf_regs_essential(void)
	266	{
	267	do_set_mux32((*ctrl)->control_padconf_core_base,
f91e0c4c	268	early_padconf, ARRAY_SIZE(early_padconf));
1e4ad74b FB	269	}
1e4ad74b FB	270
f91e0c4c LV	271	#ifdef CONFIG_IODELAY_RECALIBRATION
	272	void recalibrate_iodelay(void)
	273	{
	274	__recalibrate_iodelay(core_padconf_array_essential,
	275	ARRAY_SIZE(core_padconf_array_essential),
	276	iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
	277	}
	278	#endif
	279
1e4ad74b FB	280	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	281	int board_mmc_init(bd_t *bis)
	282	{
	283	omap_mmc_init(0, 0, 0, -1, -1);
	284	omap_mmc_init(1, 0, 0, -1, -1);
	285	return 0;
	286	}
	287	#endif
	288
	289	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
	290	int spl_start_uboot(void)
	291	{
	292	/* break into full u-boot on 'c' */
	293	if (serial_tstc() && serial_getc() == 'c')
	294	return 1;
	295
	296	#ifdef CONFIG_SPL_ENV_SUPPORT
	297	env_init();
	298	env_relocate_spec();
	299	if (getenv_yesno("boot_os") != 1)
	300	return 1;
	301	#endif
	302
	303	return 0;
	304	}
	305	#endif
	306
	307	#ifdef CONFIG_DRIVER_TI_CPSW
	308
	309	/* Delay value to add to calibrated value */
	310	#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
	311	#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
	312	#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
	313	#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
	314	#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
	315	#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
	316	#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
	317	#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
	318	#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
	319	#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
	320
	321	static void cpsw_control(int enabled)
	322	{
	323	/* VTP can be added here */
	324	}
	325
	326	static struct cpsw_slave_data cpsw_slaves[] = {
	327	{
	328	.slave_reg_ofs = 0x208,
	329	.sliver_reg_ofs = 0xd80,
	330	.phy_addr = 1,
	331	},
	332	{
	333	.slave_reg_ofs = 0x308,
	334	.sliver_reg_ofs = 0xdc0,
	335	.phy_addr = 2,
	336	},
	337	};
	338
	339	static struct cpsw_platform_data cpsw_data = {
	340	.mdio_base = CPSW_MDIO_BASE,
	341	.cpsw_base = CPSW_BASE,
	342	.mdio_div = 0xff,
	343	.channels = 8,
344	.cpdma_reg_ofs = 0x800,
345	.slaves = 1,
346	.slave_data = cpsw_slaves,
347	.ale_reg_ofs = 0xd00,
348	.ale_entries = 1024,
349	.host_port_reg_ofs = 0x108,
350	.hw_stats_reg_ofs = 0x900,
351	.bd_ram_ofs = 0x2000,
352	.mac_control = (1 << 5),
353	.control = cpsw_control,
354	.host_port_num = 0,
355	.version = CPSW_CTRL_VERSION_2,
356	};
357
358	int board_eth_init(bd_t *bis)
359	{
360	int ret;
361	uint8_t mac_addr[6];
362	uint32_t mac_hi, mac_lo;
363	uint32_t ctrl_val;
364
365	/* try reading mac address from efuse */
366	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
367	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
368	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
369	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
370	mac_addr[2] = mac_hi & 0xFF;
371	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
372	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
373	mac_addr[5] = mac_lo & 0xFF;
374
375	if (!getenv("ethaddr")) {
376	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
377
0adb5b76	378	if (is_valid_ethaddr(mac_addr))
1e4ad74b FB	379	eth_setenv_enetaddr("ethaddr", mac_addr);
	380	}
	381
	382	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	383	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	384	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	385	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	386	mac_addr[2] = mac_hi & 0xFF;
	387	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	388	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	389	mac_addr[5] = mac_lo & 0xFF;
	390
	391	if (!getenv("eth1addr")) {
0adb5b76	392	if (is_valid_ethaddr(mac_addr))
1e4ad74b FB	393	eth_setenv_enetaddr("eth1addr", mac_addr);
	394	}
	395
	396	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	397	ctrl_val \|= 0x22;
	398	writel(ctrl_val, (*ctrl)->control_core_control_io1);
	399
	400	ret = cpsw_register(&cpsw_data);
	401	if (ret < 0)
	402	printf("Error %d registering CPSW switch\n", ret);
	403
	404	return ret;
	405	}
	406	#endif