[J-u-boot.git] / include / configs / pm9263.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuration settings for the RONETIX PM9263 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */
#include <asm/hardware.h>

/* ARM asynchronous clock */

#define MASTER_PLL_DIV		6
#define MASTER_PLL_MUL		65
#define MAIN_PLL_DIV		2	/* 2 or 4 */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */

#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"

#define CONFIG_MACH_TYPE	MACH_TYPE_PM9263

/* clocks */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_PLLXR_OUT(3) |				\
		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
		 (2 << 28) |		/* PLL Clock Frequency Range */	\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_MCKR_CSS_SLOW |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_MCKR_CSS_PLLA |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL			\
		(AT91_PMC_MCKR_CSS_SLOW |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL			\
		(AT91_PMC_MCKR_CSS_PLLA |		\
		 AT91_PMC_MCKR_PRES_1 |		\
		 AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_2 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |					\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#define CONFIG_USER_LOWLEVEL_INIT	1

/*
 * Hardware drivers
 */
/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1

#define CONFIG_LCD_IN_PSRAM		1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1

/* SDRAM */
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */

/* NOR flash, if populated */
#define PHYS_FLASH_1			0x10000000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)

#endif

#define CONFIG_JFFS2_NAND		1
#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/

/* PSRAM */
#define	PHYS_PSRAM			0x70000000
#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
/* Slave EBI1, PSRAM connected */
#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW			1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_USE_FLASH	1
#undef CONFIG_SYS_USE_DATAFLASH
#undef CONFIG_SYS_USE_NANDFLASH

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"

#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"

#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11

#define CONFIG_BOOTCOMMAND		"run flashboot"
#define CONFIG_ROOTPATH			"/ronetix/rootfs"

#define CONFIG_CON_ROT			"fbcon=rotate:3 "

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		CONFIG_CON_ROT					\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""

#else
#error "Undefined memory device"
#endif

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
				GENERATED_GBL_DATA_SIZE)

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f0a2c7b4 II	2	/*
f0a2c7b4 II	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <[email protected]>
f0a2c7b4 II	5	* Lead Tech Design <www.leadtechdesign.com>
	6	* Ilko Iliev <www.ronetix.at>
	7	*
4bf3a3fc	8	* Configuration settings for the RONETIX PM9263 board.
f0a2c7b4 II	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
684a567a AD	14	/*
	15	* SoC must be defined first, before hardware.h is included.
	16	* In this case SoC is defined in boards.cfg.
	17	*/
	18	#include <asm/hardware.h>
	19
f0a2c7b4	20	/* ARM asynchronous clock */
f0a2c7b4	21
01550a2b JCPV	22	#define MASTER_PLL_DIV 6
01550a2b JCPV	23	#define MASTER_PLL_MUL 65
f0a2c7b4	24	#define MAIN_PLL_DIV 2 /* 2 or 4 */
7c966a8b	25	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
684a567a	26	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
f0a2c7b4	27
684a567a	28	#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
f0a2c7b4	29
a3e09cc2 AD	30	#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
a3e09cc2 AD	31
f0a2c7b4	32	/* clocks */
01550a2b	33	#define CONFIG_SYS_MOR_VAL \
20d98c2c	34	(AT91_PMC_MOR_MOSCEN \| \
01550a2b JCPV	35	(255 << 8)) /* Main Oscillator Start-up Time */
01550a2b JCPV	36	#define CONFIG_SYS_PLLAR_VAL \
20d98c2c AD	37	(AT91_PMC_PLLAR_29 \| /* Bit 29 must be 1 when prog */ \
	38	AT91_PMC_PLLXR_OUT(3) \| \
	39	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \| /* PLL Counter */\
01550a2b JCPV	40	(2 << 28) \| /* PLL Clock Frequency Range */ \
01550a2b JCPV	41	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
f0a2c7b4 II	42
	43	#if (MAIN_PLL_DIV == 2)
	44	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	45	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	46	(AT91_PMC_MCKR_CSS_SLOW \| \
	47	AT91_PMC_MCKR_PRES_1 \| \
	48	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4	49	/* PCK/2 = MCK Master Clock from PLLA */
01550a2b	50	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	51	(AT91_PMC_MCKR_CSS_PLLA \| \
	52	AT91_PMC_MCKR_PRES_1 \| \
	53	AT91_PMC_MCKR_MDIV_2)
f0a2c7b4 II	54	#else
f0a2c7b4 II	55	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	56	#define CONFIG_SYS_MCKR1_VAL \
20d98c2c AD	57	(AT91_PMC_MCKR_CSS_SLOW \| \
	58	AT91_PMC_MCKR_PRES_1 \| \
	59	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4	60	/* PCK/4 = MCK Master Clock from PLLA */
01550a2b	61	#define CONFIG_SYS_MCKR2_VAL \
20d98c2c AD	62	(AT91_PMC_MCKR_CSS_PLLA \| \
	63	AT91_PMC_MCKR_PRES_1 \| \
	64	AT91_PMC_MCKR_MDIV_4)
f0a2c7b4 II	65	#endif
	66	/* define PDC[31:16] as DATA[31:16] */
	67	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	68	/* no pull-up for D[31:16] */
	69	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	70	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
01550a2b	71	#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
20d98c2c AD	72	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
20d98c2c AD	73	AT91_MATRIX_CSA_EBI_CS1A)
f0a2c7b4 II	74
	75	/* SDRAM */
	76	/* SDRAMC_MR Mode register */
	77	#define CONFIG_SYS_SDRC_MR_VAL1 0
	78	/* SDRAMC_TR - Refresh Timer register */
01550a2b JCPV	79	#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
	80	/* SDRAMC_CR - Configuration register*/
	81	#define CONFIG_SYS_SDRC_CR_VAL \
	82	(AT91_SDRAMC_NC_9 \| \
	83	AT91_SDRAMC_NR_13 \| \
	84	AT91_SDRAMC_NB_4 \| \
	85	AT91_SDRAMC_CAS_2 \| \
	86	AT91_SDRAMC_DBW_32 \| \
	87	(2 << 8) \| /* tWR - Write Recovery Delay */ \
	88	(7 << 12) \| /* tRC - Row Cycle Delay */ \
	89	(2 << 16) \| /* tRP - Row Precharge Delay */ \
	90	(2 << 20) \| /* tRCD - Row to Column Delay */ \
	91	(5 << 24) \| /* tRAS - Active to Precharge Delay */ \
	92	(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
	93
f0a2c7b4	94	/* Memory Device Register -> SDRAM */
01550a2b JCPV	95	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
01550a2b JCPV	96	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
f0a2c7b4	97	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
01550a2b	98	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
f0a2c7b4 II	99	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	100	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	101	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	102	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	103	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	104	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	105	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	106	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
01550a2b	107	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
f0a2c7b4	108	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
01550a2b	109	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
f0a2c7b4 II	110	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	111	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	112	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	113
	114	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
01550a2b	115	#define CONFIG_SYS_SMC0_SETUP0_VAL \
20d98c2c AD	116	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
20d98c2c AD	117	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
01550a2b	118	#define CONFIG_SYS_SMC0_PULSE0_VAL \
20d98c2c AD	119	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
20d98c2c AD	120	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
01550a2b	121	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
20d98c2c	122	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
01550a2b	123	#define CONFIG_SYS_SMC0_MODE0_VAL \
20d98c2c AD	124	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	125	AT91_SMC_MODE_DBW_16 \| \
	126	AT91_SMC_MODE_TDF \| \
	127	AT91_SMC_MODE_TDF_CYCLE(6))
f0a2c7b4	128
01550a2b JCPV	129	/* user reset enable */
	130	#define CONFIG_SYS_RSTC_RMR_VAL \
	131	(AT91_RSTC_KEY \| \
20d98c2c AD	132	AT91_RSTC_CR_PROCRST \| \
	133	AT91_RSTC_MR_ERSTL(1) \| \
	134	AT91_RSTC_MR_ERSTL(2))
f0a2c7b4	135
01550a2b JCPV	136	/* Disable Watchdog */
01550a2b JCPV	137	#define CONFIG_SYS_WDTC_WDMR_VAL \
20d98c2c AD	138	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	139	AT91_WDT_MR_WDV(0xfff) \| \
	140	AT91_WDT_MR_WDDIS \| \
	141	AT91_WDT_MR_WDD(0xfff))
f0a2c7b4	142
f0a2c7b4 II	143	#define CONFIG_USER_LOWLEVEL_INIT 1
	144
	145	/*
	146	* Hardware drivers
	147	*/
f0a2c7b4	148	/* LCD */
f0a2c7b4 II	149	#define LCD_BPP LCD_COLOR8
	150	#define CONFIG_LCD_LOGO 1
	151	#undef LCD_TEST_PATTERN
	152	#define CONFIG_LCD_INFO 1
	153	#define CONFIG_LCD_INFO_BELOW_LOGO 1
f0a2c7b4 II	154	#define CONFIG_ATMEL_LCD 1
f0a2c7b4 II	155	#define CONFIG_ATMEL_LCD_BGR555 1
f0a2c7b4 II	156
	157	#define CONFIG_LCD_IN_PSRAM 1
	158
f0a2c7b4 II	159	/*
	160	* BOOTP options
	161	*/
	162	#define CONFIG_BOOTP_BOOTFILESIZE 1
f0a2c7b4	163
f0a2c7b4	164	/* SDRAM */
f0a2c7b4 II	165	#define PHYS_SDRAM 0x20000000
	166	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	167
f0a2c7b4	168	/* NOR flash, if populated */
f0a2c7b4 II	169	#define PHYS_FLASH_1 0x10000000
	170	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	171	#define CONFIG_SYS_MAX_FLASH_SECT 256
	172	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	173
	174	/* NAND flash */
	175	#ifdef CONFIG_CMD_NAND
f0a2c7b4 II	176	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	177	#define CONFIG_SYS_NAND_BASE 0x40000000
	178	#define CONFIG_SYS_NAND_DBW_8 1
	179	/* our ALE is AD21 */
	180	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	181	/* our CLE is AD22 */
	182	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
ac45bb16 AB	183	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
ac45bb16 AB	184	#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
2eb99ca8	185
f0a2c7b4 II	186	#endif
f0a2c7b4 II	187
f0a2c7b4 II	188	#define CONFIG_JFFS2_NAND 1
	189	#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
	190	#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
	191	#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
	192
	193	/* PSRAM */
	194	#define PHYS_PSRAM 0x70000000
	195	#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
20d98c2c AD	196	/* Slave EBI1, PSRAM connected */
	197	#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY \| \
	198	AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) \| \
	199	AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED \| \
	200	AT91_MATRIX_SCFG_SLOT_CYCLE(255))
f0a2c7b4	201
f0a2c7b4 II	202	/* USB */
f0a2c7b4 II	203	#define CONFIG_USB_ATMEL
dcd2f1a0	204	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
f0a2c7b4	205	#define CONFIG_USB_OHCI_NEW 1
f0a2c7b4 II	206	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	207	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
	208	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	209	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
f0a2c7b4	210
f0a2c7b4 II	211	#define CONFIG_SYS_USE_FLASH 1
	212	#undef CONFIG_SYS_USE_DATAFLASH
	213	#undef CONFIG_SYS_USE_NANDFLASH
	214
	215	#ifdef CONFIG_SYS_USE_DATAFLASH
	216
	217	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
0dfe3ffe WY	218	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	219	"sf read 0x22000000 0x84000 0x294000; " \
	220	"bootm 0x22000000"
f0a2c7b4 II	221
	222	#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
	223
	224	/* bootstrap + u-boot + env + linux in nandflash */
f0a2c7b4	225	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
f0a2c7b4 II	226
f0a2c7b4 II	227	#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
f0a2c7b4 II	228	/* JFFS Partition offset set */
	229	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	230	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	231
	232	/* 512k reserved for u-boot */
	233	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
	234
	235	#define CONFIG_BOOTCOMMAND "run flashboot"
8b3637c6	236	#define CONFIG_ROOTPATH "/ronetix/rootfs"
f0a2c7b4 II	237
f0a2c7b4 II	238	#define CONFIG_CON_ROT "fbcon=rotate:3 "
f0a2c7b4	239
f0a2c7b4	240	#define CONFIG_EXTRA_ENV_SETTINGS \
43ede0bc TR	241	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	242	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
f0a2c7b4 II	243	"partition=nand0,0\0" \
	244	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	245	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	246	CONFIG_CON_ROT \
	247	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	248	"addip=setenv bootargs $(bootargs) " \
	249	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	250	":$(hostname):eth0:off\0" \
	251	"ramboot=tftpboot 0x22000000 vmImage;" \
	252	"run ramargs;run addip;bootm 22000000\0" \
	253	"nfsboot=tftpboot 0x22000000 vmImage;" \
	254	"run nfsargs;run addip;bootm 22000000\0" \
	255	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	256	""
	257
	258	#else
	259	#error "Undefined memory device"
	260	#endif
	261
9a2a05a4	262	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
0dfe3ffe	263	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
9a2a05a4 AD	264	GENERATED_GBL_DATA_SIZE)
9a2a05a4 AD	265
f0a2c7b4	266	#endif