[J-u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# ifndef CONFIG_SPL_BUILD
#  define CONFIG_HW_WATCHDOG
#  define CONFIG_XILINX_TB_WATCHDOG
# endif
#endif

#define CONFIG_SYS_MALLOC_LEN	0xC0000

/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_SPI			1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_MFSL

#if defined(FLASH)
# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	0

#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"
#endif

#define CONFIG_CMDLINE_EDITING

/* Enable flat device tree support */
#define CONFIG_LMB		1

#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_MICREL_KSZ9021
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#endif

/* for booting directly linux */

#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_FDT_SIZE		(16<<10)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x100000

# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 CONFIG_SYS_MALLOC_F_LEN - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <[email protected]>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
bcec8f49	17	/* linear and spi flash memory */
1fe7e8fa SL	18	#ifdef XILINX_FLASH_START
1fe7e8fa SL	19	#define FLASH
bcec8f49	20	#undef SPIFLASH
1fe7e8fa SL	21	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	22	#else
bcec8f49	23	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	24	#undef FLASH
bcec8f49 SL	25	#define SPIFLASH
	26	#undef RAMENV /* hold environment in flash */
	27	#else
	28	#undef FLASH
	29	#undef SPIFLASH
1fe7e8fa SL	30	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	31	#endif
bcec8f49	32	#endif
1fe7e8fa	33
76316a31	34	/* uart */
67659e2e MS	35	/* The following table includes the supported baudrates */
	36	# define CONFIG_SYS_BAUDRATE_TABLE \
	37	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	38
76316a31	39	/* setting reset address */
14d0a02a	40	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31 MS	41
76316a31 MS	42	/* gpio */
4c6a6f02	43	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	44	# define CONFIG_XILINX_GPIO
4aecfb16	45	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	46	#endif
76316a31	47
0f21f98d MS	48	/* watchdog */
	49	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	50	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	51	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
b5e9b9a9 MS	52	# ifndef CONFIG_SPL_BUILD
	53	# define CONFIG_HW_WATCHDOG
	54	# define CONFIG_XILINX_TB_WATCHDOG
	55	# endif
0f21f98d MS	56	#endif
0f21f98d MS	57
e945f6dc MS	58	#define CONFIG_SYS_MALLOC_LEN 0xC0000
	59
	60	/* Stack location before relocation */
4fcd0b33 MS	61	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
4fcd0b33 MS	62	CONFIG_SYS_MALLOC_F_LEN)
76316a31	63
8f371b18 SL	64	/*
	65	* CFI flash memory layout - Example
	66	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	67	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	68	*
	69	* SECT_SIZE = 0x20000; 128kB is one sector
	70	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	71	*
	72	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	73	* FREE 256kB
	74	* 0x2204_0000 CONFIG_ENV_ADDR
	75	* ENV_AREA 128kB
	76	* 0x2206_0000
	77	* FREE
	78	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	79	*
	80	*/
	81
76316a31	82	#ifdef FLASH
4aecfb16 MS	83	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	84	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	85	# define CONFIG_SYS_FLASH_CFI 1
	86	# define CONFIG_FLASH_CFI_DRIVER 1
	87	/* ?empty sector */
	88	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	89	/* max number of memory banks */
	90	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	91	/* max number of sectors on one chip */
	92	# define CONFIG_SYS_MAX_FLASH_SECT 512
	93	/* hardware flash protection */
	94	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	95	/* use buffered writes (20x faster) */
22ff7f4d MS	96	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16	97	# ifdef RAMENV
4aecfb16 MS	98	# define CONFIG_ENV_SIZE 0x1000
	99	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	100
bcec8f49	101	# else /* FLASH && !RAMENV */
4aecfb16 MS	102	/* 128K(one sector) for env */
	103	# define CONFIG_ENV_SECT_SIZE 0x20000
	104	# define CONFIG_ENV_ADDR \
	105	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	106	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	107	# endif /* FLASH && !RAMBOOT */
76316a31	108	#else /* !FLASH */
bcec8f49 SL	109
bcec8f49 SL	110	#ifdef SPIFLASH
bcec8f49	111	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
bcec8f49	112	# define CONFIG_SPI 1
bcec8f49 SL	113	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	114	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	115	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	116
	117	# ifdef RAMENV
bcec8f49 SL	118	# define CONFIG_ENV_SIZE 0x1000
	119	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	120
	121	# else /* SPIFLASH && !RAMENV */
bcec8f49 SL	122	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	123	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	124	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	125	/* 128K(two sectors) for env */
	126	# define CONFIG_ENV_SECT_SIZE 0x10000
	127	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	128	/* Warning: adjust the offset in respect of other flash content and size */
	129	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	130	# endif /* SPIFLASH && !RAMBOOT */
	131	#else /* !SPIFLASH */
	132
4aecfb16	133	/* ENV in RAM */
4aecfb16 MS	134	# define CONFIG_ENV_SIZE 0x1000
4aecfb16 MS	135	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	136	#endif /* !SPIFLASH */
76316a31 MS	137	#endif /* !FLASH */
76316a31 MS	138
e9b737de	139	#if defined(XILINX_USE_ICACHE)
4aecfb16	140	# define CONFIG_ICACHE
e9b737de	141	#else
4aecfb16	142	# undef CONFIG_ICACHE
e9b737de MS	143	#endif
	144
	145	#if defined(XILINX_USE_DCACHE)
4aecfb16	146	# define CONFIG_DCACHE
e9b737de	147	#else
4aecfb16	148	# undef CONFIG_DCACHE
e9b737de MS	149	#endif
e9b737de MS	150
5811830f MS	151	#ifndef XILINX_DCACHE_BYTE_SIZE
	152	#define XILINX_DCACHE_BYTE_SIZE 32768
	153	#endif
	154
079a136c JL	155	/*
	156	* BOOTP options
	157	*/
	158	#define CONFIG_BOOTP_BOOTFILESIZE
	159	#define CONFIG_BOOTP_BOOTPATH
	160	#define CONFIG_BOOTP_GATEWAY
	161	#define CONFIG_BOOTP_HOSTNAME
76316a31	162
5dc11a51 JL	163	/*
	164	* Command line configuration.
	165	*/
5dc11a51	166	#define CONFIG_CMD_MFSL
4d49b280	167
5dc11a51	168	#if defined(FLASH)
bcec8f49	169	# if !defined(RAMENV)
bcec8f49 SL	170	# define CONFIG_CMD_SAVES
	171	# endif
	172
	173	#else
	174	#if defined(SPIFLASH)
bcec8f49	175
4aecfb16	176	# if !defined(RAMENV)
4aecfb16 MS	177	# define CONFIG_CMD_SAVES
4aecfb16 MS	178	# endif
5dc11a51	179	#endif
bcec8f49	180	#endif
76316a31	181
5dc11a51	182	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	183	# define CONFIG_MTD_PARTITIONS
	184	#endif
	185
7cfb13a7 SL	186	#if defined(CONFIG_CMD_UBI)
7cfb13a7 SL	187	# define CONFIG_MTD_PARTITIONS
7cfb13a7 SL	188	#endif
	189
	190	#if defined(CONFIG_MTD_PARTITIONS)
	191	/* MTD partitions */
942556a9 SR	192	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	193	#define CONFIG_FLASH_CFI_MTD
c82a541d	194	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	195
144876a3 MS	196	/* default mtd partition table */
c82a541d	197	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	198	"256k(env),3m(kernel),1m(romfs),"\
	199	"1m(cramfs),-(jffs2)"
	200	#endif
	201
4aecfb16 MS	202	/* size of console buffer */
	203	#define CONFIG_SYS_CBSIZE 512
	204	/* print buffer size */
	205	#define CONFIG_SYS_PBSIZE \
	206	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	207	/* max number of command args */
	208	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	209	#define CONFIG_SYS_LONGHELP
4aecfb16	210	/* default load address */
44a3a91c	211	#define CONFIG_SYS_LOAD_ADDR 0
76316a31	212
76316a31	213	#define CONFIG_BOOTARGS "root=romfs"
330e5545	214	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	215	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31 MS	216
76316a31 MS	217	/* architecture dependent code */
6d0f6bcf	218	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	219
0900bee9	220	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	221
2902a9b7	222	#ifndef CONFIG_EXTRA_ENV_SETTINGS
4aecfb16	223	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	224	"nor0=flash-0\0"\
c82a541d SL	225	"mtdparts=mtdparts=flash-0:"\
144876a3	226	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	227	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	228	"nc=setenv stdout nc;"\
	229	"setenv stdin nc\0" \
	230	"serial=setenv stdout serial;"\
	231	"setenv stdin serial\0"
2902a9b7	232	#endif
144876a3	233
188dc16b	234	#define CONFIG_CMDLINE_EDITING
188dc16b	235
37e892d9 MS	236	/* Enable flat device tree support */
37e892d9 MS	237	#define CONFIG_LMB 1
37e892d9	238
4632b1ea	239	#if defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff	240	# define CONFIG_MII 1
f5e5e1ff SL	241	# define CONFIG_PHY_GIGE 1
f5e5e1ff SL	242	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
f5e5e1ff SL	243	# define CONFIG_PHY_ATHEROS 1
	244	# define CONFIG_PHY_BROADCOM 1
	245	# define CONFIG_PHY_DAVICOM 1
	246	# define CONFIG_PHY_LXT 1
	247	# define CONFIG_PHY_MARVELL 1
	248	# define CONFIG_PHY_MICREL 1
2014a3de	249	# define CONFIG_PHY_MICREL_KSZ9021
f5e5e1ff SL	250	# define CONFIG_PHY_NATSEMI 1
	251	# define CONFIG_PHY_REALTEK 1
	252	# define CONFIG_PHY_VITESSE 1
	253	#else
	254	# undef CONFIG_MII
f5e5e1ff SL	255	#endif
f5e5e1ff SL	256
9d242745	257	/* SPL part */
9d242745 MS	258	#define CONFIG_CMD_SPL
9d242745 MS	259	#define CONFIG_SPL_FRAMEWORK
9d242745 MS	260
	261	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	262
4dd09742	263	#ifdef CONFIG_SYS_FLASH_BASE
4dd09742 MS	264	# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
4dd09742 MS	265	#endif
9d242745 MS	266
9d242745 MS	267	/* for booting directly linux */
9d242745	268
9d242745 MS	269	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
9d242745 MS	270	0x40000)
5aa79f26	271	#define CONFIG_SYS_FDT_SIZE (16<<10)
9d242745 MS	272	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	273	0x1000000)
	274
	275	/* SP location before relocation, must use scratch RAM */
	276	/* BRAM start */
	277	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	278	/* BRAM size - will be generated */
ca7d2266	279	#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
9d242745	280
ca7d2266 MS	281	# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	282	CONFIG_SYS_INIT_RAM_SIZE - \
	283	CONFIG_SYS_MALLOC_F_LEN)
9d242745 MS	284
	285	/* Just for sure that there is a space for stack */
	286	#define CONFIG_SPL_STACK_SIZE 0x100
	287
9d242745 MS	288	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	289
	290	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	291	CONFIG_SYS_INIT_RAM_ADDR - \
ca7d2266	292	CONFIG_SYS_MALLOC_F_LEN - \
9d242745 MS	293	CONFIG_SPL_STACK_SIZE)
9d242745 MS	294
76316a31	295	#endif /* __CONFIG_H */