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1 | /* |
2 | * cm_t43.h | |
3 | * | |
4 | * Copyright (C) 2015 Compulab, Ltd. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_CM_T43_H | |
10 | #define __CONFIG_CM_T43_H | |
11 | ||
12 | #define CONFIG_AM43XX | |
13 | #define CONFIG_CM_T43 | |
14 | #define CONFIG_ARCH_CPU_INIT | |
15 | #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ | |
16 | #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ | |
17 | ||
18 | #include <asm/arch/omap.h> | |
19 | ||
20 | /* Serial support */ | |
21 | #define CONFIG_OMAP_SERIAL | |
22 | #define CONFIG_DM_SERIAL | |
23 | #define CONFIG_SYS_NS16550 | |
24 | #define CONFIG_SYS_NS16550_SERIAL | |
25 | #define CONFIG_SYS_NS16550_CLK 48000000 | |
26 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 | |
27 | ||
28 | /* NAND support */ | |
29 | #define CONFIG_NAND | |
30 | #define CONFIG_NAND_OMAP_ELM | |
31 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
32 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
33 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
34 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
35 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
36 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
37 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
38 | #define CONFIG_SYS_NAND_ECCBYTES 14 | |
39 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW | |
40 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ | |
41 | CONFIG_SYS_NAND_PAGE_SIZE) | |
42 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
43 | 10, 11, 12, 13, 14, 15, 16, 17, \ | |
44 | 18, 19, 20, 21, 22, 23, 24, 25, \ | |
45 | 26, 27, 28, 29, 30, 31, 32, 33, \ | |
46 | 34, 35, 36, 37, 38, 39, 40, 41, \ | |
47 | 42, 43, 44, 45, 46, 47, 48, 49, \ | |
48 | 50, 51, 52, 53, 54, 55, 56, 57, } | |
49 | ||
50 | /* CPSW Ethernet support */ | |
51 | #define CONFIG_DRIVER_TI_CPSW | |
52 | #define CONFIG_MII | |
53 | #define CONFIG_BOOTP_DEFAULT | |
54 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
55 | #define CONFIG_BOOTP_GATEWAY | |
56 | #define CONFIG_NET_MULTI | |
57 | #define CONFIG_PHY_GIGE | |
58 | #define CONFIG_PHY_ATHEROS | |
59 | #define CONFIG_PHYLIB | |
60 | #define CONFIG_SYS_RX_ETH_BUFFER 64 | |
61 | ||
62 | /* USB support */ | |
63 | #define CONFIG_USB_HOST | |
64 | #define CONFIG_USB_XHCI | |
65 | #define CONFIG_USB_XHCI_OMAP | |
66 | #define CONFIG_USB_XHCI_DWC3 | |
67 | #define CONFIG_USB_STORAGE | |
68 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
69 | #define CONFIG_OMAP_USB_PHY | |
70 | #define CONFIG_AM437X_USB2PHY2_HOST | |
71 | ||
72 | /* SPI Flash support */ | |
73 | #define CONFIG_SPI_FLASH | |
74 | #define CONFIG_SPI_FLASH_MACRONIX | |
75 | #define CONFIG_SPI_FLASH_ATMEL | |
76 | #define CONFIG_SPI_FLASH_EON | |
77 | #define CONFIG_SPI_FLASH_GIGADEVICE | |
78 | #define CONFIG_SPI_FLASH_SPANSION | |
79 | #define CONFIG_SPI_FLASH_STMICRO | |
80 | #define CONFIG_SPI_FLASH_SST | |
81 | #define CONFIG_SPI_FLASH_WINBOND | |
82 | #define CONFIG_TI_SPI_MMAP | |
83 | #define CONFIG_SPI_FLASH_BAR | |
84 | #define CONFIG_SF_DEFAULT_SPEED 48000000 | |
85 | #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 | |
86 | ||
87 | /* Power */ | |
88 | #define CONFIG_POWER | |
89 | #define CONFIG_POWER_I2C | |
90 | #define CONFIG_POWER_TPS65218 | |
91 | ||
92 | /* Enabling L2 Cache */ | |
93 | #define CONFIG_SYS_L2_PL310 | |
94 | #define CONFIG_SYS_PL310_BASE 0x48242000 | |
95 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
96 | ||
97 | /* | |
98 | * Since SPL did pll and ddr initialization for us, | |
99 | * we don't need to do it twice. | |
100 | */ | |
101 | #if !defined(CONFIG_SPL_BUILD) | |
102 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
103 | #endif | |
104 | ||
105 | #define CONFIG_HSMMC2_8BIT | |
106 | ||
107 | #include <configs/ti_armv7_omap.h> | |
108 | #undef CONFIG_SPL_OS_BOOT | |
109 | #undef CONFIG_SPL_GPIO_SUPPORT | |
110 | #undef CONFIG_SPL_NAND_SUPPORT | |
111 | #undef CONFIG_SPL_BOARD_INIT | |
112 | #undef CONFIG_BOOTDELAY | |
113 | #include <config_distro_defaults.h> | |
114 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
115 | #undef CONFIG_CMD_IMLS | |
116 | ||
117 | #define CONFIG_ENV_SIZE (16 * 1024) | |
118 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
119 | ||
120 | #define V_OSCK 24000000 /* Clock output from T2 */ | |
121 | #define V_SCLK (V_OSCK) | |
122 | ||
123 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
124 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
125 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
126 | #define CONFIG_ENV_SPI_MAX_HZ 48000000 | |
127 | ||
128 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
129 | ||
130 | /* Enhance our eMMC support / experience. */ | |
131 | #define CONFIG_CMD_GPT | |
132 | #define CONFIG_EFI_PARTITION | |
133 | ||
134 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
135 | "loadaddr=0x80200000\0" \ | |
136 | "fdtaddr=0x81200000\0" \ | |
137 | "bootm_size=0x8000000\0" \ | |
138 | "autoload=no\0" \ | |
139 | "console=ttyO0,115200n8\0" \ | |
140 | "fdtfile=am437x-sb-som-t43.dtb\0" \ | |
141 | "kernel=zImage-cm-t43\0" \ | |
142 | "bootscr=bootscr.img\0" \ | |
143 | "emmcroot=/dev/mmcblk0p2 rw\0" \ | |
144 | "emmcrootfstype=ext4 rootwait\0" \ | |
145 | "emmcargs=setenv bootargs console=${console} " \ | |
146 | "root=${emmcroot} " \ | |
147 | "rootfstype=${emmcrootfstype}\0" \ | |
148 | "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ | |
149 | "bootscript=echo Running bootscript from mmc ...; " \ | |
150 | "source ${loadaddr}\0" \ | |
151 | "emmcboot=echo Booting from emmc ... && " \ | |
152 | "run emmcargs && " \ | |
153 | "load mmc 1 ${loadaddr} ${kernel} && " \ | |
154 | "load mmc 1 ${fdtaddr} ${fdtfile} && " \ | |
155 | "bootz ${loadaddr} - ${fdtaddr}\0" | |
156 | ||
157 | #define CONFIG_BOOTCOMMAND \ | |
158 | "mmc dev 0; " \ | |
159 | "if mmc rescan; then " \ | |
160 | "if run loadbootscript; then " \ | |
161 | "run bootscript; " \ | |
162 | "fi; " \ | |
163 | "fi; " \ | |
164 | "mmc dev 1; " \ | |
165 | "if mmc rescan; then " \ | |
166 | "run emmcboot; " \ | |
167 | "fi;" | |
168 | ||
169 | ||
170 | #define CONFIG_CONS_INDEX 1 | |
171 | ||
172 | /* SPL defines. */ | |
173 | #define CONFIG_SPL_TEXT_BASE 0x40300350 | |
174 | #define CONFIG_SPL_MAX_SIZE (64 * 1024) | |
175 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) | |
176 | #define CONFIG_SPL_POWER_SUPPORT | |
177 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) | |
178 | #define CONFIG_SPL_SPI_SUPPORT | |
179 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
180 | #define CONFIG_SPL_SPI_LOAD | |
181 | ||
182 | #endif /* __CONFIG_CM_T43_H */ |