projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 76316a31 | 1 | /* |
| 4aecfb16 | 2 | * (C) Copyright 2007-2010 Michal Simek |
| 76316a31 | 3 | * |
| cb1bc63b | 4 | * Michal SIMEK <[email protected]> |
| 76316a31 MS |
5 | * |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef __CONFIG_H | |
| 26 | #define __CONFIG_H | |
| 27 | ||
| 52a822ed | 28 | #include "../board/xilinx/microblaze-generic/xparameters.h" |
| 76316a31 | 29 | |
| 4aecfb16 MS |
30 | /* MicroBlaze CPU */ |
| 31 | #define CONFIG_MICROBLAZE 1 | |
| 1a50f164 | 32 | #define MICROBLAZE_V5 1 |
| 76316a31 MS |
33 | |
| 34 | /* uart */ | |
| af7ae1a4 | 35 | #ifdef XILINX_UARTLITE_BASEADDR |
| 4aecfb16 MS |
36 | # define CONFIG_XILINX_UARTLITE |
| 37 | # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR | |
| 38 | # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE | |
| 39 | # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } | |
| 40 | # define CONSOLE_ARG "console=console=ttyUL0,115200\0" | |
| e7d591e8 | 41 | #elif XILINX_UART16550_BASEADDR |
| 4aecfb16 MS |
42 | # define CONFIG_SYS_NS16550 1 |
| 43 | # define CONFIG_SYS_NS16550_SERIAL | |
| 1de55ef1 SL |
44 | # if defined(__MICROBLAZEEL__) |
| 45 | # define CONFIG_SYS_NS16550_REG_SIZE -4 | |
| 46 | # else | |
| 47 | # define CONFIG_SYS_NS16550_REG_SIZE 4 | |
| 48 | # endif | |
| 4aecfb16 MS |
49 | # define CONFIG_CONS_INDEX 1 |
| 50 | # define CONFIG_SYS_NS16550_COM1 \ | |
| 1de55ef1 | 51 | ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) |
| 4aecfb16 MS |
52 | # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ |
| 53 | # define CONFIG_BAUDRATE 115200 | |
| 54 | ||
| 55 | /* The following table includes the supported baudrates */ | |
| 56 | # define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 57 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} | |
| 58 | # define CONSOLE_ARG "console=console=ttyS0,115200\0" | |
| e7d591e8 | 59 | #else |
| 4aecfb16 | 60 | # error Undefined uart |
| af7ae1a4 | 61 | #endif |
| 76316a31 MS |
62 | |
| 63 | /* setting reset address */ | |
| 14d0a02a | 64 | /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ |
| 76316a31 | 65 | |
| 17980495 | 66 | /* ethernet */ |
| 1252df06 | 67 | #undef CONFIG_SYS_ENET |
| 8422a35e SL |
68 | #if defined(XILINX_EMACLITE_BASEADDR) |
| 69 | # define CONFIG_XILINX_EMACLITE 1 | |
| 4aecfb16 | 70 | # define CONFIG_SYS_ENET |
| 8422a35e SL |
71 | #endif |
| 72 | #if defined(XILINX_LLTEMAC_BASEADDR) | |
| 73 | # define CONFIG_XILINX_LL_TEMAC 1 | |
| 4aecfb16 | 74 | # define CONFIG_SYS_ENET |
| e5845e21 | 75 | #endif |
| e634138e MS |
76 | #if defined(XILINX_AXIEMAC_BASEADDR) |
| 77 | # define CONFIG_XILINX_AXIEMAC 1 | |
| 78 | # define CONFIG_SYS_ENET | |
| 79 | #endif | |
| 330e5545 | 80 | |
| e5845e21 | 81 | #undef ET_DEBUG |
| 17980495 | 82 | |
| 76316a31 | 83 | /* gpio */ |
| 4c6a6f02 | 84 | #ifdef XILINX_GPIO_BASEADDR |
| 4aecfb16 MS |
85 | # define CONFIG_SYS_GPIO_0 1 |
| 86 | # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR | |
| 4c6a6f02 | 87 | #endif |
| 76316a31 MS |
88 | |
| 89 | /* interrupt controller */ | |
| 4d49b280 | 90 | #ifdef XILINX_INTC_BASEADDR |
| 4aecfb16 MS |
91 | # define CONFIG_SYS_INTC_0 1 |
| 92 | # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR | |
| 93 | # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS | |
| 4d49b280 | 94 | #endif |
| 76316a31 MS |
95 | |
| 96 | /* timer */ | |
| 4d49b280 | 97 | #ifdef XILINX_TIMER_BASEADDR |
| 4aecfb16 MS |
98 | # if (XILINX_TIMER_IRQ != -1) |
| 99 | # define CONFIG_SYS_TIMER_0 1 | |
| 100 | # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR | |
| 101 | # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ | |
| 102 | # define FREQUENCE XILINX_CLOCK_FREQ | |
| 103 | # define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) | |
| 104 | # endif | |
| 330e5545 | 105 | #elif XILINX_CLOCK_FREQ |
| 4aecfb16 | 106 | # define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ |
| 4d49b280 | 107 | #else |
| 4aecfb16 | 108 | # error BAD CLOCK FREQ |
| 4d49b280 | 109 | #endif |
| 19bf1fba | 110 | /* FSL */ |
| 6d0f6bcf | 111 | /* #define CONFIG_SYS_FSL_2 */ |
| 188dc16b | 112 | /* #define FSL_INTR_2 1 */ |
| 19bf1fba | 113 | |
| 76316a31 MS |
114 | /* |
| 115 | * memory layout - Example | |
| 14d0a02a | 116 | * CONFIG_SYS_TEXT_BASE = 0x1200_0000; |
| 6d0f6bcf JCPV |
117 | * CONFIG_SYS_SRAM_BASE = 0x1000_0000; |
| 118 | * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; | |
| 76316a31 | 119 | * |
| 6d0f6bcf JCPV |
120 | * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 |
| 121 | * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 | |
| 122 | * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 | |
| 76316a31 | 123 | * |
| 6d0f6bcf | 124 | * 0x1000_0000 CONFIG_SYS_SDRAM_BASE |
| 76316a31 | 125 | * FREE |
| 14d0a02a | 126 | * 0x1200_0000 CONFIG_SYS_TEXT_BASE |
| 76316a31 MS |
127 | * U-BOOT code |
| 128 | * 0x1202_0000 | |
| 129 | * FREE | |
| 130 | * | |
| 131 | * STACK | |
| 6d0f6bcf | 132 | * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE |
| 17980495 | 133 | * MALLOC_AREA 256kB Alloc |
| 6d0f6bcf | 134 | * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE |
| 17980495 | 135 | * MONITOR_CODE 256kB Env |
| 6d0f6bcf | 136 | * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET |
| 853643d8 | 137 | * GLOBAL_DATA 4kB bd, gd |
| 6d0f6bcf | 138 | * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE |
| 76316a31 MS |
139 | */ |
| 140 | ||
| 141 | /* ddr sdram - main memory */ | |
| 6d0f6bcf JCPV |
142 | #define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START |
| 143 | #define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE | |
| 144 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
| 145 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) | |
| 76316a31 MS |
146 | |
| 147 | /* global pointer */ | |
| 32556443 | 148 | /* start of global data */ |
| 4aecfb16 | 149 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 1020286e | 150 | (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 76316a31 MS |
151 | |
| 152 | /* monitor code */ | |
| 4aecfb16 | 153 | #define SIZE 0x40000 |
| 1020286e | 154 | #define CONFIG_SYS_MONITOR_LEN SIZE |
| 4aecfb16 | 155 | #define CONFIG_SYS_MONITOR_BASE \ |
| 1020286e MS |
156 | (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \ |
| 157 | - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) | |
| 4aecfb16 MS |
158 | #define CONFIG_SYS_MONITOR_END \ |
| 159 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 6d0f6bcf | 160 | #define CONFIG_SYS_MALLOC_LEN SIZE |
| 4aecfb16 MS |
161 | #define CONFIG_SYS_MALLOC_BASE \ |
| 162 | (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) | |
| 76316a31 MS |
163 | |
| 164 | /* stack */ | |
| 8fe7b29f | 165 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE |
| 76316a31 MS |
166 | |
| 167 | /*#define RAMENV */ | |
| 168 | #define FLASH | |
| 169 | ||
| 170 | #ifdef FLASH | |
| 4aecfb16 MS |
171 | # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START |
| 172 | # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE | |
| 173 | # define CONFIG_SYS_FLASH_CFI 1 | |
| 174 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
| 175 | /* ?empty sector */ | |
| 176 | # define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
| 177 | /* max number of memory banks */ | |
| 178 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 179 | /* max number of sectors on one chip */ | |
| 180 | # define CONFIG_SYS_MAX_FLASH_SECT 512 | |
| 181 | /* hardware flash protection */ | |
| 182 | # define CONFIG_SYS_FLASH_PROTECTION | |
| 183 | ||
| 184 | # ifdef RAMENV | |
| 185 | # define CONFIG_ENV_IS_NOWHERE 1 | |
| 186 | # define CONFIG_ENV_SIZE 0x1000 | |
| 187 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 188 | ||
| 189 | # else /* !RAMENV */ | |
| 190 | # define CONFIG_ENV_IS_IN_FLASH 1 | |
| 191 | /* 128K(one sector) for env */ | |
| 192 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 193 | # define CONFIG_ENV_ADDR \ | |
| 194 | (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) | |
| 195 | # define CONFIG_ENV_SIZE 0x20000 | |
| 196 | # endif /* !RAMBOOT */ | |
| 76316a31 | 197 | #else /* !FLASH */ |
| 4aecfb16 MS |
198 | /* ENV in RAM */ |
| 199 | # define CONFIG_SYS_NO_FLASH 1 | |
| 200 | # define CONFIG_ENV_IS_NOWHERE 1 | |
| 201 | # define CONFIG_ENV_SIZE 0x1000 | |
| 202 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 203 | /* hardware flash protection */ | |
| 204 | # define CONFIG_SYS_FLASH_PROTECTION | |
| 76316a31 MS |
205 | #endif /* !FLASH */ |
| 206 | ||
| 853643d8 MS |
207 | /* system ace */ |
| 208 | #ifdef XILINX_SYSACE_BASEADDR | |
| 4aecfb16 MS |
209 | # define CONFIG_SYSTEMACE |
| 210 | /* #define DEBUG_SYSTEMACE */ | |
| 211 | # define SYSTEMACE_CONFIG_FPGA | |
| 212 | # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR | |
| 213 | # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH | |
| 214 | # define CONFIG_DOS_PARTITION | |
| 853643d8 MS |
215 | #endif |
| 216 | ||
| e9b737de | 217 | #if defined(XILINX_USE_ICACHE) |
| 4aecfb16 | 218 | # define CONFIG_ICACHE |
| e9b737de | 219 | #else |
| 4aecfb16 | 220 | # undef CONFIG_ICACHE |
| e9b737de MS |
221 | #endif |
| 222 | ||
| 223 | #if defined(XILINX_USE_DCACHE) | |
| 4aecfb16 | 224 | # define CONFIG_DCACHE |
| e9b737de | 225 | #else |
| 4aecfb16 | 226 | # undef CONFIG_DCACHE |
| e9b737de MS |
227 | #endif |
| 228 | ||
| 079a136c JL |
229 | /* |
| 230 | * BOOTP options | |
| 231 | */ | |
| 232 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 233 | #define CONFIG_BOOTP_BOOTPATH | |
| 234 | #define CONFIG_BOOTP_GATEWAY | |
| 235 | #define CONFIG_BOOTP_HOSTNAME | |
| 76316a31 | 236 | |
| 5dc11a51 JL |
237 | /* |
| 238 | * Command line configuration. | |
| 239 | */ | |
| 240 | #include <config_cmd_default.h> | |
| 241 | ||
| 242 | #define CONFIG_CMD_ASKENV | |
| 5dc11a51 | 243 | #define CONFIG_CMD_IRQ |
| 5dc11a51 | 244 | #define CONFIG_CMD_MFSL |
| 330e5545 | 245 | #define CONFIG_CMD_ECHO |
| 4d49b280 | 246 | |
| e9b737de | 247 | #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) |
| 4aecfb16 | 248 | # define CONFIG_CMD_CACHE |
| e9b737de | 249 | #else |
| 4aecfb16 | 250 | # undef CONFIG_CMD_CACHE |
| e9b737de MS |
251 | #endif |
| 252 | ||
| 6d0f6bcf | 253 | #ifndef CONFIG_SYS_ENET |
| 4aecfb16 | 254 | # undef CONFIG_CMD_NET |
| 1252df06 | 255 | # undef CONFIG_CMD_NFS |
| 4d49b280 | 256 | #else |
| 4aecfb16 MS |
257 | # define CONFIG_CMD_PING |
| 258 | # define CONFIG_CMD_DHCP | |
| 4eb29cf0 | 259 | # define CONFIG_CMD_TFTPPUT |
| 4d49b280 | 260 | #endif |
| 853643d8 MS |
261 | |
| 262 | #if defined(CONFIG_SYSTEMACE) | |
| 4aecfb16 MS |
263 | # define CONFIG_CMD_EXT2 |
| 264 | # define CONFIG_CMD_FAT | |
| 853643d8 | 265 | #endif |
| 5dc11a51 JL |
266 | |
| 267 | #if defined(FLASH) | |
| 4aecfb16 MS |
268 | # define CONFIG_CMD_ECHO |
| 269 | # define CONFIG_CMD_FLASH | |
| 270 | # define CONFIG_CMD_IMLS | |
| 271 | # define CONFIG_CMD_JFFS2 | |
| 272 | ||
| 273 | # if !defined(RAMENV) | |
| 274 | # define CONFIG_CMD_SAVEENV | |
| 275 | # define CONFIG_CMD_SAVES | |
| 276 | # endif | |
| 853643d8 | 277 | #else |
| 4aecfb16 MS |
278 | # undef CONFIG_CMD_IMLS |
| 279 | # undef CONFIG_CMD_FLASH | |
| 280 | # undef CONFIG_CMD_JFFS2 | |
| 5dc11a51 | 281 | #endif |
| 76316a31 | 282 | |
| 5dc11a51 | 283 | #if defined(CONFIG_CMD_JFFS2) |
| 144876a3 | 284 | /* JFFS2 partitions */ |
| 68d7d651 | 285 | #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ |
| 942556a9 SR |
286 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 287 | #define CONFIG_FLASH_CFI_MTD | |
| c82a541d | 288 | #define MTDIDS_DEFAULT "nor0=flash-0" |
| 144876a3 MS |
289 | |
| 290 | /* default mtd partition table */ | |
| c82a541d | 291 | #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ |
| 144876a3 MS |
292 | "256k(env),3m(kernel),1m(romfs),"\ |
| 293 | "1m(cramfs),-(jffs2)" | |
| 294 | #endif | |
| 295 | ||
| 76316a31 | 296 | /* Miscellaneous configurable options */ |
| 6d0f6bcf | 297 | #define CONFIG_SYS_PROMPT "U-Boot-mONStR> " |
| 4aecfb16 MS |
298 | /* size of console buffer */ |
| 299 | #define CONFIG_SYS_CBSIZE 512 | |
| 300 | /* print buffer size */ | |
| 301 | #define CONFIG_SYS_PBSIZE \ | |
| 302 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 303 | /* max number of command args */ | |
| 304 | #define CONFIG_SYS_MAXARGS 15 | |
| 6d0f6bcf | 305 | #define CONFIG_SYS_LONGHELP |
| 4aecfb16 MS |
306 | /* default load address */ |
| 307 | #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START | |
| 76316a31 | 308 | |
| 330e5545 | 309 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
| 76316a31 | 310 | #define CONFIG_BOOTARGS "root=romfs" |
| 330e5545 | 311 | #define CONFIG_HOSTNAME XILINX_BOARD_NAME |
| 853643d8 | 312 | #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" |
| 76316a31 | 313 | #define CONFIG_IPADDR 192.168.0.3 |
| 853643d8 MS |
314 | #define CONFIG_SERVERIP 192.168.0.5 |
| 315 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 76316a31 MS |
316 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
| 317 | ||
| 318 | /* architecture dependent code */ | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_USR_EXCEP /* user exception */ |
| 320 | #define CONFIG_SYS_HZ 1000 | |
| 76316a31 | 321 | |
| 0900bee9 | 322 | #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" |
| 144876a3 | 323 | |
| 4aecfb16 | 324 | #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ |
| c82a541d SL |
325 | "nor0=flash-0\0"\ |
| 326 | "mtdparts=mtdparts=flash-0:"\ | |
| 144876a3 MS |
327 | "256k(u-boot),256k(env),3m(kernel),"\ |
| 328 | "1m(romfs),1m(cramfs),-(jffs2)\0" | |
| 329 | ||
| 188dc16b | 330 | #define CONFIG_CMDLINE_EDITING |
| 188dc16b | 331 | |
| 0900bee9 MS |
332 | /* Use the HUSH parser */ |
| 333 | #define CONFIG_SYS_HUSH_PARSER | |
| 334 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 4aecfb16 | 335 | # define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 0900bee9 MS |
336 | #endif |
| 337 | ||
| 37e892d9 MS |
338 | /* Enable flat device tree support */ |
| 339 | #define CONFIG_LMB 1 | |
| 340 | #define CONFIG_FIT 1 | |
| 341 | #define CONFIG_OF_LIBFDT 1 | |
| 342 | ||
| 8422a35e | 343 | #if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC) |
| f5e5e1ff SL |
344 | # define CONFIG_MII 1 |
| 345 | # define CONFIG_CMD_MII 1 | |
| 346 | # define CONFIG_PHY_GIGE 1 | |
| 347 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 | |
| 348 | # define CONFIG_PHYLIB 1 | |
| 349 | # define CONFIG_PHY_ATHEROS 1 | |
| 350 | # define CONFIG_PHY_BROADCOM 1 | |
| 351 | # define CONFIG_PHY_DAVICOM 1 | |
| 352 | # define CONFIG_PHY_LXT 1 | |
| 353 | # define CONFIG_PHY_MARVELL 1 | |
| 354 | # define CONFIG_PHY_MICREL 1 | |
| 355 | # define CONFIG_PHY_NATSEMI 1 | |
| 356 | # define CONFIG_PHY_REALTEK 1 | |
| 357 | # define CONFIG_PHY_VITESSE 1 | |
| 358 | #else | |
| 359 | # undef CONFIG_MII | |
| 360 | # undef CONFIG_CMD_MII | |
| 361 | # undef CONFIG_PHYLIB | |
| 362 | #endif | |
| 363 | ||
| 76316a31 | 364 | #endif /* __CONFIG_H */ |