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1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright 2018 NXP | |
4 | */ | |
5 | ||
6 | #ifndef __IMX8M_EVK_H | |
7 | #define __IMX8M_EVK_H | |
8 | ||
9 | #include <linux/sizes.h> | |
1af3c7f4 | 10 | #include <linux/stringify.h> |
86ac7a9a PF |
11 | #include <asm/arch/imx-regs.h> |
12 | ||
b297c0d7 PF |
13 | #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) |
14 | ||
86ac7a9a PF |
15 | #define CONFIG_SPL_MAX_SIZE (124 * 1024) |
16 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
17 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR | |
18 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 | |
86ac7a9a PF |
19 | |
20 | #ifdef CONFIG_SPL_BUILD | |
21 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ | |
078111b9 | 22 | #define CONFIG_SPL_WATCHDOG |
9ca00684 | 23 | #define CONFIG_SPL_DRIVERS_MISC |
933b2f09 | 24 | #define CONFIG_SPL_POWER |
975e7cf3 | 25 | #define CONFIG_SPL_I2C |
86ac7a9a PF |
26 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
27 | #define CONFIG_SPL_STACK 0x187FF0 | |
28 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
29 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
83061dbd | 30 | #define CONFIG_SPL_GPIO |
86ac7a9a PF |
31 | #define CONFIG_SPL_MMC_SUPPORT |
32 | #define CONFIG_SPL_BSS_START_ADDR 0x00180000 | |
33 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ | |
34 | #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 | |
35 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ | |
36 | #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 | |
86ac7a9a PF |
37 | |
38 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ | |
39 | #define CONFIG_MALLOC_F_ADDR 0x182000 | |
40 | /* For RAW image gives a error info not panic */ | |
41 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE | |
42 | ||
43 | #undef CONFIG_DM_MMC | |
44 | #undef CONFIG_DM_PMIC | |
45 | #undef CONFIG_DM_PMIC_PFUZE100 | |
46 | ||
86ac7a9a PF |
47 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
48 | ||
49 | #define CONFIG_POWER | |
50 | #define CONFIG_POWER_I2C | |
51 | #define CONFIG_POWER_PFUZE100 | |
52 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
53 | #endif | |
54 | ||
55 | #define CONFIG_REMAKE_ELF | |
56 | ||
86ac7a9a PF |
57 | /* ENET Config */ |
58 | /* ENET1 */ | |
59 | #if defined(CONFIG_CMD_NET) | |
86ac7a9a PF |
60 | #define CONFIG_MII |
61 | #define CONFIG_ETHPRIME "FEC" | |
62 | ||
63 | #define CONFIG_FEC_MXC | |
64 | #define CONFIG_FEC_XCV_TYPE RGMII | |
65 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
66 | #define FEC_QUIRK_ENET_MAC | |
67 | ||
68 | #define CONFIG_PHY_GIGE | |
69 | #define IMX_FEC_BASE 0x30BE0000 | |
86ac7a9a PF |
70 | #endif |
71 | ||
5b3c76e8 AG |
72 | #ifndef CONFIG_SPL_BUILD |
73 | #define BOOT_TARGET_DEVICES(func) \ | |
74 | func(MMC, mmc, 0) \ | |
75 | func(MMC, mmc, 1) \ | |
76 | func(DHCP, dhcp, na) | |
77 | ||
78 | #include <config_distro_bootcmd.h> | |
79 | #endif | |
80 | ||
86ac7a9a PF |
81 | /* Initial environment variables */ |
82 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5b3c76e8 AG |
83 | BOOTENV \ |
84 | "scriptaddr=0x43500000\0" \ | |
85 | "kernel_addr_r=0x40880000\0" \ | |
86ac7a9a | 86 | "image=Image\0" \ |
502f3ca0 | 87 | "console=ttymxc0,115200\0" \ |
86ac7a9a | 88 | "fdt_addr=0x43000000\0" \ |
86ac7a9a | 89 | "boot_fdt=try\0" \ |
05737f35 | 90 | "fdt_file=imx8mq-evk.dtb\0" \ |
86ac7a9a | 91 | "initrd_addr=0x43800000\0" \ |
acbc1d86 | 92 | "bootm_size=0x10000000\0" \ |
86ac7a9a PF |
93 | "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ |
94 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
86ac7a9a PF |
95 | |
96 | /* Link Definitions */ | |
86ac7a9a PF |
97 | |
98 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
99 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | |
100 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
101 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
102 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
103 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
104 | ||
86ac7a9a PF |
105 | #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ |
106 | ||
86ac7a9a PF |
107 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
108 | #define PHYS_SDRAM 0x40000000 | |
109 | #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ | |
110 | ||
86ac7a9a PF |
111 | #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR |
112 | ||
113 | /* Monitor Command Prompt */ | |
114 | #undef CONFIG_SYS_PROMPT | |
115 | #define CONFIG_SYS_PROMPT "u-boot=> " | |
86ac7a9a PF |
116 | #define CONFIG_SYS_CBSIZE 1024 |
117 | #define CONFIG_SYS_MAXARGS 64 | |
118 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
119 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
120 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
121 | ||
122 | #define CONFIG_IMX_BOOTAUX | |
123 | ||
86ac7a9a PF |
124 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
125 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
126 | ||
86ac7a9a PF |
127 | #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
128 | ||
129 | #define CONFIG_MXC_GPIO | |
130 | ||
86ac7a9a PF |
131 | #define CONFIG_OF_SYSTEM_SETUP |
132 | ||
133 | #ifndef CONFIG_SPL_BUILD | |
134 | #define CONFIG_DM_PMIC | |
135 | #endif | |
136 | ||
137 | #endif |