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gpio: npcm: Add persist feature to sgpio module
[J-u-boot.git] / drivers / mtd / cfi_flash.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5653fc33 2/*
bf9e3b38 3 * (C) Copyright 2002-2004
5653fc33
WD		 4 * Brad Kemp, Seranoa Networks, [email protected]
5 *
6 * Copyright (C) 2003 Arabella Software Ltd.
7 * Yuli Barcohen <[email protected]>
5653fc33 8 *
bf9e3b38
WD		 9 * Copyright (C) 2004
10 * Ed Okerson
260421a2
SR		 11 *
12 * Copyright (C) 2006
13 * Tolunay Orkun <[email protected]>
5653fc33
WD		 14 */
15
16/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 17/* #define DEBUG */
18
03de305e 19#include <config.h>
24b852a7 20#include <console.h>
f1056910 21#include <dm.h>
3a7d5571 22#include <env.h>
f1056910
TC		 23#include <errno.h>
24#include <fdt_support.h>
b79fdc76 25#include <flash.h>
691d719d 26#include <init.h>
c30b7adb 27#include <irq_func.h>
f7ae49fc 28#include <log.h>
03de305e 29#include <time.h>
401d1c4f 30#include <asm/global_data.h>
5653fc33 31#include <asm/processor.h>
3a197b2f 32#include <asm/io.h>
4c0d4c3b 33#include <asm/byteorder.h>
aedadf10 34#include <asm/unaligned.h>
f3998fdc 35#include <env_internal.h>
c05ed00a 36#include <linux/delay.h>
fa36ae79 37#include <mtd/cfi_flash.h>
a9f5faba 38#include <watchdog.h>
028ab6b5 39
5653fc33 40/*
7e5b9b47
HS		 41 * This file implements a Common Flash Interface (CFI) driver for
42 * U-Boot.
43 *
44 * The width of the port and the width of the chips are determined at
45 * initialization. These widths are used to calculate the address for
46 * access CFI data structures.
5653fc33
WD		 47 *
48 * References
49 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
50 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
51 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
52 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 53 * AMD CFI Specification, Release 2.0 December 1, 2001
54 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
55 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 56 *
65cc0e2a 57 * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 58 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 59 */
60
f1056910
TC		 61DECLARE_GLOBAL_DATA_PTR;
62
7e5b9b47 63static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
4ffeab2c 64#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef 65static uint flash_verbose = 1;
4ffeab2c
MF		 66#else
67#define flash_verbose 1
68#endif
92eb729b 69
2a112b23
WD		 70flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
71
00dcb07c
JH		 72#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
73#define __maybe_weak __weak
74#else
75#define __maybe_weak static
76#endif
77
6f726f95
SR		 78/*
79 * 0xffff is an undefined value for the configuration register. When
80 * this value is returned, the configuration register shall not be
81 * written at all (default mode).
82 */
83static u16 cfi_flash_config_reg(int i)
84{
85#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
87#else
88 return 0xffff;
89#endif
90}
91
ca5def3f 92#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
144fef87 93int cfi_flash_num_flash_banks = CFI_MAX_FLASH_BANKS;
d9a35697
MS		 94#else
95int cfi_flash_num_flash_banks;
ca5def3f
SR		 96#endif
97
f1056910
TC		 98#ifdef CONFIG_CFI_FLASH /* for driver model */
99static void cfi_flash_init_dm(void)
100{
101 struct udevice *dev;
102
103 cfi_flash_num_flash_banks = 0;
104 /*
105 * The uclass_first_device() will probe the first device and
106 * uclass_next_device() will probe the rest if they exist. So
107 * that cfi_flash_probe() will get called assigning the base
108 * addresses that are available.
109 */
110 for (uclass_first_device(UCLASS_MTD, &dev);
111 dev;
112 uclass_next_device(&dev)) {
113 }
114}
115
f1056910
TC		 116phys_addr_t cfi_flash_bank_addr(int i)
117{
1ec0a37e 118 return flash_info[i].base;
f1056910
TC		 119}
120#else
00dcb07c 121__weak phys_addr_t cfi_flash_bank_addr(int i)
b00e19cc 122{
65cc0e2a 123 return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
b00e19cc 124}
f1056910 125#endif
b00e19cc 126
00dcb07c 127__weak unsigned long cfi_flash_bank_size(int i)
ec50a8e3 128{
65cc0e2a
TR		 129#ifdef CFG_SYS_FLASH_BANKS_SIZES
130 return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
ec50a8e3
IY		 131#else
132 return 0;
133#endif
134}
ec50a8e3 135
00dcb07c 136__maybe_weak void flash_write8(u8 value, void *addr)
cdbaefb5
HS		 137{
138 __raw_writeb(value, addr);
139}
140
00dcb07c 141__maybe_weak void flash_write16(u16 value, void *addr)
cdbaefb5
HS		 142{
143 __raw_writew(value, addr);
144}
145
00dcb07c 146__maybe_weak void flash_write32(u32 value, void *addr)
cdbaefb5
HS		 147{
148 __raw_writel(value, addr);
149}
150
00dcb07c 151__maybe_weak void flash_write64(u64 value, void *addr)
cdbaefb5
HS		 152{
153 /* No architectures currently implement __raw_writeq() */
154 *(volatile u64 *)addr = value;
155}
156
00dcb07c 157__maybe_weak u8 flash_read8(void *addr)
cdbaefb5
HS		 158{
159 return __raw_readb(addr);
160}
161
00dcb07c 162__maybe_weak u16 flash_read16(void *addr)
cdbaefb5
HS		 163{
164 return __raw_readw(addr);
165}
166
00dcb07c 167__maybe_weak u32 flash_read32(void *addr)
cdbaefb5
HS		 168{
169 return __raw_readl(addr);
170}
171
00dcb07c 172__maybe_weak u64 flash_read64(void *addr)
cdbaefb5
HS		 173{
174 /* No architectures currently implement __raw_readq() */
175 return *(volatile u64 *)addr;
176}
177
5653fc33 178/*-----------------------------------------------------------------------
5653fc33 179 */
ddcf0540 180#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
d75eacf9 181 (defined(CONFIG_SYS_MONITOR_BASE) && \
65cc0e2a 182 (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
236c49a1 183static flash_info_t *flash_get_info(ulong base)
be60a902
HS		 184{
185 int i;
24c185cf 186 flash_info_t *info;
5653fc33 187
98150e7e 188 for (i = 0; i < CFI_FLASH_BANKS; i++) {
e2e273a3 189 info = &flash_info[i];
be60a902
HS		 190 if (info->size && info->start[0] <= base &&
191 base <= info->start[0] + info->size - 1)
24c185cf 192 return info;
be60a902 193 }
5653fc33 194
24c185cf 195 return NULL;
be60a902 196}
5653fc33
WD		 197#endif
198
12d30aa7
HS		 199unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
200{
201 if (sect != (info->sector_count - 1))
202 return info->start[sect + 1] - info->start[sect];
203 else
204 return info->start[0] + info->size - info->start[sect];
205}
206
bf9e3b38
WD		 207/*-----------------------------------------------------------------------
208 * create an address based on the offset and the port width
209 */
12d30aa7 210static inline void *
ca2b07a8 211flash_map(flash_info_t *info, flash_sect_t sect, uint offset)
bf9e3b38 212{
e303be2d 213 unsigned int byte_offset = offset * info->portwidth;
12d30aa7 214
53879b17 215 return (void *)(info->start[sect] + (byte_offset << info->chip_lsb));
12d30aa7
HS		 216}
217
218static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
c0350fbf 219 unsigned int offset, void *addr)
12d30aa7 220{
bf9e3b38
WD		 221}
222
be60a902
HS		 223/*-----------------------------------------------------------------------
224 * make a proper sized command based on the port and chip widths
225 */
7288f972 226static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 227{
228 int i;
93c56f21
VL		 229 int cword_offset;
230 int cp_offset;
65cc0e2a 231#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS		 232 u32 cmd_le = cpu_to_le32(cmd);
233#endif
93c56f21 234 uchar val;
be60a902
HS		 235 uchar *cp = (uchar *) cmdbuf;
236
b168386b 237 for (i = info->portwidth; i > 0; i--) {
640f4e35 238 cword_offset = (info->portwidth - i) % info->chipwidth;
65cc0e2a 239#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
93c56f21 240 cp_offset = info->portwidth - i;
db91bb24 241 val = *((uchar *)&cmd_le + cword_offset);
be60a902 242#else
93c56f21 243 cp_offset = i - 1;
db91bb24 244 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 245#endif
7288f972 246 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 247 }
be60a902
HS		 248}
249
5653fc33 250#ifdef DEBUG
bf9e3b38
WD		 251/*-----------------------------------------------------------------------
252 * Debug support
253 */
188a5565 254static void print_longlong(char *str, unsigned long long data)
5653fc33
WD		 255{
256 int i;
257 char *cp;
bf9e3b38 258
640f4e35 259 cp = (char *)&data;
bf9e3b38 260 for (i = 0; i < 8; i++)
188a5565 261 sprintf(&str[i * 2], "%2.2x", *cp++);
bf9e3b38 262}
be60a902 263
188a5565 264static void flash_printqry(struct cfi_qry *qry)
bf9e3b38 265{
e23741f4 266 u8 *p = (u8 *)qry;
bf9e3b38
WD		 267 int x, y;
268
e23741f4
HS		 269 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
270 debug("%02x : ", x);
271 for (y = 0; y < 16; y++)
272 debug("%2.2x ", p[x + y]);
273 debug(" ");
bf9e3b38 274 for (y = 0; y < 16; y++) {
e23741f4 275 unsigned char c = p[x + y];
7223a8cb 276
e23741f4
HS		 277 if (c >= 0x20 && c <= 0x7e)
278 debug("%c", c);
279 else
280 debug(".");
bf9e3b38 281 }
e23741f4 282 debug("\n");
bf9e3b38 283 }
5653fc33
WD		 284}
285#endif
286
5653fc33
WD		 287/*-----------------------------------------------------------------------
288 * read a character at a port width address
289 */
ca2b07a8 290static inline uchar flash_read_uchar(flash_info_t *info, uint offset)
5653fc33
WD		 291{
292 uchar *cp;
12d30aa7 293 uchar retval;
bf9e3b38 294
188a5565 295 cp = flash_map(info, 0, offset);
65cc0e2a 296#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 297 retval = flash_read8(cp);
bf9e3b38 298#else
12d30aa7 299 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 300#endif
188a5565 301 flash_unmap(info, 0, offset, cp);
12d30aa7 302 return retval;
5653fc33
WD		 303}
304
90447ecb
TK		 305/*-----------------------------------------------------------------------
306 * read a word at a port width address, assume 16bit bus
307 */
ca2b07a8 308static inline ushort flash_read_word(flash_info_t *info, uint offset)
90447ecb
TK		 309{
310 ushort *addr, retval;
311
188a5565
MS		 312 addr = flash_map(info, 0, offset);
313 retval = flash_read16(addr);
314 flash_unmap(info, 0, offset, addr);
90447ecb
TK		 315 return retval;
316}
317
5653fc33 318/*-----------------------------------------------------------------------
260421a2 319 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 320 * port size word. Swap for ppc format.
321 */
ca2b07a8 322static ulong flash_read_long (flash_info_t *info, flash_sect_t sect,
3055793b 323 uint offset)
5653fc33 324{
bf9e3b38
WD		 325 uchar *addr;
326 ulong retval;
327
328#ifdef DEBUG
329 int x;
330#endif
188a5565 331 addr = flash_map(info, sect, offset);
5653fc33 332
bf9e3b38 333#ifdef DEBUG
188a5565 334 debug("long addr is at %p info->portwidth = %d\n", addr,
c0350fbf 335 info->portwidth);
0412e903 336 for (x = 0; x < 4 * info->portwidth; x++)
188a5565 337 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38 338#endif
65cc0e2a 339#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS		 340 retval = ((flash_read8(addr) << 16) |
341 (flash_read8(addr + info->portwidth) << 24) |
342 (flash_read8(addr + 2 * info->portwidth)) |
343 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 344#else
12d30aa7
HS		 345 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
346 (flash_read8(addr + info->portwidth - 1) << 16) |
347 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
348 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 349#endif
12d30aa7
HS		 350 flash_unmap(info, sect, offset, addr);
351
bf9e3b38 352 return retval;
5653fc33
WD		 353}
354
be60a902
HS		 355/*
356 * Write a proper sized command to the correct address
81b20ccc 357 */
236c49a1
MV		 358static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
359 uint offset, u32 cmd)
81b20ccc 360{
cdbaefb5 361 void *addr;
be60a902 362 cfiword_t cword;
81b20ccc 363
188a5565
MS		 364 addr = flash_map(info, sect, offset);
365 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 366 switch (info->portwidth) {
367 case FLASH_CFI_8BIT:
188a5565 368 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
c0350fbf 369 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 370 flash_write8(cword.w8, addr);
be60a902
HS		 371 break;
372 case FLASH_CFI_16BIT:
188a5565 373 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
c0350fbf
MS		 374 cmd, cword.w16,
375 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 376 flash_write16(cword.w16, addr);
be60a902
HS		 377 break;
378 case FLASH_CFI_32BIT:
188a5565 379 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
c0350fbf
MS		 380 cmd, cword.w32,
381 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 382 flash_write32(cword.w32, addr);
be60a902
HS		 383 break;
384 case FLASH_CFI_64BIT:
385#ifdef DEBUG
386 {
387 char str[20];
7e5b9b47 388
188a5565 389 print_longlong(str, cword.w64);
be60a902 390
188a5565 391 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
c0350fbf
MS		 392 addr, cmd, str,
393 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 394 }
be60a902 395#endif
622b9527 396 flash_write64(cword.w64, addr);
be60a902 397 break;
81b20ccc 398 }
be60a902
HS		 399
400 /* Ensure all the instructions are fully finished */
401 sync();
12d30aa7
HS		 402
403 flash_unmap(info, sect, offset, addr);
81b20ccc 404}
be60a902 405
ca2b07a8 406static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect)
81b20ccc 407{
188a5565
MS		 408 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
409 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 410}
81b20ccc 411
5653fc33
WD		 412/*-----------------------------------------------------------------------
413 */
c0350fbf
MS		 414static int flash_isequal(flash_info_t *info, flash_sect_t sect, uint offset,
415 uchar cmd)
5653fc33 416{
cdbaefb5 417 void *addr;
be60a902
HS		 418 cfiword_t cword;
419 int retval;
5653fc33 420
188a5565
MS		 421 addr = flash_map(info, sect, offset);
422 flash_make_cmd(info, cmd, &cword);
2662b40c 423
188a5565 424 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 425 switch (info->portwidth) {
426 case FLASH_CFI_8BIT:
188a5565 427 debug("is= %x %x\n", flash_read8(addr), cword.w8);
622b9527 428 retval = (flash_read8(addr) == cword.w8);
be60a902
HS		 429 break;
430 case FLASH_CFI_16BIT:
188a5565 431 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
622b9527 432 retval = (flash_read16(addr) == cword.w16);
be60a902
HS		 433 break;
434 case FLASH_CFI_32BIT:
188a5565 435 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
622b9527 436 retval = (flash_read32(addr) == cword.w32);
be60a902
HS		 437 break;
438 case FLASH_CFI_64BIT:
439#ifdef DEBUG
440 {
441 char str1[20];
442 char str2[20];
81b20ccc 443
188a5565
MS		 444 print_longlong(str1, flash_read64(addr));
445 print_longlong(str2, cword.w64);
446 debug("is= %s %s\n", str1, str2);
5653fc33 447 }
be60a902 448#endif
622b9527 449 retval = (flash_read64(addr) == cword.w64);
be60a902
HS		 450 break;
451 default:
452 retval = 0;
453 break;
454 }
12d30aa7
HS		 455 flash_unmap(info, sect, offset, addr);
456
be60a902
HS		 457 return retval;
458}
79b4cda0 459
be60a902
HS		 460/*-----------------------------------------------------------------------
461 */
c0350fbf
MS		 462static int flash_isset(flash_info_t *info, flash_sect_t sect, uint offset,
463 uchar cmd)
be60a902 464{
cdbaefb5 465 void *addr;
be60a902
HS		 466 cfiword_t cword;
467 int retval;
2662b40c 468
188a5565
MS		 469 addr = flash_map(info, sect, offset);
470 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 471 switch (info->portwidth) {
472 case FLASH_CFI_8BIT:
622b9527 473 retval = ((flash_read8(addr) & cword.w8) == cword.w8);
be60a902
HS		 474 break;
475 case FLASH_CFI_16BIT:
622b9527 476 retval = ((flash_read16(addr) & cword.w16) == cword.w16);
be60a902
HS		 477 break;
478 case FLASH_CFI_32BIT:
622b9527 479 retval = ((flash_read32(addr) & cword.w32) == cword.w32);
be60a902
HS		 480 break;
481 case FLASH_CFI_64BIT:
622b9527 482 retval = ((flash_read64(addr) & cword.w64) == cword.w64);
be60a902
HS		 483 break;
484 default:
485 retval = 0;
486 break;
487 }
12d30aa7
HS		 488 flash_unmap(info, sect, offset, addr);
489
be60a902
HS		 490 return retval;
491}
2662b40c 492
be60a902
HS		 493/*-----------------------------------------------------------------------
494 */
c0350fbf
MS		 495static int flash_toggle(flash_info_t *info, flash_sect_t sect, uint offset,
496 uchar cmd)
be60a902 497{
5312838d 498 u8 *addr;
be60a902
HS		 499 cfiword_t cword;
500 int retval;
656658dd 501
188a5565
MS		 502 addr = flash_map(info, sect, offset);
503 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 504 switch (info->portwidth) {
505 case FLASH_CFI_8BIT:
fb8c061e 506 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 507 break;
508 case FLASH_CFI_16BIT:
fb8c061e 509 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 510 break;
511 case FLASH_CFI_32BIT:
fb8c061e 512 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 513 break;
514 case FLASH_CFI_64BIT:
b168386b 515 retval = ((flash_read32(addr) != flash_read32(addr)) ||
640f4e35 516 (flash_read32(addr + 4) != flash_read32(addr + 4)));
be60a902
HS		 517 break;
518 default:
519 retval = 0;
520 break;
521 }
12d30aa7
HS		 522 flash_unmap(info, sect, offset, addr);
523
be60a902 524 return retval;
5653fc33
WD		 525}
526
be60a902
HS		 527/*
528 * flash_is_busy - check to see if the flash is busy
529 *
530 * This routine checks the status of the chip and returns true if the
531 * chip is busy.
7680c140 532 */
ca2b07a8 533static int flash_is_busy(flash_info_t *info, flash_sect_t sect)
7680c140 534{
be60a902 535 int retval;
7680c140 536
be60a902 537 switch (info->vendor) {
9c048b52 538 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 539 case CFI_CMDSET_INTEL_STANDARD:
540 case CFI_CMDSET_INTEL_EXTENDED:
188a5565 541 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
be60a902
HS		 542 break;
543 case CFI_CMDSET_AMD_STANDARD:
544 case CFI_CMDSET_AMD_EXTENDED:
545#ifdef CONFIG_FLASH_CFI_LEGACY
546 case CFI_CMDSET_AMD_LEGACY:
547#endif
72443c7f 548 if (info->sr_supported) {
188a5565 549 flash_write_cmd(info, sect, info->addr_unlock1,
c0350fbf 550 FLASH_CMD_READ_STATUS);
188a5565 551 retval = !flash_isset(info, sect, 0,
c0350fbf 552 FLASH_STATUS_DONE);
72443c7f 553 } else {
188a5565 554 retval = flash_toggle(info, sect, 0,
c0350fbf 555 AMD_STATUS_TOGGLE);
72443c7f
MV		 556 }
557
be60a902
HS		 558 break;
559 default:
560 retval = 0;
7680c140 561 }
38d2831d 562 debug("%s: %d\n", __func__, retval);
be60a902 563 return retval;
7680c140
WD		 564}
565
5653fc33 566/*-----------------------------------------------------------------------
be60a902
HS		 567 * wait for XSR.7 to be set. Time out with an error if it does not.
568 * This routine does not set the flash to read-array mode.
5653fc33 569 */
ca2b07a8 570static int flash_status_check(flash_info_t *info, flash_sect_t sector,
c0350fbf 571 ulong tout, char *prompt)
5653fc33 572{
be60a902 573 ulong start;
5653fc33 574
6d0f6bcf 575#if CONFIG_SYS_HZ != 1000
ddcf0540 576 /* Avoid overflow for large HZ */
c40c94a3 577 if ((ulong)CONFIG_SYS_HZ > 100000)
ddcf0540 578 tout *= (ulong)CONFIG_SYS_HZ / 1000;
c40c94a3
RA		 579 else
580 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
be60a902 581#endif
5653fc33 582
be60a902 583 /* Wait for command completion */
65cc0e2a 584#ifdef CFG_SYS_LOW_RES_TIMER
22d6c8fa 585 reset_timer();
e110c4fe 586#endif
188a5565 587 start = get_timer(0);
29caf930 588 schedule();
188a5565
MS		 589 while (flash_is_busy(info, sector)) {
590 if (get_timer(start) > tout) {
591 printf("Flash %s timeout at address %lx data %lx\n",
c0350fbf
MS		 592 prompt, info->start[sector],
593 flash_read_long(info, sector, 0));
188a5565 594 flash_write_cmd(info, sector, 0, info->cmd_reset);
e303be2d 595 udelay(1);
9aa7e531 596 return FL_ERR_TIMEOUT;
5653fc33 597 }
188a5565 598 udelay(1); /* also triggers watchdog */
5653fc33 599 }
9aa7e531 600 return FL_ERR_OK;
be60a902 601}
5653fc33 602
be60a902
HS		 603/*-----------------------------------------------------------------------
604 * Wait for XSR.7 to be set, if it times out print an error, otherwise
605 * do a full status check.
606 *
607 * This routine sets the flash to read-array mode.
608 */
ca2b07a8 609static int flash_full_status_check(flash_info_t *info, flash_sect_t sector,
c0350fbf 610 ulong tout, char *prompt)
be60a902
HS		 611{
612 int retcode;
5653fc33 613
188a5565 614 retcode = flash_status_check(info, sector, tout, prompt);
be60a902 615 switch (info->vendor) {
9c048b52 616 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 617 case CFI_CMDSET_INTEL_EXTENDED:
618 case CFI_CMDSET_INTEL_STANDARD:
9aa7e531 619 if (retcode == FL_ERR_OK &&
c0350fbf 620 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
9aa7e531 621 retcode = FL_ERR_INVAL;
188a5565 622 printf("Flash %s error at address %lx\n", prompt,
c0350fbf 623 info->start[sector]);
188a5565 624 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS |
be60a902 625 FLASH_STATUS_PSLBS)) {
188a5565
MS		 626 puts("Command Sequence Error.\n");
627 } else if (flash_isset(info, sector, 0,
be60a902 628 FLASH_STATUS_ECLBS)) {
188a5565 629 puts("Block Erase Error.\n");
9aa7e531 630 retcode = FL_ERR_NOT_ERASED;
188a5565 631 } else if (flash_isset(info, sector, 0,
be60a902 632 FLASH_STATUS_PSLBS)) {
188a5565 633 puts("Locking Error\n");
5653fc33 634 }
188a5565
MS		 635 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
636 puts("Block locked.\n");
9aa7e531 637 retcode = FL_ERR_PROTECTED;
be60a902 638 }
188a5565
MS		 639 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
640 puts("Vpp Low Error.\n");
5653fc33 641 }
188a5565 642 flash_write_cmd(info, sector, 0, info->cmd_reset);
a90b9575 643 udelay(1);
be60a902
HS		 644 break;
645 default:
646 break;
5653fc33 647 }
be60a902 648 return retcode;
5653fc33
WD		 649}
650
e5720823
TC		 651static int use_flash_status_poll(flash_info_t *info)
652{
653#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
654 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
655 info->vendor == CFI_CMDSET_AMD_STANDARD)
656 return 1;
657#endif
658 return 0;
659}
660
661static int flash_status_poll(flash_info_t *info, void *src, void *dst,
662 ulong tout, char *prompt)
663{
664#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
665 ulong start;
666 int ready;
667
668#if CONFIG_SYS_HZ != 1000
ddcf0540 669 /* Avoid overflow for large HZ */
e5720823 670 if ((ulong)CONFIG_SYS_HZ > 100000)
ddcf0540 671 tout *= (ulong)CONFIG_SYS_HZ / 1000;
e5720823
TC		 672 else
673 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
674#endif
675
676 /* Wait for command completion */
65cc0e2a 677#ifdef CFG_SYS_LOW_RES_TIMER
22d6c8fa 678 reset_timer();
e110c4fe 679#endif
e5720823 680 start = get_timer(0);
29caf930 681 schedule();
e5720823
TC		 682 while (1) {
683 switch (info->portwidth) {
684 case FLASH_CFI_8BIT:
685 ready = flash_read8(dst) == flash_read8(src);
686 break;
687 case FLASH_CFI_16BIT:
688 ready = flash_read16(dst) == flash_read16(src);
689 break;
690 case FLASH_CFI_32BIT:
691 ready = flash_read32(dst) == flash_read32(src);
692 break;
693 case FLASH_CFI_64BIT:
694 ready = flash_read64(dst) == flash_read64(src);
695 break;
696 default:
697 ready = 0;
698 break;
699 }
700 if (ready)
701 break;
702 if (get_timer(start) > tout) {
703 printf("Flash %s timeout at address %lx data %lx\n",
704 prompt, (ulong)dst, (ulong)flash_read8(dst));
9aa7e531 705 return FL_ERR_TIMEOUT;
e5720823
TC		 706 }
707 udelay(1); /* also triggers watchdog */
708 }
709#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
9aa7e531 710 return FL_ERR_OK;
e5720823
TC		 711}
712
5653fc33
WD		 713/*-----------------------------------------------------------------------
714 */
ca2b07a8 715static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
5653fc33 716{
65cc0e2a 717#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 718 unsigned short w;
719 unsigned int l;
720 unsigned long long ll;
721#endif
5653fc33 722
be60a902
HS		 723 switch (info->portwidth) {
724 case FLASH_CFI_8BIT:
622b9527 725 cword->w8 = c;
be60a902
HS		 726 break;
727 case FLASH_CFI_16BIT:
65cc0e2a 728#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 729 w = c;
730 w <<= 8;
622b9527 731 cword->w16 = (cword->w16 >> 8) | w;
be60a902 732#else
622b9527 733 cword->w16 = (cword->w16 << 8) | c;
81b20ccc 734#endif
be60a902
HS		 735 break;
736 case FLASH_CFI_32BIT:
65cc0e2a 737#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 738 l = c;
739 l <<= 24;
622b9527 740 cword->w32 = (cword->w32 >> 8) | l;
be60a902 741#else
622b9527 742 cword->w32 = (cword->w32 << 8) | c;
be60a902
HS		 743#endif
744 break;
745 case FLASH_CFI_64BIT:
65cc0e2a 746#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 747 ll = c;
748 ll <<= 56;
622b9527 749 cword->w64 = (cword->w64 >> 8) | ll;
be60a902 750#else
622b9527 751 cword->w64 = (cword->w64 << 8) | c;
be60a902
HS		 752#endif
753 break;
260421a2 754 }
be60a902 755}
5653fc33 756
0f8e851e
JG		 757/*
758 * Loop through the sector table starting from the previously found sector.
759 * Searches forwards or backwards, dependent on the passed address.
be60a902 760 */
ca2b07a8 761static flash_sect_t find_sector(flash_info_t *info, ulong addr)
be60a902 762{
11dc4010 763 static flash_sect_t saved_sector; /* previously found sector */
e303be2d 764 static flash_info_t *saved_info; /* previously used flash bank */
0f8e851e
JG		 765 flash_sect_t sector = saved_sector;
766
4f89da49 767 if (info != saved_info || sector >= info->sector_count)
e303be2d
SR		 768 sector = 0;
769
5701ba82 770 while ((sector < info->sector_count - 1) &&
c0350fbf 771 (info->start[sector] < addr))
0f8e851e
JG		 772 sector++;
773 while ((info->start[sector] > addr) && (sector > 0))
774 /*
775 * also decrements the sector in case of an overshot
776 * in the first loop
777 */
778 sector--;
779
780 saved_sector = sector;
e303be2d 781 saved_info = info;
be60a902 782 return sector;
5653fc33
WD		 783}
784
785/*-----------------------------------------------------------------------
5653fc33 786 */
c0350fbf 787static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword)
5653fc33 788{
09ce9921 789 void *dstaddr = (void *)dest;
be60a902 790 int flag;
a7292871
JG		 791 flash_sect_t sect = 0;
792 char sect_found = 0;
5653fc33 793
be60a902
HS		 794 /* Check if Flash is (sufficiently) erased */
795 switch (info->portwidth) {
796 case FLASH_CFI_8BIT:
622b9527 797 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8);
be60a902
HS		 798 break;
799 case FLASH_CFI_16BIT:
622b9527 800 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16);
be60a902
HS		 801 break;
802 case FLASH_CFI_32BIT:
622b9527 803 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32);
be60a902
HS		 804 break;
805 case FLASH_CFI_64BIT:
622b9527 806 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64);
be60a902
HS		 807 break;
808 default:
12d30aa7
HS		 809 flag = 0;
810 break;
5653fc33 811 }
09ce9921 812 if (!flag)
9aa7e531 813 return FL_ERR_NOT_ERASED;
5653fc33 814
be60a902 815 /* Disable interrupts which might cause a timeout here */
188a5565 816 flag = disable_interrupts();
79b4cda0 817
be60a902 818 switch (info->vendor) {
9c048b52 819 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 820 case CFI_CMDSET_INTEL_EXTENDED:
821 case CFI_CMDSET_INTEL_STANDARD:
188a5565
MS		 822 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
823 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
be60a902
HS		 824 break;
825 case CFI_CMDSET_AMD_EXTENDED:
826 case CFI_CMDSET_AMD_STANDARD:
0d01f66d 827 sect = find_sector(info, dest);
188a5565
MS		 828 flash_unlock_seq(info, sect);
829 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE);
a7292871 830 sect_found = 1;
be60a902 831 break;
b4db4a76
PYC		 832#ifdef CONFIG_FLASH_CFI_LEGACY
833 case CFI_CMDSET_AMD_LEGACY:
834 sect = find_sector(info, dest);
188a5565
MS		 835 flash_unlock_seq(info, 0);
836 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE);
b4db4a76
PYC		 837 sect_found = 1;
838 break;
839#endif
5653fc33
WD		 840 }
841
be60a902
HS		 842 switch (info->portwidth) {
843 case FLASH_CFI_8BIT:
622b9527 844 flash_write8(cword.w8, dstaddr);
be60a902
HS		 845 break;
846 case FLASH_CFI_16BIT:
622b9527 847 flash_write16(cword.w16, dstaddr);
be60a902
HS		 848 break;
849 case FLASH_CFI_32BIT:
622b9527 850 flash_write32(cword.w32, dstaddr);
be60a902
HS		 851 break;
852 case FLASH_CFI_64BIT:
622b9527 853 flash_write64(cword.w64, dstaddr);
be60a902 854 break;
5653fc33
WD		 855 }
856
be60a902
HS		 857 /* re-enable interrupts if necessary */
858 if (flag)
188a5565 859 enable_interrupts();
5653fc33 860
a7292871 861 if (!sect_found)
188a5565 862 sect = find_sector(info, dest);
a7292871 863
e5720823
TC		 864 if (use_flash_status_poll(info))
865 return flash_status_poll(info, &cword, dstaddr,
866 info->write_tout, "write");
867 else
868 return flash_full_status_check(info, sect,
869 info->write_tout, "write");
5653fc33
WD		 870}
871
6d0f6bcf 872#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 873
ca2b07a8 874static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp,
c0350fbf 875 int len)
5653fc33 876{
be60a902
HS		 877 flash_sect_t sector;
878 int cnt;
879 int retcode;
5312838d
MS		 880 u8 *src = cp;
881 u8 *dst = (u8 *)dest;
882 u8 *dst2 = dst;
85c344e5 883 int flag = 1;
96ef831f
GL		 884 uint offset = 0;
885 unsigned int shift;
9c048b52 886 uchar write_cmd;
cdbaefb5 887
0dc80e27
SR		 888 switch (info->portwidth) {
889 case FLASH_CFI_8BIT:
96ef831f 890 shift = 0;
0dc80e27
SR		 891 break;
892 case FLASH_CFI_16BIT:
96ef831f 893 shift = 1;
0dc80e27
SR		 894 break;
895 case FLASH_CFI_32BIT:
96ef831f 896 shift = 2;
0dc80e27
SR		 897 break;
898 case FLASH_CFI_64BIT:
96ef831f 899 shift = 3;
0dc80e27
SR		 900 break;
901 default:
9aa7e531 902 retcode = FL_ERR_INVAL;
0dc80e27
SR		 903 goto out_unmap;
904 }
905
96ef831f
GL		 906 cnt = len >> shift;
907
85c344e5 908 while ((cnt-- > 0) && (flag == 1)) {
0dc80e27
SR		 909 switch (info->portwidth) {
910 case FLASH_CFI_8BIT:
911 flag = ((flash_read8(dst2) & flash_read8(src)) ==
912 flash_read8(src));
913 src += 1, dst2 += 1;
914 break;
915 case FLASH_CFI_16BIT:
916 flag = ((flash_read16(dst2) & flash_read16(src)) ==
917 flash_read16(src));
918 src += 2, dst2 += 2;
919 break;
920 case FLASH_CFI_32BIT:
921 flag = ((flash_read32(dst2) & flash_read32(src)) ==
922 flash_read32(src));
923 src += 4, dst2 += 4;
924 break;
925 case FLASH_CFI_64BIT:
926 flag = ((flash_read64(dst2) & flash_read64(src)) ==
927 flash_read64(src));
928 src += 8, dst2 += 8;
929 break;
930 }
931 }
932 if (!flag) {
9aa7e531 933 retcode = FL_ERR_NOT_ERASED;
0dc80e27
SR		 934 goto out_unmap;
935 }
936
937 src = cp;
188a5565 938 sector = find_sector(info, dest);
bf9e3b38
WD		 939
940 switch (info->vendor) {
9c048b52 941 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 942 case CFI_CMDSET_INTEL_STANDARD:
943 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52 944 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
ddcf0540
MS		 945 FLASH_CMD_WRITE_BUFFER_PROG :
946 FLASH_CMD_WRITE_TO_BUFFER;
188a5565
MS		 947 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
948 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
949 flash_write_cmd(info, sector, 0, write_cmd);
950 retcode = flash_status_check(info, sector,
c0350fbf
MS		 951 info->buffer_write_tout,
952 "write to buffer");
9aa7e531 953 if (retcode == FL_ERR_OK) {
be60a902 954 /* reduce the number of loops by the width of
a6d18f27
MS		 955 * the port
956 */
96ef831f 957 cnt = len >> shift;
188a5565 958 flash_write_cmd(info, sector, 0, cnt - 1);
be60a902
HS		 959 while (cnt-- > 0) {
960 switch (info->portwidth) {
961 case FLASH_CFI_8BIT:
cdbaefb5
HS		 962 flash_write8(flash_read8(src), dst);
963 src += 1, dst += 1;
be60a902
HS		 964 break;
965 case FLASH_CFI_16BIT:
cdbaefb5
HS		 966 flash_write16(flash_read16(src), dst);
967 src += 2, dst += 2;
be60a902
HS		 968 break;
969 case FLASH_CFI_32BIT:
cdbaefb5
HS		 970 flash_write32(flash_read32(src), dst);
971 src += 4, dst += 4;
be60a902
HS		 972 break;
973 case FLASH_CFI_64BIT:
cdbaefb5
HS		 974 flash_write64(flash_read64(src), dst);
975 src += 8, dst += 8;
be60a902
HS		 976 break;
977 default:
9aa7e531 978 retcode = FL_ERR_INVAL;
12d30aa7 979 goto out_unmap;
be60a902
HS		 980 }
981 }
188a5565 982 flash_write_cmd(info, sector, 0,
c0350fbf 983 FLASH_CMD_WRITE_BUFFER_CONFIRM);
188a5565 984 retcode = flash_full_status_check(
be60a902
HS		 985 info, sector, info->buffer_write_tout,
986 "buffer write");
987 }
12d30aa7
HS		 988
989 break;
be60a902 990
5653fc33
WD		 991 case CFI_CMDSET_AMD_STANDARD:
992 case CFI_CMDSET_AMD_EXTENDED:
7570a0cc 993 flash_unlock_seq(info, sector);
96ef831f
GL		 994
995#ifdef CONFIG_FLASH_SPANSION_S29WS_N
996 offset = ((unsigned long)dst - info->start[sector]) >> shift;
997#endif
998 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
999 cnt = len >> shift;
7dedefdf 1000 flash_write_cmd(info, sector, offset, cnt - 1);
be60a902
HS		 1001
1002 switch (info->portwidth) {
1003 case FLASH_CFI_8BIT:
cdbaefb5
HS		 1004 while (cnt-- > 0) {
1005 flash_write8(flash_read8(src), dst);
1006 src += 1, dst += 1;
1007 }
be60a902
HS		 1008 break;
1009 case FLASH_CFI_16BIT:
cdbaefb5
HS		 1010 while (cnt-- > 0) {
1011 flash_write16(flash_read16(src), dst);
1012 src += 2, dst += 2;
1013 }
be60a902
HS		 1014 break;
1015 case FLASH_CFI_32BIT:
cdbaefb5
HS		 1016 while (cnt-- > 0) {
1017 flash_write32(flash_read32(src), dst);
1018 src += 4, dst += 4;
1019 }
be60a902
HS		 1020 break;
1021 case FLASH_CFI_64BIT:
cdbaefb5
HS		 1022 while (cnt-- > 0) {
1023 flash_write64(flash_read64(src), dst);
1024 src += 8, dst += 8;
1025 }
be60a902
HS		 1026 break;
1027 default:
9aa7e531 1028 retcode = FL_ERR_INVAL;
12d30aa7 1029 goto out_unmap;
be60a902
HS		 1030 }
1031
188a5565 1032 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
e5720823
TC		 1033 if (use_flash_status_poll(info))
1034 retcode = flash_status_poll(info, src - (1 << shift),
1035 dst - (1 << shift),
1036 info->buffer_write_tout,
1037 "buffer write");
1038 else
1039 retcode = flash_full_status_check(info, sector,
1040 info->buffer_write_tout,
1041 "buffer write");
12d30aa7 1042 break;
be60a902 1043
5653fc33 1044 default:
188a5565 1045 debug("Unknown Command Set\n");
9aa7e531 1046 retcode = FL_ERR_INVAL;
12d30aa7 1047 break;
5653fc33 1048 }
12d30aa7
HS		 1049
1050out_unmap:
12d30aa7 1051 return retcode;
5653fc33 1052}
6d0f6bcf 1053#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1054
5653fc33 1055/*-----------------------------------------------------------------------
5653fc33 1056 */
ca2b07a8 1057int flash_erase(flash_info_t *info, int s_first, int s_last)
5653fc33 1058{
be60a902
HS		 1059 int rcode = 0;
1060 int prot;
1061 flash_sect_t sect;
e5720823 1062 int st;
5653fc33 1063
be60a902 1064 if (info->flash_id != FLASH_MAN_CFI) {
188a5565 1065 puts("Can't erase unknown flash type - aborted\n");
be60a902
HS		 1066 return 1;
1067 }
4f89da49 1068 if (s_first < 0 || s_first > s_last) {
188a5565 1069 puts("- no sectors to erase\n");
be60a902
HS		 1070 return 1;
1071 }
2662b40c 1072
be60a902 1073 prot = 0;
0412e903
MS		 1074 for (sect = s_first; sect <= s_last; ++sect)
1075 if (info->protect[sect])
be60a902 1076 prot++;
be60a902 1077 if (prot) {
188a5565 1078 printf("- Warning: %d protected sectors will not be erased!\n",
c0350fbf 1079 prot);
6ea808ef 1080 } else if (flash_verbose) {
188a5565 1081 putc('\n');
be60a902 1082 }
bf9e3b38 1083
be60a902 1084 for (sect = s_first; sect <= s_last; sect++) {
de15a06a
JH		 1085 if (ctrlc()) {
1086 printf("\n");
1087 return 1;
1088 }
1089
be60a902 1090 if (info->protect[sect] == 0) { /* not protected */
6822a647
JH		 1091#ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
1092 int k;
1093 int size;
1094 int erased;
1095 u32 *flash;
1096
1097 /*
1098 * Check if whole sector is erased
1099 */
1100 size = flash_sector_size(info, sect);
1101 erased = 1;
1102 flash = (u32 *)info->start[sect];
1103 /* divide by 4 for longword access */
1104 size = size >> 2;
1105 for (k = 0; k < size; k++) {
1106 if (flash_read32(flash++) != 0xffffffff) {
1107 erased = 0;
1108 break;
1109 }
1110 }
1111 if (erased) {
1112 if (flash_verbose)
1113 putc(',');
1114 continue;
1115 }
1116#endif
be60a902 1117 switch (info->vendor) {
9c048b52 1118 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1119 case CFI_CMDSET_INTEL_STANDARD:
1120 case CFI_CMDSET_INTEL_EXTENDED:
188a5565 1121 flash_write_cmd(info, sect, 0,
c0350fbf 1122 FLASH_CMD_CLEAR_STATUS);
188a5565 1123 flash_write_cmd(info, sect, 0,
c0350fbf 1124 FLASH_CMD_BLOCK_ERASE);
188a5565 1125 flash_write_cmd(info, sect, 0,
c0350fbf 1126 FLASH_CMD_ERASE_CONFIRM);
be60a902
HS		 1127 break;
1128 case CFI_CMDSET_AMD_STANDARD:
1129 case CFI_CMDSET_AMD_EXTENDED:
188a5565
MS		 1130 flash_unlock_seq(info, sect);
1131 flash_write_cmd(info, sect,
be60a902
HS		 1132 info->addr_unlock1,
1133 AMD_CMD_ERASE_START);
188a5565
MS		 1134 flash_unlock_seq(info, sect);
1135 flash_write_cmd(info, sect, 0,
c0350fbf 1136 info->cmd_erase_sector);
be60a902
HS		 1137 break;
1138#ifdef CONFIG_FLASH_CFI_LEGACY
1139 case CFI_CMDSET_AMD_LEGACY:
188a5565
MS		 1140 flash_unlock_seq(info, 0);
1141 flash_write_cmd(info, 0, info->addr_unlock1,
be60a902 1142 AMD_CMD_ERASE_START);
188a5565
MS		 1143 flash_unlock_seq(info, 0);
1144 flash_write_cmd(info, sect, 0,
be60a902
HS		 1145 AMD_CMD_ERASE_SECTOR);
1146 break;
1147#endif
1148 default:
9f720216 1149 debug("Unknown flash vendor %d\n",
c0350fbf 1150 info->vendor);
be60a902 1151 break;
bf9e3b38 1152 }
be60a902 1153
e5720823 1154 if (use_flash_status_poll(info)) {
11dc4010 1155 cfiword_t cword;
e5720823 1156 void *dest;
7223a8cb 1157
622b9527 1158 cword.w64 = 0xffffffffffffffffULL;
e5720823
TC		 1159 dest = flash_map(info, sect, 0);
1160 st = flash_status_poll(info, &cword, dest,
ddcf0540
MS		 1161 info->erase_blk_tout,
1162 "erase");
e5720823 1163 flash_unmap(info, sect, 0, dest);
12d7fed9 1164 } else {
e5720823
TC		 1165 st = flash_full_status_check(info, sect,
1166 info->erase_blk_tout,
1167 "erase");
12d7fed9
MS		 1168 }
1169
e5720823 1170 if (st)
be60a902 1171 rcode = 1;
e5720823 1172 else if (flash_verbose)
188a5565 1173 putc('.');
5653fc33 1174 }
5653fc33 1175 }
6ea808ef
PZ		 1176
1177 if (flash_verbose)
188a5565 1178 puts(" done\n");
6ea808ef 1179
be60a902 1180 return rcode;
5653fc33 1181}
bf9e3b38 1182
70084df7
SR		 1183#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1184static int sector_erased(flash_info_t *info, int i)
1185{
1186 int k;
1187 int size;
4d2ca9d6 1188 u32 *flash;
70084df7
SR		 1189
1190 /*
1191 * Check if whole sector is erased
1192 */
1193 size = flash_sector_size(info, i);
4d2ca9d6 1194 flash = (u32 *)info->start[i];
70084df7
SR		 1195 /* divide by 4 for longword access */
1196 size = size >> 2;
1197
1198 for (k = 0; k < size; k++) {
4d2ca9d6 1199 if (flash_read32(flash++) != 0xffffffff)
70084df7
SR		 1200 return 0; /* not erased */
1201 }
1202
1203 return 1; /* erased */
1204}
1205#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1206
ca2b07a8 1207void flash_print_info(flash_info_t *info)
5653fc33 1208{
be60a902 1209 int i;
4d13cbad 1210
be60a902 1211 if (info->flash_id != FLASH_MAN_CFI) {
188a5565 1212 puts("missing or unknown FLASH type\n");
be60a902
HS		 1213 return;
1214 }
1215
188a5565 1216 printf("%s flash (%d x %d)",
c0350fbf
MS		 1217 info->name,
1218 (info->portwidth << 3), (info->chipwidth << 3));
640f4e35 1219 if (info->size < 1024 * 1024)
188a5565 1220 printf(" Size: %ld kB in %d Sectors\n",
c0350fbf 1221 info->size >> 10, info->sector_count);
be60a902 1222 else
188a5565 1223 printf(" Size: %ld MB in %d Sectors\n",
c0350fbf 1224 info->size >> 20, info->sector_count);
188a5565 1225 printf(" ");
be60a902 1226 switch (info->vendor) {
dde0913b
MS		 1227 case CFI_CMDSET_INTEL_PROG_REGIONS:
1228 printf("Intel Prog Regions");
1229 break;
1230 case CFI_CMDSET_INTEL_STANDARD:
1231 printf("Intel Standard");
1232 break;
1233 case CFI_CMDSET_INTEL_EXTENDED:
1234 printf("Intel Extended");
1235 break;
1236 case CFI_CMDSET_AMD_STANDARD:
1237 printf("AMD Standard");
1238 break;
1239 case CFI_CMDSET_AMD_EXTENDED:
1240 printf("AMD Extended");
1241 break;
be60a902 1242#ifdef CONFIG_FLASH_CFI_LEGACY
dde0913b
MS		 1243 case CFI_CMDSET_AMD_LEGACY:
1244 printf("AMD Legacy");
1245 break;
4d13cbad 1246#endif
dde0913b
MS		 1247 default:
1248 printf("Unknown (%d)", info->vendor);
1249 break;
be60a902 1250 }
188a5565 1251 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
c0350fbf 1252 info->manufacturer_id);
188a5565 1253 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
c0350fbf 1254 info->device_id);
5b448adb
HS		 1255 if ((info->device_id & 0xff) == 0x7E) {
1256 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
c0350fbf 1257 info->device_id2);
be60a902 1258 }
4f89da49 1259 if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock)
d2af028d 1260 printf("\n Advanced Sector Protection (PPB) enabled");
188a5565 1261 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
c0350fbf 1262 info->erase_blk_tout, info->write_tout);
be60a902 1263 if (info->buffer_size > 1) {
876c52f3 1264 printf(" Buffer write timeout: %ld ms, ",
c0350fbf 1265 info->buffer_write_tout);
876c52f3 1266 printf("buffer size: %d bytes\n", info->buffer_size);
5653fc33 1267 }
5653fc33 1268
188a5565 1269 puts("\n Sector Start Addresses:");
be60a902 1270 for (i = 0; i < info->sector_count; ++i) {
2e97394a 1271 if (ctrlc())
70084df7 1272 break;
be60a902 1273 if ((i % 5) == 0)
70084df7 1274 putc('\n');
6d0f6bcf 1275#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902 1276 /* print empty and read-only info */
188a5565 1277 printf(" %08lX %c %s ",
c0350fbf
MS		 1278 info->start[i],
1279 sector_erased(info, i) ? 'E' : ' ',
1280 info->protect[i] ? "RO" : " ");
6d0f6bcf 1281#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
188a5565 1282 printf(" %08lX %s ",
c0350fbf
MS		 1283 info->start[i],
1284 info->protect[i] ? "RO" : " ");
bf9e3b38 1285#endif
be60a902 1286 }
188a5565 1287 putc('\n');
5653fc33
WD		 1288}
1289
9a042e9c
JVB		 1290/*-----------------------------------------------------------------------
1291 * This is used in a few places in write_buf() to show programming
1292 * progress. Making it a function is nasty because it needs to do side
1293 * effect updates to digit and dots. Repeated code is nasty too, so
1294 * we define it once here.
1295 */
98fbad63 1296#if CONFIG_FLASH_SHOW_PROGRESS
f0105727 1297#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
6ea808ef
PZ		 1298 if (flash_verbose) { \
1299 dots -= dots_sub; \
4f89da49 1300 if (scale > 0 && dots <= 0) { \
6ea808ef 1301 if ((digit % 5) == 0) \
188a5565 1302 printf("%d", digit / 5); \
6ea808ef 1303 else \
188a5565 1304 putc('.'); \
6ea808ef
PZ		 1305 digit--; \
1306 dots += scale; \
1307 } \
9a042e9c 1308 }
f0105727
SR		 1309#else
1310#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1311#endif
9a042e9c 1312
be60a902
HS		 1313/*-----------------------------------------------------------------------
1314 * Copy memory to flash, returns:
1315 * 0 - OK
1316 * 1 - write timeout
1317 * 2 - Flash not erased
5653fc33 1318 */
ca2b07a8 1319int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
5653fc33 1320{
be60a902 1321 ulong wp;
12d30aa7 1322 uchar *p;
be60a902 1323 int aln;
5653fc33 1324 cfiword_t cword;
be60a902 1325 int i, rc;
6d0f6bcf 1326#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1327 int buffered_size;
5653fc33 1328#endif
98fbad63 1329#if CONFIG_FLASH_SHOW_PROGRESS
9a042e9c
JVB		 1330 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1331 int scale = 0;
1332 int dots = 0;
1333
1334 /*
1335 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1336 */
1337 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1338 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1339 CONFIG_FLASH_SHOW_PROGRESS);
1340 }
1341#endif
1342
be60a902
HS		 1343 /* get lower aligned address */
1344 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1345
be60a902 1346 /* handle unaligned start */
d3525b6b
MS		 1347 aln = addr - wp;
1348 if (aln != 0) {
622b9527 1349 cword.w32 = 0;
09ce9921 1350 p = (uchar *)wp;
12d30aa7 1351 for (i = 0; i < aln; ++i)
188a5565 1352 flash_add_byte(info, &cword, flash_read8(p + i));
5653fc33 1353
be60a902 1354 for (; (i < info->portwidth) && (cnt > 0); i++) {
188a5565 1355 flash_add_byte(info, &cword, *src++);
be60a902 1356 cnt--;
be60a902 1357 }
12d30aa7 1358 for (; (cnt == 0) && (i < info->portwidth); ++i)
188a5565 1359 flash_add_byte(info, &cword, flash_read8(p + i));
12d30aa7 1360
188a5565 1361 rc = flash_write_cfiword(info, wp, cword);
12d30aa7 1362 if (rc != 0)
be60a902 1363 return rc;
12d30aa7
HS		 1364
1365 wp += i;
f0105727 1366 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1367 }
1368
1369 /* handle the aligned part */
6d0f6bcf 1370#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS		 1371 buffered_size = (info->portwidth / info->chipwidth);
1372 buffered_size *= info->buffer_size;
1373 while (cnt >= info->portwidth) {
1374 /* prohibit buffer write when buffer_size is 1 */
1375 if (info->buffer_size == 1) {
622b9527 1376 cword.w32 = 0;
be60a902 1377 for (i = 0; i < info->portwidth; i++)
188a5565 1378 flash_add_byte(info, &cword, *src++);
d3525b6b
MS		 1379 rc = flash_write_cfiword(info, wp, cword);
1380 if (rc != 0)
be60a902
HS		 1381 return rc;
1382 wp += info->portwidth;
1383 cnt -= info->portwidth;
1384 continue;
1385 }
1386
1387 /* write buffer until next buffered_size aligned boundary */
1388 i = buffered_size - (wp % buffered_size);
1389 if (i > cnt)
1390 i = cnt;
d3525b6b 1391 rc = flash_write_cfibuffer(info, wp, src, i);
9aa7e531 1392 if (rc != FL_ERR_OK)
be60a902
HS		 1393 return rc;
1394 i -= i & (info->portwidth - 1);
1395 wp += i;
1396 src += i;
1397 cnt -= i;
f0105727 1398 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
de15a06a
JH		 1399 /* Only check every once in a while */
1400 if ((cnt & 0xFFFF) < buffered_size && ctrlc())
9aa7e531 1401 return FL_ERR_ABORTED;
be60a902
HS		 1402 }
1403#else
1404 while (cnt >= info->portwidth) {
622b9527 1405 cword.w32 = 0;
0412e903 1406 for (i = 0; i < info->portwidth; i++)
188a5565 1407 flash_add_byte(info, &cword, *src++);
d3525b6b
MS		 1408 rc = flash_write_cfiword(info, wp, cword);
1409 if (rc != 0)
be60a902
HS		 1410 return rc;
1411 wp += info->portwidth;
1412 cnt -= info->portwidth;
f0105727 1413 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
de15a06a
JH		 1414 /* Only check every once in a while */
1415 if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
9aa7e531 1416 return FL_ERR_ABORTED;
be60a902 1417 }
6d0f6bcf 1418#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1419
0412e903 1420 if (cnt == 0)
be60a902 1421 return (0);
be60a902
HS		 1422
1423 /*
1424 * handle unaligned tail bytes
1425 */
622b9527 1426 cword.w32 = 0;
09ce9921 1427 p = (uchar *)wp;
12d30aa7 1428 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
188a5565 1429 flash_add_byte(info, &cword, *src++);
be60a902
HS		 1430 --cnt;
1431 }
12d30aa7 1432 for (; i < info->portwidth; ++i)
188a5565 1433 flash_add_byte(info, &cword, flash_read8(p + i));
be60a902 1434
188a5565 1435 return flash_write_cfiword(info, wp, cword);
5653fc33 1436}
bf9e3b38 1437
20043a4c
SR		 1438static inline int manufact_match(flash_info_t *info, u32 manu)
1439{
1440 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16);
1441}
1442
5653fc33
WD		 1443/*-----------------------------------------------------------------------
1444 */
6d0f6bcf 1445#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902 1446
81316a90
HB		 1447static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
1448{
88ecd8bf 1449 if (manufact_match(info, INTEL_MANUFACT) &&
c0350fbf 1450 info->device_id == NUMONYX_256MBIT) {
81316a90
HB		 1451 /*
1452 * see errata called
1453 * "Numonyx Axcell P33/P30 Specification Update" :)
1454 */
1455 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID);
1456 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT,
1457 prot)) {
1458 /*
1459 * cmd must come before FLASH_CMD_PROTECT + 20us
1460 * Disable interrupts which might cause a timeout here.
1461 */
1462 int flag = disable_interrupts();
1463 unsigned short cmd;
1464
1465 if (prot)
1466 cmd = FLASH_CMD_PROTECT_SET;
1467 else
1468 cmd = FLASH_CMD_PROTECT_CLEAR;
58eab328
AP		 1469
1470 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
81316a90
HB		 1471 flash_write_cmd(info, sector, 0, cmd);
1472 /* re-enable interrupts if necessary */
1473 if (flag)
1474 enable_interrupts();
1475 }
1476 return 1;
1477 }
1478 return 0;
1479}
1480
ca2b07a8 1481int flash_real_protect(flash_info_t *info, long sector, int prot)
5653fc33 1482{
be60a902 1483 int retcode = 0;
5653fc33 1484
bc9019e1 1485 switch (info->vendor) {
dde0913b
MS		 1486 case CFI_CMDSET_INTEL_PROG_REGIONS:
1487 case CFI_CMDSET_INTEL_STANDARD:
1488 case CFI_CMDSET_INTEL_EXTENDED:
1489 if (!cfi_protect_bugfix(info, sector, prot)) {
1490 flash_write_cmd(info, sector, 0,
c0350fbf 1491 FLASH_CMD_CLEAR_STATUS);
dde0913b 1492 flash_write_cmd(info, sector, 0,
c0350fbf 1493 FLASH_CMD_PROTECT);
dde0913b 1494 if (prot)
81316a90 1495 flash_write_cmd(info, sector, 0,
c0350fbf 1496 FLASH_CMD_PROTECT_SET);
dde0913b 1497 else
81316a90 1498 flash_write_cmd(info, sector, 0,
c0350fbf 1499 FLASH_CMD_PROTECT_CLEAR);
dde0913b
MS		 1500 }
1501 break;
1502 case CFI_CMDSET_AMD_EXTENDED:
1503 case CFI_CMDSET_AMD_STANDARD:
1504 /* U-Boot only checks the first byte */
1505 if (manufact_match(info, ATM_MANUFACT)) {
1506 if (prot) {
1507 flash_unlock_seq(info, 0);
1508 flash_write_cmd(info, 0,
1509 info->addr_unlock1,
1510 ATM_CMD_SOFTLOCK_START);
1511 flash_unlock_seq(info, 0);
1512 flash_write_cmd(info, sector, 0,
1513 ATM_CMD_LOCK_SECT);
1514 } else {
1515 flash_write_cmd(info, 0,
1516 info->addr_unlock1,
1517 AMD_CMD_UNLOCK_START);
1518 if (info->device_id == ATM_ID_BV6416)
1519 flash_write_cmd(info, sector,
c0350fbf 1520 0, ATM_CMD_UNLOCK_SECT);
54652991 1521 }
dde0913b
MS		 1522 }
1523 if (info->legacy_unlock) {
1524 int flag = disable_interrupts();
1525 int lock_flag;
1526
1527 flash_unlock_seq(info, 0);
1528 flash_write_cmd(info, 0, info->addr_unlock1,
1529 AMD_CMD_SET_PPB_ENTRY);
1530 lock_flag = flash_isset(info, sector, 0, 0x01);
1531 if (prot) {
1532 if (lock_flag) {
188a5565 1533 flash_write_cmd(info, sector, 0,
c0350fbf 1534 AMD_CMD_PPB_LOCK_BC1);
dde0913b 1535 flash_write_cmd(info, sector, 0,
c0350fbf 1536 AMD_CMD_PPB_LOCK_BC2);
bc9019e1 1537 }
dde0913b 1538 debug("sector %ld %slocked\n", sector,
c0350fbf 1539 lock_flag ? "" : "already ");
dde0913b
MS		 1540 } else {
1541 if (!lock_flag) {
1542 debug("unlock %ld\n", sector);
1543 flash_write_cmd(info, 0, 0,
c0350fbf 1544 AMD_CMD_PPB_UNLOCK_BC1);
dde0913b 1545 flash_write_cmd(info, 0, 0,
c0350fbf 1546 AMD_CMD_PPB_UNLOCK_BC2);
66863b05 1547 }
dde0913b 1548 debug("sector %ld %sunlocked\n", sector,
c0350fbf 1549 !lock_flag ? "" : "already ");
66863b05 1550 }
dde0913b
MS		 1551 if (flag)
1552 enable_interrupts();
1553
1554 if (flash_status_check(info, sector,
c0350fbf
MS		 1555 info->erase_blk_tout,
1556 prot ? "protect" : "unprotect"))
dde0913b
MS		 1557 printf("status check error\n");
1558
1559 flash_write_cmd(info, 0, 0,
1560 AMD_CMD_SET_PPB_EXIT_BC1);
1561 flash_write_cmd(info, 0, 0,
1562 AMD_CMD_SET_PPB_EXIT_BC2);
1563 }
1564 break;
4e00acde 1565#ifdef CONFIG_FLASH_CFI_LEGACY
dde0913b
MS		 1566 case CFI_CMDSET_AMD_LEGACY:
1567 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1568 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
1569 if (prot)
ddcf0540
MS		 1570 flash_write_cmd(info, sector, 0,
1571 FLASH_CMD_PROTECT_SET);
dde0913b 1572 else
ddcf0540
MS		 1573 flash_write_cmd(info, sector, 0,
1574 FLASH_CMD_PROTECT_CLEAR);
4e00acde 1575#endif
bc9019e1 1576 };
bf9e3b38 1577
df4e813b
SR		 1578 /*
1579 * Flash needs to be in status register read mode for
1580 * flash_full_status_check() to work correctly
1581 */
1582 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
d3525b6b 1583 retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
c0350fbf 1584 prot ? "protect" : "unprotect");
d3525b6b 1585 if (retcode == 0) {
be60a902
HS		 1586 info->protect[sector] = prot;
1587
1588 /*
1589 * On some of Intel's flash chips (marked via legacy_unlock)
1590 * unprotect unprotects all locking.
1591 */
4f89da49 1592 if (prot == 0 && info->legacy_unlock) {
be60a902
HS		 1593 flash_sect_t i;
1594
1595 for (i = 0; i < info->sector_count; i++) {
1596 if (info->protect[i])
188a5565 1597 flash_real_protect(info, i, 1);
be60a902 1598 }
5653fc33 1599 }
5653fc33 1600 }
be60a902 1601 return retcode;
5653fc33 1602}
bf9e3b38 1603
5653fc33 1604/*-----------------------------------------------------------------------
be60a902 1605 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1606 */
ca2b07a8 1607void flash_read_user_serial(flash_info_t *info, void *buffer, int offset,
c0350fbf 1608 int len)
5653fc33 1609{
be60a902
HS		 1610 uchar *src;
1611 uchar *dst;
bf9e3b38 1612
be60a902 1613 dst = buffer;
188a5565
MS		 1614 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION);
1615 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1616 memcpy(dst, src + offset, len);
1617 flash_write_cmd(info, 0, 0, info->cmd_reset);
a90b9575 1618 udelay(1);
12d30aa7 1619 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1620}
1621
be60a902
HS		 1622/*
1623 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1624 */
ca2b07a8 1625void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset,
c0350fbf 1626 int len)
5653fc33 1627{
be60a902 1628 uchar *src;
bf9e3b38 1629
188a5565
MS		 1630 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
1631 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1632 memcpy(buffer, src + offset, len);
1633 flash_write_cmd(info, 0, 0, info->cmd_reset);
a90b9575 1634 udelay(1);
12d30aa7 1635 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1636}
1637
6d0f6bcf 1638#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1639
0ddf06dd
HS		 1640/*-----------------------------------------------------------------------
1641 * Reverse the order of the erase regions in the CFI QRY structure.
1642 * This is needed for chips that are either a) correctly detected as
1643 * top-boot, or b) buggy.
1644 */
1645static void cfi_reverse_geometry(struct cfi_qry *qry)
1646{
1647 unsigned int i, j;
1648 u32 tmp;
1649
1650 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
4f89da49
MS		 1651 tmp = get_unaligned(&qry->erase_region_info[i]);
1652 put_unaligned(get_unaligned(&qry->erase_region_info[j]),
1653 &qry->erase_region_info[i]);
1654 put_unaligned(tmp, &qry->erase_region_info[j]);
0ddf06dd
HS		 1655 }
1656}
be60a902 1657
260421a2
SR		 1658/*-----------------------------------------------------------------------
1659 * read jedec ids from device and set corresponding fields in info struct
1660 *
1661 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1662 *
0ddf06dd
HS		 1663 */
1664static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1665{
1666 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
a90b9575 1667 udelay(1);
0ddf06dd
HS		 1668 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1669 udelay(1000); /* some flash are slow to respond */
188a5565 1670 info->manufacturer_id = flash_read_uchar(info,
c0350fbf 1671 FLASH_OFFSET_MANUFACTURER_ID);
d77c7ac4 1672 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
188a5565
MS		 1673 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) :
1674 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID);
0ddf06dd
HS		 1675 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1676}
1677
1678static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1679{
1680 info->cmd_reset = FLASH_CMD_RESET;
1681
1682 cmdset_intel_read_jedec_ids(info);
1683 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1684
6d0f6bcf 1685#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS		 1686 /* read legacy lock/unlock bit from intel flash */
1687 if (info->ext_addr) {
c0350fbf
MS		 1688 info->legacy_unlock =
1689 flash_read_uchar(info, info->ext_addr + 5) & 0x08;
0ddf06dd
HS		 1690 }
1691#endif
1692
1693 return 0;
1694}
1695
1696static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1697{
c8a9a82c
MS		 1698 ushort bank_id = 0;
1699 uchar manu_id;
2544f470 1700 uchar feature;
3a7b2c21 1701
0ddf06dd
HS		 1702 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1703 flash_unlock_seq(info, 0);
1704 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1705 udelay(1000); /* some flash are slow to respond */
90447ecb 1706
c8a9a82c 1707 manu_id = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID);
3a7b2c21 1708 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
c8a9a82c
MS		 1709 while (manu_id == FLASH_CONTINUATION_CODE && bank_id < 0x800) {
1710 bank_id += 0x100;
1711 manu_id = flash_read_uchar(info,
c0350fbf 1712 bank_id | FLASH_OFFSET_MANUFACTURER_ID);
3a7b2c21 1713 }
c8a9a82c 1714 info->manufacturer_id = manu_id;
90447ecb 1715
2544f470
YS		 1716 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n",
1717 info->ext_addr, info->cfi_version);
1718 if (info->ext_addr && info->cfi_version >= 0x3134) {
1719 /* read software feature (at 0x53) */
1720 feature = flash_read_uchar(info, info->ext_addr + 0x13);
1721 debug("feature = 0x%x\n", feature);
1722 info->sr_supported = feature & 0x1;
1723 }
72443c7f 1724
b168386b 1725 switch (info->chipwidth) {
90447ecb 1726 case FLASH_CFI_8BIT:
188a5565 1727 info->device_id = flash_read_uchar(info,
c0350fbf 1728 FLASH_OFFSET_DEVICE_ID);
90447ecb
TK		 1729 if (info->device_id == 0x7E) {
1730 /* AMD 3-byte (expanded) device ids */
188a5565 1731 info->device_id2 = flash_read_uchar(info,
c0350fbf 1732 FLASH_OFFSET_DEVICE_ID2);
90447ecb 1733 info->device_id2 <<= 8;
188a5565 1734 info->device_id2 |= flash_read_uchar(info,
90447ecb
TK		 1735 FLASH_OFFSET_DEVICE_ID3);
1736 }
1737 break;
1738 case FLASH_CFI_16BIT:
188a5565 1739 info->device_id = flash_read_word(info,
c0350fbf 1740 FLASH_OFFSET_DEVICE_ID);
5b448adb
HS		 1741 if ((info->device_id & 0xff) == 0x7E) {
1742 /* AMD 3-byte (expanded) device ids */
188a5565 1743 info->device_id2 = flash_read_uchar(info,
c0350fbf 1744 FLASH_OFFSET_DEVICE_ID2);
5b448adb 1745 info->device_id2 <<= 8;
188a5565 1746 info->device_id2 |= flash_read_uchar(info,
5b448adb
HS		 1747 FLASH_OFFSET_DEVICE_ID3);
1748 }
90447ecb
TK		 1749 break;
1750 default:
1751 break;
0ddf06dd
HS		 1752 }
1753 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1754 udelay(1);
0ddf06dd
HS		 1755}
1756
1757static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1758{
1759 info->cmd_reset = AMD_CMD_RESET;
07b2c5c0 1760 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR;
0ddf06dd
HS		 1761
1762 cmdset_amd_read_jedec_ids(info);
1763 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1764
66863b05 1765#ifdef CONFIG_SYS_FLASH_PROTECTION
ac6b9115
SR		 1766 if (info->ext_addr) {
1767 /* read sector protect/unprotect scheme (at 0x49) */
1768 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8)
66863b05
AG		 1769 info->legacy_unlock = 1;
1770 }
1771#endif
1772
0ddf06dd
HS		 1773 return 0;
1774}
1775
1776#ifdef CONFIG_FLASH_CFI_LEGACY
ca2b07a8 1777static void flash_read_jedec_ids(flash_info_t *info)
260421a2
SR		 1778{
1779 info->manufacturer_id = 0;
1780 info->device_id = 0;
1781 info->device_id2 = 0;
1782
1783 switch (info->vendor) {
9c048b52 1784 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1785 case CFI_CMDSET_INTEL_STANDARD:
1786 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1787 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1788 break;
1789 case CFI_CMDSET_AMD_STANDARD:
1790 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1791 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1792 break;
1793 default:
1794 break;
1795 }
1796}
1797
5653fc33 1798/*-----------------------------------------------------------------------
be60a902
HS		 1799 * Call board code to request info about non-CFI flash.
1800 * board_flash_get_legacy needs to fill in at least:
1801 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1802 */
09ce9921 1803static int flash_detect_legacy(phys_addr_t base, int banknum)
5653fc33 1804{
be60a902 1805 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1806
be60a902
HS		 1807 if (board_flash_get_legacy(base, banknum, info)) {
1808 /* board code may have filled info completely. If not, we
a6d18f27
MS		 1809 * use JEDEC ID probing.
1810 */
be60a902
HS		 1811 if (!info->vendor) {
1812 int modes[] = {
1813 CFI_CMDSET_AMD_STANDARD,
1814 CFI_CMDSET_INTEL_STANDARD
1815 };
1816 int i;
7e5b9b47 1817
31bf0f57 1818 for (i = 0; i < ARRAY_SIZE(modes); i++) {
be60a902 1819 info->vendor = modes[i];
09ce9921
BB		 1820 info->start[0] =
1821 (ulong)map_physmem(base,
e1fb6d0d 1822 info->portwidth,
09ce9921 1823 MAP_NOCACHE);
88ecd8bf 1824 if (info->portwidth == FLASH_CFI_8BIT &&
c0350fbf 1825 info->interface == FLASH_CFI_X8X16) {
be60a902
HS		 1826 info->addr_unlock1 = 0x2AAA;
1827 info->addr_unlock2 = 0x5555;
1828 } else {
1829 info->addr_unlock1 = 0x5555;
1830 info->addr_unlock2 = 0x2AAA;
1831 }
1832 flash_read_jedec_ids(info);
1833 debug("JEDEC PROBE: ID %x %x %x\n",
c0350fbf
MS		 1834 info->manufacturer_id,
1835 info->device_id,
1836 info->device_id2);
09ce9921 1837 if (jedec_flash_match(info, info->start[0]))
be60a902 1838 break;
9860137f
MS		 1839
1840 unmap_physmem((void *)info->start[0],
1841 info->portwidth);
be60a902
HS		 1842 }
1843 }
1844
b168386b 1845 switch (info->vendor) {
9c048b52 1846 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1847 case CFI_CMDSET_INTEL_STANDARD:
1848 case CFI_CMDSET_INTEL_EXTENDED:
1849 info->cmd_reset = FLASH_CMD_RESET;
1850 break;
1851 case CFI_CMDSET_AMD_STANDARD:
1852 case CFI_CMDSET_AMD_EXTENDED:
1853 case CFI_CMDSET_AMD_LEGACY:
1854 info->cmd_reset = AMD_CMD_RESET;
1855 break;
1856 }
1857 info->flash_id = FLASH_MAN_CFI;
1858 return 1;
1859 }
1860 return 0; /* use CFI */
1861}
1862#else
09ce9921 1863static inline int flash_detect_legacy(phys_addr_t base, int banknum)
be60a902
HS		 1864{
1865 return 0; /* use CFI */
1866}
1867#endif
1868
1869/*-----------------------------------------------------------------------
1870 * detect if flash is compatible with the Common Flash Interface (CFI)
1871 * http://www.jedec.org/download/search/jesd68.pdf
1872 */
c0350fbf
MS		 1873static void flash_read_cfi(flash_info_t *info, void *buf, unsigned int start,
1874 size_t len)
e23741f4
HS		 1875{
1876 u8 *p = buf;
1877 unsigned int i;
1878
1879 for (i = 0; i < len; i++)
e303be2d 1880 p[i] = flash_read_uchar(info, start + i);
e23741f4
HS		 1881}
1882
11dc4010 1883static void __flash_cmd_reset(flash_info_t *info)
fa36ae79
SR		 1884{
1885 /*
1886 * We do not yet know what kind of commandset to use, so we issue
1887 * the reset command in both Intel and AMD variants, in the hope
1888 * that AMD flash roms ignore the Intel command.
1889 */
1890 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1891 udelay(1);
fa36ae79
SR		 1892 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1893}
7223a8cb 1894
fa36ae79 1895void flash_cmd_reset(flash_info_t *info)
640f4e35 1896 __attribute__((weak, alias("__flash_cmd_reset")));
fa36ae79 1897
ca2b07a8 1898static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
be60a902
HS		 1899{
1900 int cfi_offset;
1901
e303be2d
SR		 1902 /* Issue FLASH reset command */
1903 flash_cmd_reset(info);
1904
31bf0f57 1905 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi);
be60a902 1906 cfi_offset++) {
188a5565 1907 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset],
c0350fbf 1908 FLASH_CMD_CFI);
88ecd8bf 1909 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
ddcf0540
MS		 1910 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
1911 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
c0350fbf
MS		 1912 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1913 sizeof(struct cfi_qry));
e23741f4 1914 info->interface = le16_to_cpu(qry->interface_desc);
53879b17
JT		 1915 /* Some flash chips can support multiple bus widths.
1916 * In this case, override the interface width and
1917 * limit it to the port width.
1918 */
1919 if ((info->interface == FLASH_CFI_X8X16) &&
1920 (info->portwidth == FLASH_CFI_8BIT)) {
1921 debug("Overriding 16-bit interface width to"
1922 " 8-bit port width\n");
1923 info->interface = FLASH_CFI_X8;
1924 } else if ((info->interface == FLASH_CFI_X16X32) &&
1925 (info->portwidth == FLASH_CFI_16BIT)) {
1926 debug("Overriding 16-bit interface width to"
1927 " 16-bit port width\n");
1928 info->interface = FLASH_CFI_X16;
1929 }
e303be2d 1930
be60a902 1931 info->cfi_offset = flash_offset_cfi[cfi_offset];
188a5565 1932 debug("device interface is %d\n",
c0350fbf 1933 info->interface);
53879b17
JT		 1934 debug("found port %d chip %d chip_lsb %d ",
1935 info->portwidth, info->chipwidth, info->chip_lsb);
188a5565 1936 debug("port %d bits chip %d bits\n",
c0350fbf
MS		 1937 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1938 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
be60a902
HS		 1939
1940 /* calculate command offsets as in the Linux driver */
e303be2d
SR		 1941 info->addr_unlock1 = 0x555;
1942 info->addr_unlock2 = 0x2aa;
7e5b9b47
HS		 1943
1944 /*
1945 * modify the unlock address if we are
1946 * in compatibility mode
1947 */
b168386b 1948 if (/* x8/x16 in x8 mode */
4f89da49
MS		 1949 (info->chipwidth == FLASH_CFI_BY8 &&
1950 info->interface == FLASH_CFI_X8X16) ||
b168386b 1951 /* x16/x32 in x16 mode */
4f89da49 1952 (info->chipwidth == FLASH_CFI_BY16 &&
0cec0a12 1953 info->interface == FLASH_CFI_X16X32)) {
7e5b9b47
HS		 1954 info->addr_unlock1 = 0xaaa;
1955 info->addr_unlock2 = 0x555;
1956 }
1957
1958 info->name = "CFI conformant";
1959 return 1;
1960 }
1961 }
1962
1963 return 0;
1964}
1965
ca2b07a8 1966static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
7e5b9b47 1967{
188a5565 1968 debug("flash detect cfi\n");
bf9e3b38 1969
6d0f6bcf 1970 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1971 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1972 for (info->chipwidth = FLASH_CFI_BY8;
1973 info->chipwidth <= info->portwidth;
53879b17
JT		 1974 info->chipwidth <<= 1) {
1975 /*
1976 * First, try detection without shifting the addresses
1977 * for 8bit devices (16bit wide connection)
1978 */
1979 info->chip_lsb = 0;
1980 if (__flash_detect_cfi(info, qry))
1981 return 1;
1982
1983 /*
1984 * Not detected, so let's try with shifting
1985 * for 8bit devices
1986 */
1987 info->chip_lsb = 1;
e303be2d 1988 if (__flash_detect_cfi(info, qry))
7e5b9b47 1989 return 1;
53879b17 1990 }
5653fc33 1991 }
188a5565 1992 debug("not found\n");
5653fc33
WD		 1993 return 0;
1994}
bf9e3b38 1995
467bcee1
HS		 1996/*
1997 * Manufacturer-specific quirks. Add workarounds for geometry
1998 * reversal, etc. here.
1999 */
2000static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
2001{
2002 /* check if flash geometry needs reversal */
2003 if (qry->num_erase_regions > 1) {
2004 /* reverse geometry if top boot part */
2005 if (info->cfi_version < 0x3131) {
2006 /* CFI < 1.1, try to guess from device id */
2007 if ((info->device_id & 0x80) != 0)
2008 cfi_reverse_geometry(qry);
e303be2d 2009 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
467bcee1
HS		 2010 /* CFI >= 1.1, deduct from top/bottom flag */
2011 /* note: ext_addr is valid since cfi_version > 0 */
2012 cfi_reverse_geometry(qry);
2013 }
2014 }
2015}
2016
2017static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
2018{
2019 int reverse_geometry = 0;
2020
2021 /* Check the "top boot" bit in the PRI */
2022 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
2023 reverse_geometry = 1;
2024
2025 /* AT49BV6416(T) list the erase regions in the wrong order.
2026 * However, the device ID is identical with the non-broken
cb82a532 2027 * AT49BV642D they differ in the high byte.
467bcee1 2028 */
467bcee1
HS		 2029 if (info->device_id == 0xd6 || info->device_id == 0xd2)
2030 reverse_geometry = !reverse_geometry;
467bcee1
HS		 2031
2032 if (reverse_geometry)
2033 cfi_reverse_geometry(qry);
2034}
2035
e8eac437
RR		 2036static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
2037{
2038 /* check if flash geometry needs reversal */
2039 if (qry->num_erase_regions > 1) {
2040 /* reverse geometry if top boot part */
2041 if (info->cfi_version < 0x3131) {
6a011ce8
MF		 2042 /* CFI < 1.1, guess by device id */
2043 if (info->device_id == 0x22CA || /* M29W320DT */
2044 info->device_id == 0x2256 || /* M29W320ET */
2045 info->device_id == 0x22D7) { /* M29W800DT */
e8eac437
RR		 2046 cfi_reverse_geometry(qry);
2047 }
4c2105cb
MF		 2048 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
2049 /* CFI >= 1.1, deduct from top/bottom flag */
2050 /* note: ext_addr is valid since cfi_version > 0 */
2051 cfi_reverse_geometry(qry);
e8eac437
RR		 2052 }
2053 }
2054}
2055
07b2c5c0
AD		 2056static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry)
2057{
2058 /*
2059 * SST, for many recent nor parallel flashes, says they are
2060 * CFI-conformant. This is not true, since qry struct.
2061 * reports a std. AMD command set (0x0002), while SST allows to
2062 * erase two different sector sizes for the same memory.
2063 * 64KB sector (SST call it block) needs 0x30 to be erased.
2064 * 4KB sector (SST call it sector) needs 0x50 to be erased.
2065 * Since CFI query detect the 4KB number of sectors, users expects
2066 * a sector granularity of 4KB, and it is here set.
2067 */
2068 if (info->device_id == 0x5D23 || /* SST39VF3201B */
2069 info->device_id == 0x5C23) { /* SST39VF3202B */
2070 /* set sector granularity to 4KB */
640f4e35 2071 info->cmd_erase_sector = 0x50;
07b2c5c0
AD		 2072 }
2073}
2074
c502321c
JT		 2075static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry)
2076{
2077 /*
2078 * The M29EW devices seem to report the CFI information wrong
2079 * when it's in 8 bit mode.
2080 * There's an app note from Numonyx on this issue.
2081 * So adjust the buffer size for M29EW while operating in 8-bit mode
2082 */
4f89da49 2083 if (qry->max_buf_write_size > 0x8 &&
c0350fbf
MS		 2084 info->device_id == 0x7E &&
2085 (info->device_id2 == 0x2201 ||
2086 info->device_id2 == 0x2301 ||
2087 info->device_id2 == 0x2801 ||
2088 info->device_id2 == 0x4801)) {
876c52f3
MS		 2089 debug("Adjusted buffer size on Numonyx flash");
2090 debug(" M29EW family in 8 bit mode\n");
c502321c
JT		 2091 qry->max_buf_write_size = 0x8;
2092 }
2093}
2094
5653fc33
WD		 2095/*
2096 * The following code cannot be run from FLASH!
2097 *
2098 */
188a5565 2099ulong flash_get_size(phys_addr_t base, int banknum)
5653fc33 2100{
bf9e3b38 2101 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 2102 int i, j;
2103 flash_sect_t sect_cnt;
09ce9921 2104 phys_addr_t sector;
5653fc33
WD		 2105 unsigned long tmp;
2106 int size_ratio;
2107 uchar num_erase_regions;
bf9e3b38
WD		 2108 int erase_region_size;
2109 int erase_region_count;
e23741f4 2110 struct cfi_qry qry;
34bbb8fb 2111 unsigned long max_size;
260421a2 2112
f979690e
KG		 2113 memset(&qry, 0, sizeof(qry));
2114
260421a2
SR		 2115 info->ext_addr = 0;
2116 info->cfi_version = 0;
6d0f6bcf 2117#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR		 2118 info->legacy_unlock = 0;
2119#endif
5653fc33 2120
09ce9921 2121 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
5653fc33 2122
188a5565 2123 if (flash_detect_cfi(info, &qry)) {
4f89da49
MS		 2124 info->vendor = le16_to_cpu(get_unaligned(&qry.p_id));
2125 info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr));
e23741f4
HS		 2126 num_erase_regions = qry.num_erase_regions;
2127
260421a2 2128 if (info->ext_addr) {
640f4e35 2129 info->cfi_version = (ushort)flash_read_uchar(info,
e303be2d 2130 info->ext_addr + 3) << 8;
640f4e35 2131 info->cfi_version |= (ushort)flash_read_uchar(info,
e303be2d 2132 info->ext_addr + 4);
260421a2 2133 }
0ddf06dd 2134
bf9e3b38 2135#ifdef DEBUG
188a5565 2136 flash_printqry(&qry);
bf9e3b38 2137#endif
0ddf06dd 2138
bf9e3b38 2139 switch (info->vendor) {
9c048b52 2140 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 2141 case CFI_CMDSET_INTEL_STANDARD:
2142 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 2143 cmdset_intel_init(info, &qry);
5653fc33
WD		 2144 break;
2145 case CFI_CMDSET_AMD_STANDARD:
2146 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 2147 cmdset_amd_init(info, &qry);
5653fc33 2148 break;
0ddf06dd
HS		 2149 default:
2150 printf("CFI: Unknown command set 0x%x\n",
c0350fbf 2151 info->vendor);
0ddf06dd
HS		 2152 /*
2153 * Unfortunately, this means we don't know how
2154 * to get the chip back to Read mode. Might
2155 * as well try an Intel-style reset...
2156 */
2157 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
2158 return 0;
5653fc33 2159 }
cd37d9e6 2160
467bcee1
HS		 2161 /* Do manufacturer-specific fixups */
2162 switch (info->manufacturer_id) {
2c9f48af
MS		 2163 case 0x0001: /* AMD */
2164 case 0x0037: /* AMIC */
467bcee1
HS		 2165 flash_fixup_amd(info, &qry);
2166 break;
2167 case 0x001f:
2168 flash_fixup_atmel(info, &qry);
2169 break;
e8eac437
RR		 2170 case 0x0020:
2171 flash_fixup_stm(info, &qry);
2172 break;
07b2c5c0
AD		 2173 case 0x00bf: /* SST */
2174 flash_fixup_sst(info, &qry);
2175 break;
c502321c
JT		 2176 case 0x0089: /* Numonyx */
2177 flash_fixup_num(info, &qry);
2178 break;
467bcee1
HS		 2179 }
2180
188a5565
MS		 2181 debug("manufacturer is %d\n", info->vendor);
2182 debug("manufacturer id is 0x%x\n", info->manufacturer_id);
2183 debug("device id is 0x%x\n", info->device_id);
2184 debug("device id2 is 0x%x\n", info->device_id2);
2185 debug("cfi version is 0x%04x\n", info->cfi_version);
260421a2 2186
5653fc33 2187 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38 2188 /* if the chip is x8/x16 reduce the ratio by half */
4f89da49 2189 if (info->interface == FLASH_CFI_X8X16 &&
c0350fbf 2190 info->chipwidth == FLASH_CFI_BY8) {
bf9e3b38
WD		 2191 size_ratio >>= 1;
2192 }
188a5565 2193 debug("size_ratio %d port %d bits chip %d bits\n",
c0350fbf
MS		 2194 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
2195 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
ec50a8e3
IY		 2196 info->size = 1 << qry.dev_size;
2197 /* multiply the size by the number of chips */
2198 info->size *= size_ratio;
34bbb8fb 2199 max_size = cfi_flash_bank_size(banknum);
43bacbe6
NS		 2200#ifdef CONFIG_CFI_FLASH
2201 if (max_size)
2202 max_size = min((unsigned long)info->addr_size, max_size);
2203 else
2204 max_size = info->addr_size;
2205#endif
4f89da49 2206 if (max_size && info->size > max_size) {
ec50a8e3
IY		 2207 debug("[truncated from %ldMiB]", info->size >> 20);
2208 info->size = max_size;
2209 }
188a5565 2210 debug("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 2211 sect_cnt = 0;
2212 sector = base;
bf9e3b38
WD		 2213 for (i = 0; i < num_erase_regions; i++) {
2214 if (i > NUM_ERASE_REGIONS) {
188a5565 2215 printf("%d erase regions found, only %d used\n",
c0350fbf 2216 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 2217 break;
2218 }
e23741f4 2219
aedadf10 2220 tmp = le32_to_cpu(get_unaligned(
4f89da49 2221 &qry.erase_region_info[i]));
0ddf06dd 2222 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 2223
2224 erase_region_count = (tmp & 0xffff) + 1;
2225 tmp >>= 16;
bf9e3b38
WD		 2226 erase_region_size =
2227 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
ddcf0540
MS		 2228 debug("erase_region_count = %d ", erase_region_count);
2229 debug("erase_region_size = %d\n", erase_region_size);
bf9e3b38 2230 for (j = 0; j < erase_region_count; j++) {
ec50a8e3
IY		 2231 if (sector - base >= info->size)
2232 break;
6d0f6bcf 2233 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS		 2234 printf("ERROR: too many flash sectors\n");
2235 break;
2236 }
09ce9921
BB		 2237 info->start[sect_cnt] =
2238 (ulong)map_physmem(sector,
2239 info->portwidth,
2240 MAP_NOCACHE);
5653fc33 2241 sector += (erase_region_size * size_ratio);
a1191902
WD		 2242
2243 /*
7e5b9b47
HS		 2244 * Only read protection status from
2245 * supported devices (intel...)
a1191902
WD		 2246 */
2247 switch (info->vendor) {
9c048b52 2248 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 2249 case CFI_CMDSET_INTEL_EXTENDED:
2250 case CFI_CMDSET_INTEL_STANDARD:
df4e813b
SR		 2251 /*
2252 * Set flash to read-id mode. Otherwise
2253 * reading protected status is not
2254 * guaranteed.
2255 */
2256 flash_write_cmd(info, sect_cnt, 0,
2257 FLASH_CMD_READ_ID);
a1191902 2258 info->protect[sect_cnt] =
188a5565 2259 flash_isset(info, sect_cnt,
c0350fbf
MS		 2260 FLASH_OFFSET_PROTECT,
2261 FLASH_STATUS_PROTECT);
edc498c6
VK		 2262 flash_write_cmd(info, sect_cnt, 0,
2263 FLASH_CMD_RESET);
a1191902 2264 break;
03deff43
SR		 2265 case CFI_CMDSET_AMD_EXTENDED:
2266 case CFI_CMDSET_AMD_STANDARD:
ac6b9115 2267 if (!info->legacy_unlock) {
03deff43
SR		 2268 /* default: not protected */
2269 info->protect[sect_cnt] = 0;
2270 break;
2271 }
2272
2273 /* Read protection (PPB) from sector */
2274 flash_write_cmd(info, 0, 0,
2275 info->cmd_reset);
2276 flash_unlock_seq(info, 0);
2277 flash_write_cmd(info, 0,
2278 info->addr_unlock1,
94657482 2279 AMD_CMD_SET_PPB_ENTRY);
03deff43 2280 info->protect[sect_cnt] =
94657482
MV		 2281 !flash_isset(info, sect_cnt,
2282 0, 0x01);
2283 flash_write_cmd(info, 0, 0,
2284 info->cmd_reset);
03deff43 2285 break;
a1191902 2286 default:
7e5b9b47
HS		 2287 /* default: not protected */
2288 info->protect[sect_cnt] = 0;
a1191902
WD		 2289 }
2290
5653fc33
WD		 2291 sect_cnt++;
2292 }
2293 }
2294
2295 info->sector_count = sect_cnt;
e23741f4
HS		 2296 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
2297 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 2298 info->erase_blk_tout = tmp *
e23741f4
HS		 2299 (1 << qry.block_erase_timeout_max);
2300 tmp = (1 << qry.buf_write_timeout_typ) *
2301 (1 << qry.buf_write_timeout_max);
2302
7e5b9b47 2303 /* round up when converting to ms */
e23741f4
HS		 2304 info->buffer_write_tout = (tmp + 999) / 1000;
2305 tmp = (1 << qry.word_write_timeout_typ) *
2306 (1 << qry.word_write_timeout_max);
7e5b9b47 2307 /* round up when converting to ms */
e23741f4 2308 info->write_tout = (tmp + 999) / 1000;
5653fc33 2309 info->flash_id = FLASH_MAN_CFI;
4f89da49
MS		 2310 if (info->interface == FLASH_CFI_X8X16 &&
2311 info->chipwidth == FLASH_CFI_BY8) {
7e5b9b47
HS		 2312 /* XXX - Need to test on x8/x16 in parallel. */
2313 info->portwidth >>= 1;
855a496f 2314 }
2215987e 2315
188a5565 2316 flash_write_cmd(info, 0, 0, info->cmd_reset);
5653fc33
WD		 2317 }
2318
bf9e3b38 2319 return (info->size);
5653fc33
WD		 2320}
2321
4ffeab2c 2322#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef
PZ		 2323void flash_set_verbose(uint v)
2324{
2325 flash_verbose = v;
2326}
4ffeab2c 2327#endif
6ea808ef 2328
6f726f95
SR		 2329static void cfi_flash_set_config_reg(u32 base, u16 val)
2330{
2331#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
2332 /*
2333 * Only set this config register if really defined
2334 * to a valid value (0xffff is invalid)
2335 */
2336 if (val == 0xffff)
2337 return;
2338
2339 /*
2340 * Set configuration register. Data is "encrypted" in the 16 lower
2341 * address bits.
2342 */
2343 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
2344 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
2345
2346 /*
2347 * Finally issue reset-command to bring device back to
2348 * read-array mode
2349 */
2350 flash_write16(FLASH_CMD_RESET, (void *)base);
2351#endif
2352}
2353
5653fc33
WD		 2354/*-----------------------------------------------------------------------
2355 */
6ee1416e 2356
236c49a1 2357static void flash_protect_default(void)
6ee1416e 2358{
2c51983b
PT		 2359#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2360 int i;
2361 struct apl_s {
2362 ulong start;
2363 ulong size;
2364 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
2365#endif
2366
6ee1416e 2367 /* Monitor protection ON by default */
d75eacf9 2368#if defined(CONFIG_SYS_MONITOR_BASE) && \
65cc0e2a 2369 (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
6ee1416e
HS		 2370 (!defined(CONFIG_MONITOR_IS_IN_RAM))
2371 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2372 CONFIG_SYS_MONITOR_BASE,
2373 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2374 flash_get_info(CONFIG_SYS_MONITOR_BASE));
6ee1416e
HS		 2375#endif
2376
2377 /* Environment protection ON by default */
2378#ifdef CONFIG_ENV_IS_IN_FLASH
2379 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2380 CONFIG_ENV_ADDR,
2381 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2382 flash_get_info(CONFIG_ENV_ADDR));
6ee1416e
HS		 2383#endif
2384
2385 /* Redundant environment protection ON by default */
2386#ifdef CONFIG_ENV_ADDR_REDUND
2387 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2388 CONFIG_ENV_ADDR_REDUND,
2389 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
2390 flash_get_info(CONFIG_ENV_ADDR_REDUND));
6ee1416e
HS		 2391#endif
2392
2393#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
31bf0f57 2394 for (i = 0; i < ARRAY_SIZE(apl); i++) {
31d34143 2395 debug("autoprotecting from %08lx to %08lx\n",
6ee1416e
HS		 2396 apl[i].start, apl[i].start + apl[i].size - 1);
2397 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2398 apl[i].start,
2399 apl[i].start + apl[i].size - 1,
2400 flash_get_info(apl[i].start));
6ee1416e
HS		 2401 }
2402#endif
2403}
2404
188a5565 2405unsigned long flash_init(void)
5653fc33 2406{
be60a902
HS		 2407 unsigned long size = 0;
2408 int i;
5653fc33 2409
6d0f6bcf 2410#ifdef CONFIG_SYS_FLASH_PROTECTION
3a3baf3e
ES		 2411 /* read environment from EEPROM */
2412 char s[64];
7223a8cb 2413
00caae6d 2414 env_get_f("unlock", s, sizeof(s));
81b20ccc 2415#endif
5653fc33 2416
f1056910
TC		 2417#ifdef CONFIG_CFI_FLASH /* for driver model */
2418 cfi_flash_init_dm();
2419#endif
2420
be60a902 2421 /* Init: no FLASHes known */
98150e7e 2422 for (i = 0; i < CFI_FLASH_BANKS; ++i) {
be60a902 2423 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 2424
6f726f95
SR		 2425 /* Optionally write flash configuration register */
2426 cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
2427 cfi_flash_config_reg(i));
2428
b00e19cc 2429 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
34bbb8fb 2430 flash_get_size(cfi_flash_bank_addr(i), i);
be60a902
HS		 2431 size += flash_info[i].size;
2432 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 2433#ifndef CONFIG_SYS_FLASH_QUIET_TEST
876c52f3
MS		 2434 printf("## Unknown flash on Bank %d ", i + 1);
2435 printf("- Size = 0x%08lx = %ld MB\n",
c0350fbf
MS		 2436 flash_info[i].size,
2437 flash_info[i].size >> 20);
6d0f6bcf 2438#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 2439 }
6d0f6bcf 2440#ifdef CONFIG_SYS_FLASH_PROTECTION
c15df21f 2441 else if (strcmp(s, "yes") == 0) {
be60a902
HS		 2442 /*
2443 * Only the U-Boot image and it's environment
2444 * is protected, all other sectors are
2445 * unprotected (unlocked) if flash hardware
6d0f6bcf 2446 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS		 2447 * and the environment variable "unlock" is
2448 * set to "yes".
2449 */
2450 if (flash_info[i].legacy_unlock) {
2451 int k;
5653fc33 2452
be60a902
HS		 2453 /*
2454 * Disable legacy_unlock temporarily,
2455 * since flash_real_protect would
2456 * relock all other sectors again
2457 * otherwise.
2458 */
2459 flash_info[i].legacy_unlock = 0;
5653fc33 2460
be60a902
HS		 2461 /*
2462 * Legacy unlocking (e.g. Intel J3) ->
2463 * unlock only one sector. This will
2464 * unlock all sectors.
2465 */
188a5565 2466 flash_real_protect(&flash_info[i], 0, 0);
5653fc33 2467
be60a902 2468 flash_info[i].legacy_unlock = 1;
5653fc33 2469
be60a902
HS		 2470 /*
2471 * Manually mark other sectors as
2472 * unlocked (unprotected)
2473 */
2474 for (k = 1; k < flash_info[i].sector_count; k++)
2475 flash_info[i].protect[k] = 0;
2476 } else {
2477 /*
2478 * No legancy unlocking -> unlock all sectors
2479 */
188a5565 2480 flash_protect(FLAG_PROTECT_CLEAR,
c0350fbf
MS		 2481 flash_info[i].start[0],
2482 flash_info[i].start[0]
2483 + flash_info[i].size - 1,
2484 &flash_info[i]);
79b4cda0 2485 }
79b4cda0 2486 }
6d0f6bcf 2487#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2488 }
79b4cda0 2489
6ee1416e 2490 flash_protect_default();
91809ed5
PZ		 2491#ifdef CONFIG_FLASH_CFI_MTD
2492 cfi_mtd_init();
2493#endif
2494
be60a902 2495 return (size);
5653fc33 2496}
f1056910
TC		 2497
2498#ifdef CONFIG_CFI_FLASH /* for driver model */
2499static int cfi_flash_probe(struct udevice *dev)
2500{
492b9917 2501 fdt_addr_t addr;
43bacbe6 2502 fdt_size_t size;
492b9917 2503 int idx;
f1056910 2504
492b9917 2505 for (idx = 0; idx < CFI_MAX_FLASH_BANKS; idx++) {
43bacbe6 2506 addr = dev_read_addr_size_index(dev, idx, &size);
492b9917
AP		 2507 if (addr == FDT_ADDR_T_NONE)
2508 break;
8bfeb33c 2509
1ec0a37e
MV		 2510 flash_info[cfi_flash_num_flash_banks].dev = dev;
2511 flash_info[cfi_flash_num_flash_banks].base = addr;
43bacbe6 2512 flash_info[cfi_flash_num_flash_banks].addr_size = size;
1ec0a37e 2513 cfi_flash_num_flash_banks++;
f1056910 2514 }
1ec0a37e 2515 gd->bd->bi_flashstart = flash_info[0].base;
f1056910
TC		 2516
2517 return 0;
2518}
2519
2520static const struct udevice_id cfi_flash_ids[] = {
2521 { .compatible = "cfi-flash" },
2522 { .compatible = "jedec-flash" },
2523 {}
2524};
2525
2526U_BOOT_DRIVER(cfi_flash) = {
2527 .name = "cfi_flash",
2528 .id = UCLASS_MTD,
2529 .of_match = cfi_flash_ids,
2530 .probe = cfi_flash_probe,
2531};
2532#endif /* CONFIG_CFI_FLASH */
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