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Merge branch 'master' of git://git.denx.de/u-boot-arm
[J-u-boot.git] / drivers / mtd / cfi_flash.c
CommitLineData
5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD		 3 * Brad Kemp, Seranoa Networks, [email protected]
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <[email protected]>
5653fc33 7 *
bf9e3b38
WD		 8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR		 10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <[email protected]>
bf9e3b38 13 *
5653fc33
WD		 14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD		 32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 35/* #define DEBUG */
36
5653fc33
WD		 37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
fa36ae79 42#include <mtd/cfi_flash.h>
a9f5faba 43#include <watchdog.h>
028ab6b5 44
5653fc33 45/*
7e5b9b47
HS		 46 * This file implements a Common Flash Interface (CFI) driver for
47 * U-Boot.
48 *
49 * The width of the port and the width of the chips are determined at
50 * initialization. These widths are used to calculate the address for
51 * access CFI data structures.
5653fc33
WD		 52 *
53 * References
54 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
55 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
56 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
57 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 58 * AMD CFI Specification, Release 2.0 December 1, 2001
59 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
60 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 61 *
6d0f6bcf 62 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 63 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 64 */
65
7e5b9b47 66static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
4ffeab2c 67#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef 68static uint flash_verbose = 1;
4ffeab2c
MF		 69#else
70#define flash_verbose 1
71#endif
92eb729b 72
2a112b23
WD		 73flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
74
79b4cda0
SR		 75/*
76 * Check if chip width is defined. If not, start detecting with 8bit.
77 */
6d0f6bcf
JCPV		 78#ifndef CONFIG_SYS_FLASH_CFI_WIDTH
79#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
79b4cda0
SR		 80#endif
81
6f726f95
SR		 82/*
83 * 0xffff is an undefined value for the configuration register. When
84 * this value is returned, the configuration register shall not be
85 * written at all (default mode).
86 */
87static u16 cfi_flash_config_reg(int i)
88{
89#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
90 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
91#else
92 return 0xffff;
93#endif
94}
95
ca5def3f
SR		 96#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
97int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
98#endif
99
b00e19cc
SR		 100static phys_addr_t __cfi_flash_bank_addr(int i)
101{
102 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
103}
104phys_addr_t cfi_flash_bank_addr(int i)
105 __attribute__((weak, alias("__cfi_flash_bank_addr")));
106
ec50a8e3
IY		 107static unsigned long __cfi_flash_bank_size(int i)
108{
109#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
110 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
111#else
112 return 0;
113#endif
114}
115unsigned long cfi_flash_bank_size(int i)
116 __attribute__((weak, alias("__cfi_flash_bank_size")));
117
45aa5a7f 118static void __flash_write8(u8 value, void *addr)
cdbaefb5
HS		 119{
120 __raw_writeb(value, addr);
121}
122
45aa5a7f 123static void __flash_write16(u16 value, void *addr)
cdbaefb5
HS		 124{
125 __raw_writew(value, addr);
126}
127
45aa5a7f 128static void __flash_write32(u32 value, void *addr)
cdbaefb5
HS		 129{
130 __raw_writel(value, addr);
131}
132
45aa5a7f 133static void __flash_write64(u64 value, void *addr)
cdbaefb5
HS		 134{
135 /* No architectures currently implement __raw_writeq() */
136 *(volatile u64 *)addr = value;
137}
138
45aa5a7f 139static u8 __flash_read8(void *addr)
cdbaefb5
HS		 140{
141 return __raw_readb(addr);
142}
143
45aa5a7f 144static u16 __flash_read16(void *addr)
cdbaefb5
HS		 145{
146 return __raw_readw(addr);
147}
148
45aa5a7f 149static u32 __flash_read32(void *addr)
cdbaefb5
HS		 150{
151 return __raw_readl(addr);
152}
153
97bf85d7 154static u64 __flash_read64(void *addr)
cdbaefb5
HS		 155{
156 /* No architectures currently implement __raw_readq() */
157 return *(volatile u64 *)addr;
158}
159
45aa5a7f
SR		 160#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
161void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8")));
162void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16")));
163void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32")));
164void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64")));
165u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8")));
166u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16")));
167u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32")));
97bf85d7 168u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
45aa5a7f
SR		 169#else
170#define flash_write8 __flash_write8
171#define flash_write16 __flash_write16
172#define flash_write32 __flash_write32
173#define flash_write64 __flash_write64
174#define flash_read8 __flash_read8
175#define flash_read16 __flash_read16
176#define flash_read32 __flash_read32
177#define flash_read64 __flash_read64
178#endif
97bf85d7 179
5653fc33 180/*-----------------------------------------------------------------------
5653fc33 181 */
6d0f6bcf 182#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
4f975678 183flash_info_t *flash_get_info(ulong base)
be60a902
HS		 184{
185 int i;
cba34aaf 186 flash_info_t *info = NULL;
5653fc33 187
6d0f6bcf 188 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
be60a902
HS		 189 info = & flash_info[i];
190 if (info->size && info->start[0] <= base &&
191 base <= info->start[0] + info->size - 1)
192 break;
193 }
5653fc33 194
cba34aaf 195 return info;
be60a902 196}
5653fc33
WD		 197#endif
198
12d30aa7
HS		 199unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
200{
201 if (sect != (info->sector_count - 1))
202 return info->start[sect + 1] - info->start[sect];
203 else
204 return info->start[0] + info->size - info->start[sect];
205}
206
bf9e3b38
WD		 207/*-----------------------------------------------------------------------
208 * create an address based on the offset and the port width
209 */
12d30aa7
HS		 210static inline void *
211flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 212{
12d30aa7
HS		 213 unsigned int byte_offset = offset * info->portwidth;
214
09ce9921 215 return (void *)(info->start[sect] + byte_offset);
12d30aa7
HS		 216}
217
218static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
219 unsigned int offset, void *addr)
220{
bf9e3b38
WD		 221}
222
be60a902
HS		 223/*-----------------------------------------------------------------------
224 * make a proper sized command based on the port and chip widths
225 */
7288f972 226static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 227{
228 int i;
93c56f21
VL		 229 int cword_offset;
230 int cp_offset;
6d0f6bcf 231#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS		 232 u32 cmd_le = cpu_to_le32(cmd);
233#endif
93c56f21 234 uchar val;
be60a902
HS		 235 uchar *cp = (uchar *) cmdbuf;
236
93c56f21
VL		 237 for (i = info->portwidth; i > 0; i--){
238 cword_offset = (info->portwidth-i)%info->chipwidth;
6d0f6bcf 239#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
93c56f21 240 cp_offset = info->portwidth - i;
340ccb26 241 val = *((uchar*)&cmd_le + cword_offset);
be60a902 242#else
93c56f21 243 cp_offset = i - 1;
7288f972 244 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 245#endif
7288f972 246 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 247 }
be60a902
HS		 248}
249
5653fc33 250#ifdef DEBUG
bf9e3b38
WD		 251/*-----------------------------------------------------------------------
252 * Debug support
253 */
3055793b 254static void print_longlong (char *str, unsigned long long data)
5653fc33
WD		 255{
256 int i;
257 char *cp;
bf9e3b38 258
657f2062 259 cp = (char *) &data;
bf9e3b38
WD		 260 for (i = 0; i < 8; i++)
261 sprintf (&str[i * 2], "%2.2x", *cp++);
262}
be60a902 263
e23741f4 264static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 265{
e23741f4 266 u8 *p = (u8 *)qry;
bf9e3b38
WD		 267 int x, y;
268
e23741f4
HS		 269 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
270 debug("%02x : ", x);
271 for (y = 0; y < 16; y++)
272 debug("%2.2x ", p[x + y]);
273 debug(" ");
bf9e3b38 274 for (y = 0; y < 16; y++) {
e23741f4
HS		 275 unsigned char c = p[x + y];
276 if (c >= 0x20 && c <= 0x7e)
277 debug("%c", c);
278 else
279 debug(".");
bf9e3b38 280 }
e23741f4 281 debug("\n");
bf9e3b38 282 }
5653fc33
WD		 283}
284#endif
285
286
5653fc33
WD		 287/*-----------------------------------------------------------------------
288 * read a character at a port width address
289 */
3055793b 290static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD		 291{
292 uchar *cp;
12d30aa7 293 uchar retval;
bf9e3b38 294
12d30aa7 295 cp = flash_map (info, 0, offset);
6d0f6bcf 296#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 297 retval = flash_read8(cp);
bf9e3b38 298#else
12d30aa7 299 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 300#endif
12d30aa7
HS		 301 flash_unmap (info, 0, offset, cp);
302 return retval;
5653fc33
WD		 303}
304
90447ecb
TK		 305/*-----------------------------------------------------------------------
306 * read a word at a port width address, assume 16bit bus
307 */
308static inline ushort flash_read_word (flash_info_t * info, uint offset)
309{
310 ushort *addr, retval;
311
312 addr = flash_map (info, 0, offset);
313 retval = flash_read16 (addr);
314 flash_unmap (info, 0, offset, addr);
315 return retval;
316}
317
318
5653fc33 319/*-----------------------------------------------------------------------
260421a2 320 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 321 * port size word. Swap for ppc format.
322 */
3055793b
HS		 323static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
324 uint offset)
5653fc33 325{
bf9e3b38
WD		 326 uchar *addr;
327 ulong retval;
328
329#ifdef DEBUG
330 int x;
331#endif
12d30aa7 332 addr = flash_map (info, sect, offset);
5653fc33 333
bf9e3b38
WD		 334#ifdef DEBUG
335 debug ("long addr is at %p info->portwidth = %d\n", addr,
336 info->portwidth);
337 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 338 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD		 339 }
340#endif
6d0f6bcf 341#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS		 342 retval = ((flash_read8(addr) << 16) |
343 (flash_read8(addr + info->portwidth) << 24) |
344 (flash_read8(addr + 2 * info->portwidth)) |
345 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 346#else
12d30aa7
HS		 347 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
348 (flash_read8(addr + info->portwidth - 1) << 16) |
349 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
350 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 351#endif
12d30aa7
HS		 352 flash_unmap(info, sect, offset, addr);
353
bf9e3b38 354 return retval;
5653fc33
WD		 355}
356
be60a902
HS		 357/*
358 * Write a proper sized command to the correct address
81b20ccc 359 */
fa36ae79
SR		 360void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
361 uint offset, u32 cmd)
81b20ccc 362{
7e5b9b47 363
cdbaefb5 364 void *addr;
be60a902 365 cfiword_t cword;
81b20ccc 366
12d30aa7 367 addr = flash_map (info, sect, offset);
be60a902
HS		 368 flash_make_cmd (info, cmd, &cword);
369 switch (info->portwidth) {
370 case FLASH_CFI_8BIT:
cdbaefb5 371 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 372 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 373 flash_write8(cword.c, addr);
be60a902
HS		 374 break;
375 case FLASH_CFI_16BIT:
cdbaefb5 376 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS		 377 cmd, cword.w,
378 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 379 flash_write16(cword.w, addr);
be60a902
HS		 380 break;
381 case FLASH_CFI_32BIT:
cdbaefb5 382 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS		 383 cmd, cword.l,
384 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 385 flash_write32(cword.l, addr);
be60a902
HS		 386 break;
387 case FLASH_CFI_64BIT:
388#ifdef DEBUG
389 {
390 char str[20];
7e5b9b47 391
be60a902
HS		 392 print_longlong (str, cword.ll);
393
394 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 395 addr, cmd, str,
be60a902 396 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 397 }
be60a902 398#endif
cdbaefb5 399 flash_write64(cword.ll, addr);
be60a902 400 break;
81b20ccc 401 }
be60a902
HS		 402
403 /* Ensure all the instructions are fully finished */
404 sync();
12d30aa7
HS		 405
406 flash_unmap(info, sect, offset, addr);
81b20ccc 407}
be60a902
HS		 408
409static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 410{
be60a902
HS		 411 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
412 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 413}
81b20ccc 414
5653fc33
WD		 415/*-----------------------------------------------------------------------
416 */
be60a902
HS		 417static int flash_isequal (flash_info_t * info, flash_sect_t sect,
418 uint offset, uchar cmd)
5653fc33 419{
cdbaefb5 420 void *addr;
be60a902
HS		 421 cfiword_t cword;
422 int retval;
5653fc33 423
12d30aa7 424 addr = flash_map (info, sect, offset);
be60a902 425 flash_make_cmd (info, cmd, &cword);
2662b40c 426
cdbaefb5 427 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 428 switch (info->portwidth) {
429 case FLASH_CFI_8BIT:
cdbaefb5
HS		 430 debug ("is= %x %x\n", flash_read8(addr), cword.c);
431 retval = (flash_read8(addr) == cword.c);
be60a902
HS		 432 break;
433 case FLASH_CFI_16BIT:
cdbaefb5
HS		 434 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
435 retval = (flash_read16(addr) == cword.w);
be60a902
HS		 436 break;
437 case FLASH_CFI_32BIT:
52514699 438 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
cdbaefb5 439 retval = (flash_read32(addr) == cword.l);
be60a902
HS		 440 break;
441 case FLASH_CFI_64BIT:
442#ifdef DEBUG
443 {
444 char str1[20];
445 char str2[20];
81b20ccc 446
cdbaefb5 447 print_longlong (str1, flash_read64(addr));
be60a902
HS		 448 print_longlong (str2, cword.ll);
449 debug ("is= %s %s\n", str1, str2);
5653fc33 450 }
be60a902 451#endif
cdbaefb5 452 retval = (flash_read64(addr) == cword.ll);
be60a902
HS		 453 break;
454 default:
455 retval = 0;
456 break;
457 }
12d30aa7
HS		 458 flash_unmap(info, sect, offset, addr);
459
be60a902
HS		 460 return retval;
461}
79b4cda0 462
be60a902
HS		 463/*-----------------------------------------------------------------------
464 */
465static int flash_isset (flash_info_t * info, flash_sect_t sect,
466 uint offset, uchar cmd)
467{
cdbaefb5 468 void *addr;
be60a902
HS		 469 cfiword_t cword;
470 int retval;
2662b40c 471
12d30aa7 472 addr = flash_map (info, sect, offset);
be60a902
HS		 473 flash_make_cmd (info, cmd, &cword);
474 switch (info->portwidth) {
475 case FLASH_CFI_8BIT:
cdbaefb5 476 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS		 477 break;
478 case FLASH_CFI_16BIT:
cdbaefb5 479 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS		 480 break;
481 case FLASH_CFI_32BIT:
47cc23cb 482 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS		 483 break;
484 case FLASH_CFI_64BIT:
cdbaefb5 485 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS		 486 break;
487 default:
488 retval = 0;
489 break;
490 }
12d30aa7
HS		 491 flash_unmap(info, sect, offset, addr);
492
be60a902
HS		 493 return retval;
494}
2662b40c 495
be60a902
HS		 496/*-----------------------------------------------------------------------
497 */
498static int flash_toggle (flash_info_t * info, flash_sect_t sect,
499 uint offset, uchar cmd)
500{
cdbaefb5 501 void *addr;
be60a902
HS		 502 cfiword_t cword;
503 int retval;
656658dd 504
12d30aa7 505 addr = flash_map (info, sect, offset);
be60a902
HS		 506 flash_make_cmd (info, cmd, &cword);
507 switch (info->portwidth) {
508 case FLASH_CFI_8BIT:
fb8c061e 509 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 510 break;
511 case FLASH_CFI_16BIT:
fb8c061e 512 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 513 break;
514 case FLASH_CFI_32BIT:
fb8c061e 515 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 516 break;
517 case FLASH_CFI_64BIT:
9abda6ba
WD		 518 retval = ( (flash_read32( addr ) != flash_read32( addr )) ||
519 (flash_read32(addr+4) != flash_read32(addr+4)) );
be60a902
HS		 520 break;
521 default:
522 retval = 0;
523 break;
524 }
12d30aa7
HS		 525 flash_unmap(info, sect, offset, addr);
526
be60a902 527 return retval;
5653fc33
WD		 528}
529
be60a902
HS		 530/*
531 * flash_is_busy - check to see if the flash is busy
532 *
533 * This routine checks the status of the chip and returns true if the
534 * chip is busy.
7680c140 535 */
be60a902 536static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 537{
be60a902 538 int retval;
7680c140 539
be60a902 540 switch (info->vendor) {
9c048b52 541 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 542 case CFI_CMDSET_INTEL_STANDARD:
543 case CFI_CMDSET_INTEL_EXTENDED:
544 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
545 break;
546 case CFI_CMDSET_AMD_STANDARD:
547 case CFI_CMDSET_AMD_EXTENDED:
548#ifdef CONFIG_FLASH_CFI_LEGACY
549 case CFI_CMDSET_AMD_LEGACY:
550#endif
551 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
552 break;
553 default:
554 retval = 0;
7680c140 555 }
be60a902
HS		 556 debug ("flash_is_busy: %d\n", retval);
557 return retval;
7680c140
WD		 558}
559
5653fc33 560/*-----------------------------------------------------------------------
be60a902
HS		 561 * wait for XSR.7 to be set. Time out with an error if it does not.
562 * This routine does not set the flash to read-array mode.
5653fc33 563 */
be60a902
HS		 564static int flash_status_check (flash_info_t * info, flash_sect_t sector,
565 ulong tout, char *prompt)
5653fc33 566{
be60a902 567 ulong start;
5653fc33 568
6d0f6bcf 569#if CONFIG_SYS_HZ != 1000
c40c94a3
RA		 570 if ((ulong)CONFIG_SYS_HZ > 100000)
571 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
572 else
573 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
be60a902 574#endif
5653fc33 575
be60a902 576 /* Wait for command completion */
e110c4fe 577#ifdef CONFIG_SYS_LOW_RES_TIMER
22d6c8fa 578 reset_timer();
e110c4fe 579#endif
be60a902 580 start = get_timer (0);
a9f5faba 581 WATCHDOG_RESET();
be60a902
HS		 582 while (flash_is_busy (info, sector)) {
583 if (get_timer (start) > tout) {
584 printf ("Flash %s timeout at address %lx data %lx\n",
585 prompt, info->start[sector],
586 flash_read_long (info, sector, 0));
587 flash_write_cmd (info, sector, 0, info->cmd_reset);
a90b9575 588 udelay(1);
be60a902 589 return ERR_TIMOUT;
5653fc33 590 }
be60a902 591 udelay (1); /* also triggers watchdog */
5653fc33 592 }
be60a902
HS		 593 return ERR_OK;
594}
5653fc33 595
be60a902
HS		 596/*-----------------------------------------------------------------------
597 * Wait for XSR.7 to be set, if it times out print an error, otherwise
598 * do a full status check.
599 *
600 * This routine sets the flash to read-array mode.
601 */
602static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
603 ulong tout, char *prompt)
604{
605 int retcode;
5653fc33 606
be60a902
HS		 607 retcode = flash_status_check (info, sector, tout, prompt);
608 switch (info->vendor) {
9c048b52 609 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 610 case CFI_CMDSET_INTEL_EXTENDED:
611 case CFI_CMDSET_INTEL_STANDARD:
0d01f66d 612 if ((retcode != ERR_OK)
be60a902
HS		 613 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
614 retcode = ERR_INVAL;
615 printf ("Flash %s error at address %lx\n", prompt,
616 info->start[sector]);
617 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
618 FLASH_STATUS_PSLBS)) {
619 puts ("Command Sequence Error.\n");
620 } else if (flash_isset (info, sector, 0,
621 FLASH_STATUS_ECLBS)) {
622 puts ("Block Erase Error.\n");
623 retcode = ERR_NOT_ERASED;
624 } else if (flash_isset (info, sector, 0,
625 FLASH_STATUS_PSLBS)) {
626 puts ("Locking Error\n");
5653fc33 627 }
be60a902
HS		 628 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
629 puts ("Block locked.\n");
630 retcode = ERR_PROTECTED;
631 }
632 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
633 puts ("Vpp Low Error.\n");
5653fc33 634 }
be60a902 635 flash_write_cmd (info, sector, 0, info->cmd_reset);
a90b9575 636 udelay(1);
be60a902
HS		 637 break;
638 default:
639 break;
5653fc33 640 }
be60a902 641 return retcode;
5653fc33
WD		 642}
643
e5720823
TC		 644static int use_flash_status_poll(flash_info_t *info)
645{
646#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
647 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
648 info->vendor == CFI_CMDSET_AMD_STANDARD)
649 return 1;
650#endif
651 return 0;
652}
653
654static int flash_status_poll(flash_info_t *info, void *src, void *dst,
655 ulong tout, char *prompt)
656{
657#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
658 ulong start;
659 int ready;
660
661#if CONFIG_SYS_HZ != 1000
662 if ((ulong)CONFIG_SYS_HZ > 100000)
663 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
664 else
665 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
666#endif
667
668 /* Wait for command completion */
e110c4fe 669#ifdef CONFIG_SYS_LOW_RES_TIMER
22d6c8fa 670 reset_timer();
e110c4fe 671#endif
e5720823 672 start = get_timer(0);
a9f5faba 673 WATCHDOG_RESET();
e5720823
TC		 674 while (1) {
675 switch (info->portwidth) {
676 case FLASH_CFI_8BIT:
677 ready = flash_read8(dst) == flash_read8(src);
678 break;
679 case FLASH_CFI_16BIT:
680 ready = flash_read16(dst) == flash_read16(src);
681 break;
682 case FLASH_CFI_32BIT:
683 ready = flash_read32(dst) == flash_read32(src);
684 break;
685 case FLASH_CFI_64BIT:
686 ready = flash_read64(dst) == flash_read64(src);
687 break;
688 default:
689 ready = 0;
690 break;
691 }
692 if (ready)
693 break;
694 if (get_timer(start) > tout) {
695 printf("Flash %s timeout at address %lx data %lx\n",
696 prompt, (ulong)dst, (ulong)flash_read8(dst));
697 return ERR_TIMOUT;
698 }
699 udelay(1); /* also triggers watchdog */
700 }
701#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
702 return ERR_OK;
703}
704
5653fc33
WD		 705/*-----------------------------------------------------------------------
706 */
be60a902 707static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 708{
6d0f6bcf 709#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 710 unsigned short w;
711 unsigned int l;
712 unsigned long long ll;
713#endif
5653fc33 714
be60a902
HS		 715 switch (info->portwidth) {
716 case FLASH_CFI_8BIT:
717 cword->c = c;
718 break;
719 case FLASH_CFI_16BIT:
6d0f6bcf 720#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 721 w = c;
722 w <<= 8;
723 cword->w = (cword->w >> 8) | w;
724#else
725 cword->w = (cword->w << 8) | c;
81b20ccc 726#endif
be60a902
HS		 727 break;
728 case FLASH_CFI_32BIT:
6d0f6bcf 729#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 730 l = c;
731 l <<= 24;
732 cword->l = (cword->l >> 8) | l;
733#else
734 cword->l = (cword->l << 8) | c;
735#endif
736 break;
737 case FLASH_CFI_64BIT:
6d0f6bcf 738#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 739 ll = c;
740 ll <<= 56;
741 cword->ll = (cword->ll >> 8) | ll;
742#else
743 cword->ll = (cword->ll << 8) | c;
744#endif
745 break;
260421a2 746 }
be60a902 747}
5653fc33 748
0f8e851e
JG		 749/*
750 * Loop through the sector table starting from the previously found sector.
751 * Searches forwards or backwards, dependent on the passed address.
be60a902
HS		 752 */
753static flash_sect_t find_sector (flash_info_t * info, ulong addr)
754{
11dc4010
KP		 755 static flash_sect_t saved_sector; /* previously found sector */
756 static flash_info_t *saved_info; /* previously used flash bank */
0f8e851e
JG		 757 flash_sect_t sector = saved_sector;
758
af567301
MK		 759 if ((info != saved_info) || (sector >= info->sector_count))
760 sector = 0;
761
0f8e851e
JG		 762 while ((info->start[sector] < addr)
763 && (sector < info->sector_count - 1))
764 sector++;
765 while ((info->start[sector] > addr) && (sector > 0))
766 /*
767 * also decrements the sector in case of an overshot
768 * in the first loop
769 */
770 sector--;
771
772 saved_sector = sector;
af567301 773 saved_info = info;
be60a902 774 return sector;
5653fc33
WD		 775}
776
777/*-----------------------------------------------------------------------
5653fc33 778 */
be60a902
HS		 779static int flash_write_cfiword (flash_info_t * info, ulong dest,
780 cfiword_t cword)
5653fc33 781{
09ce9921 782 void *dstaddr = (void *)dest;
be60a902 783 int flag;
a7292871
JG		 784 flash_sect_t sect = 0;
785 char sect_found = 0;
5653fc33 786
be60a902
HS		 787 /* Check if Flash is (sufficiently) erased */
788 switch (info->portwidth) {
789 case FLASH_CFI_8BIT:
cdbaefb5 790 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS		 791 break;
792 case FLASH_CFI_16BIT:
cdbaefb5 793 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS		 794 break;
795 case FLASH_CFI_32BIT:
cdbaefb5 796 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS		 797 break;
798 case FLASH_CFI_64BIT:
cdbaefb5 799 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS		 800 break;
801 default:
12d30aa7
HS		 802 flag = 0;
803 break;
5653fc33 804 }
09ce9921 805 if (!flag)
0dc80e27 806 return ERR_NOT_ERASED;
5653fc33 807
be60a902
HS		 808 /* Disable interrupts which might cause a timeout here */
809 flag = disable_interrupts ();
79b4cda0 810
be60a902 811 switch (info->vendor) {
9c048b52 812 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 813 case CFI_CMDSET_INTEL_EXTENDED:
814 case CFI_CMDSET_INTEL_STANDARD:
815 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
816 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
817 break;
818 case CFI_CMDSET_AMD_EXTENDED:
819 case CFI_CMDSET_AMD_STANDARD:
0d01f66d
ES		 820 sect = find_sector(info, dest);
821 flash_unlock_seq (info, sect);
822 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
a7292871 823 sect_found = 1;
be60a902 824 break;
b4db4a76
PYC		 825#ifdef CONFIG_FLASH_CFI_LEGACY
826 case CFI_CMDSET_AMD_LEGACY:
827 sect = find_sector(info, dest);
828 flash_unlock_seq (info, 0);
829 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
830 sect_found = 1;
831 break;
832#endif
5653fc33
WD		 833 }
834
be60a902
HS		 835 switch (info->portwidth) {
836 case FLASH_CFI_8BIT:
cdbaefb5 837 flash_write8(cword.c, dstaddr);
be60a902
HS		 838 break;
839 case FLASH_CFI_16BIT:
cdbaefb5 840 flash_write16(cword.w, dstaddr);
be60a902
HS		 841 break;
842 case FLASH_CFI_32BIT:
cdbaefb5 843 flash_write32(cword.l, dstaddr);
be60a902
HS		 844 break;
845 case FLASH_CFI_64BIT:
cdbaefb5 846 flash_write64(cword.ll, dstaddr);
be60a902 847 break;
5653fc33
WD		 848 }
849
be60a902
HS		 850 /* re-enable interrupts if necessary */
851 if (flag)
852 enable_interrupts ();
5653fc33 853
a7292871
JG		 854 if (!sect_found)
855 sect = find_sector (info, dest);
856
e5720823
TC		 857 if (use_flash_status_poll(info))
858 return flash_status_poll(info, &cword, dstaddr,
859 info->write_tout, "write");
860 else
861 return flash_full_status_check(info, sect,
862 info->write_tout, "write");
5653fc33
WD		 863}
864
6d0f6bcf 865#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 866
be60a902
HS		 867static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
868 int len)
5653fc33 869{
be60a902
HS		 870 flash_sect_t sector;
871 int cnt;
872 int retcode;
cdbaefb5 873 void *src = cp;
ec21d5cf 874 void *dst = (void *)dest;
0dc80e27 875 void *dst2 = dst;
85c344e5 876 int flag = 1;
96ef831f
GL		 877 uint offset = 0;
878 unsigned int shift;
9c048b52 879 uchar write_cmd;
cdbaefb5 880
0dc80e27
SR		 881 switch (info->portwidth) {
882 case FLASH_CFI_8BIT:
96ef831f 883 shift = 0;
0dc80e27
SR		 884 break;
885 case FLASH_CFI_16BIT:
96ef831f 886 shift = 1;
0dc80e27
SR		 887 break;
888 case FLASH_CFI_32BIT:
96ef831f 889 shift = 2;
0dc80e27
SR		 890 break;
891 case FLASH_CFI_64BIT:
96ef831f 892 shift = 3;
0dc80e27
SR		 893 break;
894 default:
895 retcode = ERR_INVAL;
896 goto out_unmap;
897 }
898
96ef831f
GL		 899 cnt = len >> shift;
900
85c344e5 901 while ((cnt-- > 0) && (flag == 1)) {
0dc80e27
SR		 902 switch (info->portwidth) {
903 case FLASH_CFI_8BIT:
904 flag = ((flash_read8(dst2) & flash_read8(src)) ==
905 flash_read8(src));
906 src += 1, dst2 += 1;
907 break;
908 case FLASH_CFI_16BIT:
909 flag = ((flash_read16(dst2) & flash_read16(src)) ==
910 flash_read16(src));
911 src += 2, dst2 += 2;
912 break;
913 case FLASH_CFI_32BIT:
914 flag = ((flash_read32(dst2) & flash_read32(src)) ==
915 flash_read32(src));
916 src += 4, dst2 += 4;
917 break;
918 case FLASH_CFI_64BIT:
919 flag = ((flash_read64(dst2) & flash_read64(src)) ==
920 flash_read64(src));
921 src += 8, dst2 += 8;
922 break;
923 }
924 }
925 if (!flag) {
926 retcode = ERR_NOT_ERASED;
927 goto out_unmap;
928 }
929
930 src = cp;
cdbaefb5 931 sector = find_sector (info, dest);
bf9e3b38
WD		 932
933 switch (info->vendor) {
9c048b52 934 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 935 case CFI_CMDSET_INTEL_STANDARD:
936 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52
VL		 937 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
938 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
be60a902 939 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
9c048b52
VL		 940 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
941 flash_write_cmd (info, sector, 0, write_cmd);
be60a902
HS		 942 retcode = flash_status_check (info, sector,
943 info->buffer_write_tout,
944 "write to buffer");
945 if (retcode == ERR_OK) {
946 /* reduce the number of loops by the width of
947 * the port */
96ef831f 948 cnt = len >> shift;
93c56f21 949 flash_write_cmd (info, sector, 0, cnt - 1);
be60a902
HS		 950 while (cnt-- > 0) {
951 switch (info->portwidth) {
952 case FLASH_CFI_8BIT:
cdbaefb5
HS		 953 flash_write8(flash_read8(src), dst);
954 src += 1, dst += 1;
be60a902
HS		 955 break;
956 case FLASH_CFI_16BIT:
cdbaefb5
HS		 957 flash_write16(flash_read16(src), dst);
958 src += 2, dst += 2;
be60a902
HS		 959 break;
960 case FLASH_CFI_32BIT:
cdbaefb5
HS		 961 flash_write32(flash_read32(src), dst);
962 src += 4, dst += 4;
be60a902
HS		 963 break;
964 case FLASH_CFI_64BIT:
cdbaefb5
HS		 965 flash_write64(flash_read64(src), dst);
966 src += 8, dst += 8;
be60a902
HS		 967 break;
968 default:
12d30aa7
HS		 969 retcode = ERR_INVAL;
970 goto out_unmap;
be60a902
HS		 971 }
972 }
973 flash_write_cmd (info, sector, 0,
974 FLASH_CMD_WRITE_BUFFER_CONFIRM);
975 retcode = flash_full_status_check (
976 info, sector, info->buffer_write_tout,
977 "buffer write");
978 }
12d30aa7
HS		 979
980 break;
be60a902 981
5653fc33
WD		 982 case CFI_CMDSET_AMD_STANDARD:
983 case CFI_CMDSET_AMD_EXTENDED:
be60a902 984 flash_unlock_seq(info,0);
96ef831f
GL		 985
986#ifdef CONFIG_FLASH_SPANSION_S29WS_N
987 offset = ((unsigned long)dst - info->start[sector]) >> shift;
988#endif
989 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
990 cnt = len >> shift;
7dedefdf 991 flash_write_cmd(info, sector, offset, cnt - 1);
be60a902
HS		 992
993 switch (info->portwidth) {
994 case FLASH_CFI_8BIT:
cdbaefb5
HS		 995 while (cnt-- > 0) {
996 flash_write8(flash_read8(src), dst);
997 src += 1, dst += 1;
998 }
be60a902
HS		 999 break;
1000 case FLASH_CFI_16BIT:
cdbaefb5
HS		 1001 while (cnt-- > 0) {
1002 flash_write16(flash_read16(src), dst);
1003 src += 2, dst += 2;
1004 }
be60a902
HS		 1005 break;
1006 case FLASH_CFI_32BIT:
cdbaefb5
HS		 1007 while (cnt-- > 0) {
1008 flash_write32(flash_read32(src), dst);
1009 src += 4, dst += 4;
1010 }
be60a902
HS		 1011 break;
1012 case FLASH_CFI_64BIT:
cdbaefb5
HS		 1013 while (cnt-- > 0) {
1014 flash_write64(flash_read64(src), dst);
1015 src += 8, dst += 8;
1016 }
be60a902
HS		 1017 break;
1018 default:
12d30aa7
HS		 1019 retcode = ERR_INVAL;
1020 goto out_unmap;
be60a902
HS		 1021 }
1022
1023 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
e5720823
TC		 1024 if (use_flash_status_poll(info))
1025 retcode = flash_status_poll(info, src - (1 << shift),
1026 dst - (1 << shift),
1027 info->buffer_write_tout,
1028 "buffer write");
1029 else
1030 retcode = flash_full_status_check(info, sector,
1031 info->buffer_write_tout,
1032 "buffer write");
12d30aa7 1033 break;
be60a902 1034
5653fc33 1035 default:
be60a902 1036 debug ("Unknown Command Set\n");
12d30aa7
HS		 1037 retcode = ERR_INVAL;
1038 break;
5653fc33 1039 }
12d30aa7
HS		 1040
1041out_unmap:
12d30aa7 1042 return retcode;
5653fc33 1043}
6d0f6bcf 1044#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1045
bf9e3b38 1046
5653fc33 1047/*-----------------------------------------------------------------------
5653fc33 1048 */
be60a902 1049int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1050{
be60a902
HS		 1051 int rcode = 0;
1052 int prot;
1053 flash_sect_t sect;
e5720823 1054 int st;
5653fc33 1055
be60a902
HS		 1056 if (info->flash_id != FLASH_MAN_CFI) {
1057 puts ("Can't erase unknown flash type - aborted\n");
1058 return 1;
1059 }
1060 if ((s_first < 0) || (s_first > s_last)) {
1061 puts ("- no sectors to erase\n");
1062 return 1;
1063 }
2662b40c 1064
be60a902
HS		 1065 prot = 0;
1066 for (sect = s_first; sect <= s_last; ++sect) {
1067 if (info->protect[sect]) {
1068 prot++;
5653fc33
WD		 1069 }
1070 }
be60a902
HS		 1071 if (prot) {
1072 printf ("- Warning: %d protected sectors will not be erased!\n",
1073 prot);
6ea808ef 1074 } else if (flash_verbose) {
be60a902
HS		 1075 putc ('\n');
1076 }
bf9e3b38 1077
bf9e3b38 1078
be60a902 1079 for (sect = s_first; sect <= s_last; sect++) {
de15a06a
JH		 1080 if (ctrlc()) {
1081 printf("\n");
1082 return 1;
1083 }
1084
be60a902 1085 if (info->protect[sect] == 0) { /* not protected */
6822a647
JH		 1086#ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
1087 int k;
1088 int size;
1089 int erased;
1090 u32 *flash;
1091
1092 /*
1093 * Check if whole sector is erased
1094 */
1095 size = flash_sector_size(info, sect);
1096 erased = 1;
1097 flash = (u32 *)info->start[sect];
1098 /* divide by 4 for longword access */
1099 size = size >> 2;
1100 for (k = 0; k < size; k++) {
1101 if (flash_read32(flash++) != 0xffffffff) {
1102 erased = 0;
1103 break;
1104 }
1105 }
1106 if (erased) {
1107 if (flash_verbose)
1108 putc(',');
1109 continue;
1110 }
1111#endif
be60a902 1112 switch (info->vendor) {
9c048b52 1113 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1114 case CFI_CMDSET_INTEL_STANDARD:
1115 case CFI_CMDSET_INTEL_EXTENDED:
1116 flash_write_cmd (info, sect, 0,
1117 FLASH_CMD_CLEAR_STATUS);
1118 flash_write_cmd (info, sect, 0,
1119 FLASH_CMD_BLOCK_ERASE);
1120 flash_write_cmd (info, sect, 0,
1121 FLASH_CMD_ERASE_CONFIRM);
1122 break;
1123 case CFI_CMDSET_AMD_STANDARD:
1124 case CFI_CMDSET_AMD_EXTENDED:
1125 flash_unlock_seq (info, sect);
1126 flash_write_cmd (info, sect,
1127 info->addr_unlock1,
1128 AMD_CMD_ERASE_START);
1129 flash_unlock_seq (info, sect);
1130 flash_write_cmd (info, sect, 0,
1131 AMD_CMD_ERASE_SECTOR);
1132 break;
1133#ifdef CONFIG_FLASH_CFI_LEGACY
1134 case CFI_CMDSET_AMD_LEGACY:
1135 flash_unlock_seq (info, 0);
1136 flash_write_cmd (info, 0, info->addr_unlock1,
1137 AMD_CMD_ERASE_START);
1138 flash_unlock_seq (info, 0);
1139 flash_write_cmd (info, sect, 0,
1140 AMD_CMD_ERASE_SECTOR);
1141 break;
1142#endif
1143 default:
1144 debug ("Unkown flash vendor %d\n",
1145 info->vendor);
1146 break;
bf9e3b38 1147 }
be60a902 1148
e5720823 1149 if (use_flash_status_poll(info)) {
11dc4010 1150 cfiword_t cword;
e5720823 1151 void *dest;
11dc4010 1152 cword.ll = 0xffffffffffffffffULL;
e5720823
TC		 1153 dest = flash_map(info, sect, 0);
1154 st = flash_status_poll(info, &cword, dest,
1155 info->erase_blk_tout, "erase");
1156 flash_unmap(info, sect, 0, dest);
1157 } else
1158 st = flash_full_status_check(info, sect,
1159 info->erase_blk_tout,
1160 "erase");
1161 if (st)
be60a902 1162 rcode = 1;
e5720823 1163 else if (flash_verbose)
be60a902 1164 putc ('.');
5653fc33 1165 }
5653fc33 1166 }
6ea808ef
PZ		 1167
1168 if (flash_verbose)
1169 puts (" done\n");
1170
be60a902 1171 return rcode;
5653fc33 1172}
bf9e3b38 1173
70084df7
SR		 1174#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1175static int sector_erased(flash_info_t *info, int i)
1176{
1177 int k;
1178 int size;
4d2ca9d6 1179 u32 *flash;
70084df7
SR		 1180
1181 /*
1182 * Check if whole sector is erased
1183 */
1184 size = flash_sector_size(info, i);
4d2ca9d6 1185 flash = (u32 *)info->start[i];
70084df7
SR		 1186 /* divide by 4 for longword access */
1187 size = size >> 2;
1188
1189 for (k = 0; k < size; k++) {
4d2ca9d6 1190 if (flash_read32(flash++) != 0xffffffff)
70084df7
SR		 1191 return 0; /* not erased */
1192 }
1193
1194 return 1; /* erased */
1195}
1196#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1197
be60a902 1198void flash_print_info (flash_info_t * info)
5653fc33 1199{
be60a902 1200 int i;
4d13cbad 1201
be60a902
HS		 1202 if (info->flash_id != FLASH_MAN_CFI) {
1203 puts ("missing or unknown FLASH type\n");
1204 return;
1205 }
1206
eddf52b5 1207 printf ("%s flash (%d x %d)",
be60a902
HS		 1208 info->name,
1209 (info->portwidth << 3), (info->chipwidth << 3));
1210 if (info->size < 1024*1024)
1211 printf (" Size: %ld kB in %d Sectors\n",
1212 info->size >> 10, info->sector_count);
1213 else
1214 printf (" Size: %ld MB in %d Sectors\n",
1215 info->size >> 20, info->sector_count);
1216 printf (" ");
1217 switch (info->vendor) {
9c048b52
VL		 1218 case CFI_CMDSET_INTEL_PROG_REGIONS:
1219 printf ("Intel Prog Regions");
1220 break;
be60a902
HS		 1221 case CFI_CMDSET_INTEL_STANDARD:
1222 printf ("Intel Standard");
1223 break;
1224 case CFI_CMDSET_INTEL_EXTENDED:
1225 printf ("Intel Extended");
1226 break;
1227 case CFI_CMDSET_AMD_STANDARD:
1228 printf ("AMD Standard");
1229 break;
1230 case CFI_CMDSET_AMD_EXTENDED:
1231 printf ("AMD Extended");
1232 break;
1233#ifdef CONFIG_FLASH_CFI_LEGACY
1234 case CFI_CMDSET_AMD_LEGACY:
1235 printf ("AMD Legacy");
1236 break;
4d13cbad 1237#endif
be60a902
HS		 1238 default:
1239 printf ("Unknown (%d)", info->vendor);
1240 break;
1241 }
d77c7ac4
PDM		 1242 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
1243 info->manufacturer_id);
1244 printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1245 info->device_id);
5b448adb
HS		 1246 if ((info->device_id & 0xff) == 0x7E) {
1247 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1248 info->device_id2);
be60a902
HS		 1249 }
1250 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1251 info->erase_blk_tout,
1252 info->write_tout);
1253 if (info->buffer_size > 1) {
1254 printf (" Buffer write timeout: %ld ms, "
1255 "buffer size: %d bytes\n",
1256 info->buffer_write_tout,
1257 info->buffer_size);
5653fc33 1258 }
5653fc33 1259
be60a902
HS		 1260 puts ("\n Sector Start Addresses:");
1261 for (i = 0; i < info->sector_count; ++i) {
2e97394a 1262 if (ctrlc())
70084df7 1263 break;
be60a902 1264 if ((i % 5) == 0)
70084df7 1265 putc('\n');
6d0f6bcf 1266#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902
HS		 1267 /* print empty and read-only info */
1268 printf (" %08lX %c %s ",
1269 info->start[i],
70084df7 1270 sector_erased(info, i) ? 'E' : ' ',
be60a902 1271 info->protect[i] ? "RO" : " ");
6d0f6bcf 1272#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
be60a902
HS		 1273 printf (" %08lX %s ",
1274 info->start[i],
1275 info->protect[i] ? "RO" : " ");
bf9e3b38 1276#endif
be60a902
HS		 1277 }
1278 putc ('\n');
1279 return;
5653fc33
WD		 1280}
1281
9a042e9c
JVB		 1282/*-----------------------------------------------------------------------
1283 * This is used in a few places in write_buf() to show programming
1284 * progress. Making it a function is nasty because it needs to do side
1285 * effect updates to digit and dots. Repeated code is nasty too, so
1286 * we define it once here.
1287 */
f0105727
SR		 1288#ifdef CONFIG_FLASH_SHOW_PROGRESS
1289#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
6ea808ef
PZ		 1290 if (flash_verbose) { \
1291 dots -= dots_sub; \
1292 if ((scale > 0) && (dots <= 0)) { \
1293 if ((digit % 5) == 0) \
1294 printf ("%d", digit / 5); \
1295 else \
1296 putc ('.'); \
1297 digit--; \
1298 dots += scale; \
1299 } \
9a042e9c 1300 }
f0105727
SR		 1301#else
1302#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1303#endif
9a042e9c 1304
be60a902
HS		 1305/*-----------------------------------------------------------------------
1306 * Copy memory to flash, returns:
1307 * 0 - OK
1308 * 1 - write timeout
1309 * 2 - Flash not erased
5653fc33 1310 */
be60a902 1311int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1312{
be60a902 1313 ulong wp;
12d30aa7 1314 uchar *p;
be60a902 1315 int aln;
5653fc33 1316 cfiword_t cword;
be60a902 1317 int i, rc;
6d0f6bcf 1318#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1319 int buffered_size;
5653fc33 1320#endif
9a042e9c
JVB		 1321#ifdef CONFIG_FLASH_SHOW_PROGRESS
1322 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1323 int scale = 0;
1324 int dots = 0;
1325
1326 /*
1327 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1328 */
1329 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1330 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1331 CONFIG_FLASH_SHOW_PROGRESS);
1332 }
1333#endif
1334
be60a902
HS		 1335 /* get lower aligned address */
1336 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1337
be60a902
HS		 1338 /* handle unaligned start */
1339 if ((aln = addr - wp) != 0) {
1340 cword.l = 0;
09ce9921 1341 p = (uchar *)wp;
12d30aa7
HS		 1342 for (i = 0; i < aln; ++i)
1343 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1344
be60a902
HS		 1345 for (; (i < info->portwidth) && (cnt > 0); i++) {
1346 flash_add_byte (info, &cword, *src++);
1347 cnt--;
be60a902 1348 }
12d30aa7
HS		 1349 for (; (cnt == 0) && (i < info->portwidth); ++i)
1350 flash_add_byte (info, &cword, flash_read8(p + i));
1351
1352 rc = flash_write_cfiword (info, wp, cword);
12d30aa7 1353 if (rc != 0)
be60a902 1354 return rc;
12d30aa7
HS		 1355
1356 wp += i;
f0105727 1357 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1358 }
1359
1360 /* handle the aligned part */
6d0f6bcf 1361#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS		 1362 buffered_size = (info->portwidth / info->chipwidth);
1363 buffered_size *= info->buffer_size;
1364 while (cnt >= info->portwidth) {
1365 /* prohibit buffer write when buffer_size is 1 */
1366 if (info->buffer_size == 1) {
1367 cword.l = 0;
1368 for (i = 0; i < info->portwidth; i++)
1369 flash_add_byte (info, &cword, *src++);
1370 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1371 return rc;
1372 wp += info->portwidth;
1373 cnt -= info->portwidth;
1374 continue;
1375 }
1376
1377 /* write buffer until next buffered_size aligned boundary */
1378 i = buffered_size - (wp % buffered_size);
1379 if (i > cnt)
1380 i = cnt;
1381 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1382 return rc;
1383 i -= i & (info->portwidth - 1);
1384 wp += i;
1385 src += i;
1386 cnt -= i;
f0105727 1387 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
de15a06a
JH		 1388 /* Only check every once in a while */
1389 if ((cnt & 0xFFFF) < buffered_size && ctrlc())
1390 return ERR_ABORTED;
be60a902
HS		 1391 }
1392#else
1393 while (cnt >= info->portwidth) {
1394 cword.l = 0;
1395 for (i = 0; i < info->portwidth; i++) {
1396 flash_add_byte (info, &cword, *src++);
1397 }
1398 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1399 return rc;
1400 wp += info->portwidth;
1401 cnt -= info->portwidth;
f0105727 1402 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
de15a06a
JH		 1403 /* Only check every once in a while */
1404 if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
1405 return ERR_ABORTED;
be60a902 1406 }
6d0f6bcf 1407#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1408
be60a902
HS		 1409 if (cnt == 0) {
1410 return (0);
1411 }
1412
1413 /*
1414 * handle unaligned tail bytes
1415 */
1416 cword.l = 0;
09ce9921 1417 p = (uchar *)wp;
12d30aa7 1418 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS		 1419 flash_add_byte (info, &cword, *src++);
1420 --cnt;
1421 }
12d30aa7
HS		 1422 for (; i < info->portwidth; ++i)
1423 flash_add_byte (info, &cword, flash_read8(p + i));
be60a902
HS		 1424
1425 return flash_write_cfiword (info, wp, cword);
5653fc33 1426}
bf9e3b38 1427
5653fc33
WD		 1428/*-----------------------------------------------------------------------
1429 */
6d0f6bcf 1430#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902 1431
81316a90
HB		 1432static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
1433{
11dc4010
KP		 1434 if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16)
1435 && info->device_id == NUMONYX_256MBIT) {
81316a90
HB		 1436 /*
1437 * see errata called
1438 * "Numonyx Axcell P33/P30 Specification Update" :)
1439 */
1440 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID);
1441 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT,
1442 prot)) {
1443 /*
1444 * cmd must come before FLASH_CMD_PROTECT + 20us
1445 * Disable interrupts which might cause a timeout here.
1446 */
1447 int flag = disable_interrupts();
1448 unsigned short cmd;
1449
1450 if (prot)
1451 cmd = FLASH_CMD_PROTECT_SET;
1452 else
1453 cmd = FLASH_CMD_PROTECT_CLEAR;
1454 flash_write_cmd(info, sector, 0,
1455 FLASH_CMD_PROTECT);
1456 flash_write_cmd(info, sector, 0, cmd);
1457 /* re-enable interrupts if necessary */
1458 if (flag)
1459 enable_interrupts();
1460 }
1461 return 1;
1462 }
1463 return 0;
1464}
1465
be60a902 1466int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1467{
be60a902 1468 int retcode = 0;
5653fc33 1469
bc9019e1
RC		 1470 switch (info->vendor) {
1471 case CFI_CMDSET_INTEL_PROG_REGIONS:
1472 case CFI_CMDSET_INTEL_STANDARD:
9e8e63cc 1473 case CFI_CMDSET_INTEL_EXTENDED:
81316a90
HB		 1474 if (!cfi_protect_bugfix(info, sector, prot)) {
1475 flash_write_cmd(info, sector, 0,
1476 FLASH_CMD_CLEAR_STATUS);
1477 flash_write_cmd(info, sector, 0,
1478 FLASH_CMD_PROTECT);
54652991 1479 if (prot)
81316a90
HB		 1480 flash_write_cmd(info, sector, 0,
1481 FLASH_CMD_PROTECT_SET);
54652991 1482 else
81316a90
HB		 1483 flash_write_cmd(info, sector, 0,
1484 FLASH_CMD_PROTECT_CLEAR);
1485
54652991 1486 }
bc9019e1
RC		 1487 break;
1488 case CFI_CMDSET_AMD_EXTENDED:
1489 case CFI_CMDSET_AMD_STANDARD:
bc9019e1 1490 /* U-Boot only checks the first byte */
11dc4010
KP		 1491 if (info->manufacturer_id ==
1492 ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) {
bc9019e1
RC		 1493 if (prot) {
1494 flash_unlock_seq (info, 0);
1495 flash_write_cmd (info, 0,
1496 info->addr_unlock1,
1497 ATM_CMD_SOFTLOCK_START);
1498 flash_unlock_seq (info, 0);
1499 flash_write_cmd (info, sector, 0,
1500 ATM_CMD_LOCK_SECT);
1501 } else {
1502 flash_write_cmd (info, 0,
1503 info->addr_unlock1,
1504 AMD_CMD_UNLOCK_START);
1505 if (info->device_id == ATM_ID_BV6416)
1506 flash_write_cmd (info, sector,
1507 0, ATM_CMD_UNLOCK_SECT);
1508 }
1509 }
11dc4010
KP		 1510 if (info->manufacturer_id ==
1511 ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
66863b05
AG		 1512 int flag = disable_interrupts();
1513 int lock_flag;
1514
1515 flash_unlock_seq(info, 0);
1516 flash_write_cmd(info, 0, info->addr_unlock1,
1517 AMD_CMD_SET_PPB_ENTRY);
1518 lock_flag = flash_isset(info, sector, 0, 0x01);
1519 if (prot) {
1520 if (lock_flag) {
1521 flash_write_cmd(info, sector, 0,
1522 AMD_CMD_PPB_LOCK_BC1);
1523 flash_write_cmd(info, sector, 0,
1524 AMD_CMD_PPB_LOCK_BC2);
1525 }
1526 debug("sector %ld %slocked\n", sector,
1527 lock_flag ? "" : "already ");
1528 } else {
1529 if (!lock_flag) {
1530 debug("unlock %ld\n", sector);
1531 flash_write_cmd(info, 0, 0,
1532 AMD_CMD_PPB_UNLOCK_BC1);
1533 flash_write_cmd(info, 0, 0,
1534 AMD_CMD_PPB_UNLOCK_BC2);
1535 }
1536 debug("sector %ld %sunlocked\n", sector,
1537 !lock_flag ? "" : "already ");
1538 }
1539 if (flag)
1540 enable_interrupts();
1541
1542 if (flash_status_check(info, sector,
1543 info->erase_blk_tout,
1544 prot ? "protect" : "unprotect"))
1545 printf("status check error\n");
1546
1547 flash_write_cmd(info, 0, 0,
1548 AMD_CMD_SET_PPB_EXIT_BC1);
1549 flash_write_cmd(info, 0, 0,
1550 AMD_CMD_SET_PPB_EXIT_BC2);
1551 }
bc9019e1 1552 break;
4e00acde
TL		 1553#ifdef CONFIG_FLASH_CFI_LEGACY
1554 case CFI_CMDSET_AMD_LEGACY:
1555 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1556 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1557 if (prot)
1558 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1559 else
1560 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1561#endif
bc9019e1 1562 };
bf9e3b38 1563
df4e813b
SR		 1564 /*
1565 * Flash needs to be in status register read mode for
1566 * flash_full_status_check() to work correctly
1567 */
1568 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
be60a902
HS		 1569 if ((retcode =
1570 flash_full_status_check (info, sector, info->erase_blk_tout,
1571 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1572
be60a902
HS		 1573 info->protect[sector] = prot;
1574
1575 /*
1576 * On some of Intel's flash chips (marked via legacy_unlock)
1577 * unprotect unprotects all locking.
1578 */
1579 if ((prot == 0) && (info->legacy_unlock)) {
1580 flash_sect_t i;
1581
1582 for (i = 0; i < info->sector_count; i++) {
1583 if (info->protect[i])
1584 flash_real_protect (info, i, 1);
1585 }
5653fc33 1586 }
5653fc33 1587 }
be60a902 1588 return retcode;
5653fc33 1589}
bf9e3b38 1590
5653fc33 1591/*-----------------------------------------------------------------------
be60a902 1592 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1593 */
be60a902
HS		 1594void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1595 int len)
5653fc33 1596{
be60a902
HS		 1597 uchar *src;
1598 uchar *dst;
bf9e3b38 1599
be60a902 1600 dst = buffer;
12d30aa7 1601 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS		 1602 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1603 memcpy (dst, src + offset, len);
1604 flash_write_cmd (info, 0, 0, info->cmd_reset);
a90b9575 1605 udelay(1);
12d30aa7 1606 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1607}
1608
be60a902
HS		 1609/*
1610 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1611 */
be60a902
HS		 1612void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1613 int len)
5653fc33 1614{
be60a902 1615 uchar *src;
bf9e3b38 1616
12d30aa7 1617 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS		 1618 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1619 memcpy (buffer, src + offset, len);
1620 flash_write_cmd (info, 0, 0, info->cmd_reset);
a90b9575 1621 udelay(1);
12d30aa7 1622 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1623}
1624
6d0f6bcf 1625#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1626
0ddf06dd
HS		 1627/*-----------------------------------------------------------------------
1628 * Reverse the order of the erase regions in the CFI QRY structure.
1629 * This is needed for chips that are either a) correctly detected as
1630 * top-boot, or b) buggy.
1631 */
1632static void cfi_reverse_geometry(struct cfi_qry *qry)
1633{
1634 unsigned int i, j;
1635 u32 tmp;
1636
1637 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1638 tmp = qry->erase_region_info[i];
1639 qry->erase_region_info[i] = qry->erase_region_info[j];
1640 qry->erase_region_info[j] = tmp;
1641 }
1642}
be60a902 1643
260421a2
SR		 1644/*-----------------------------------------------------------------------
1645 * read jedec ids from device and set corresponding fields in info struct
1646 *
1647 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1648 *
0ddf06dd
HS		 1649 */
1650static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1651{
1652 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
a90b9575 1653 udelay(1);
0ddf06dd
HS		 1654 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1655 udelay(1000); /* some flash are slow to respond */
1656 info->manufacturer_id = flash_read_uchar (info,
1657 FLASH_OFFSET_MANUFACTURER_ID);
d77c7ac4
PDM		 1658 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
1659 flash_read_word (info, FLASH_OFFSET_DEVICE_ID) :
1660 flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID);
0ddf06dd
HS		 1661 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1662}
1663
1664static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1665{
1666 info->cmd_reset = FLASH_CMD_RESET;
1667
1668 cmdset_intel_read_jedec_ids(info);
1669 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1670
6d0f6bcf 1671#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS		 1672 /* read legacy lock/unlock bit from intel flash */
1673 if (info->ext_addr) {
1674 info->legacy_unlock = flash_read_uchar (info,
1675 info->ext_addr + 5) & 0x08;
1676 }
1677#endif
1678
1679 return 0;
1680}
1681
1682static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1683{
3a7b2c21
NG		 1684 ushort bankId = 0;
1685 uchar manuId;
1686
0ddf06dd
HS		 1687 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1688 flash_unlock_seq(info, 0);
1689 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1690 udelay(1000); /* some flash are slow to respond */
90447ecb 1691
3a7b2c21
NG		 1692 manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID);
1693 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
1694 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) {
1695 bankId += 0x100;
1696 manuId = flash_read_uchar (info,
1697 bankId | FLASH_OFFSET_MANUFACTURER_ID);
1698 }
1699 info->manufacturer_id = manuId;
90447ecb
TK		 1700
1701 switch (info->chipwidth){
1702 case FLASH_CFI_8BIT:
1703 info->device_id = flash_read_uchar (info,
1704 FLASH_OFFSET_DEVICE_ID);
1705 if (info->device_id == 0x7E) {
1706 /* AMD 3-byte (expanded) device ids */
1707 info->device_id2 = flash_read_uchar (info,
1708 FLASH_OFFSET_DEVICE_ID2);
1709 info->device_id2 <<= 8;
1710 info->device_id2 |= flash_read_uchar (info,
1711 FLASH_OFFSET_DEVICE_ID3);
1712 }
1713 break;
1714 case FLASH_CFI_16BIT:
1715 info->device_id = flash_read_word (info,
1716 FLASH_OFFSET_DEVICE_ID);
5b448adb
HS		 1717 if ((info->device_id & 0xff) == 0x7E) {
1718 /* AMD 3-byte (expanded) device ids */
1719 info->device_id2 = flash_read_uchar (info,
1720 FLASH_OFFSET_DEVICE_ID2);
1721 info->device_id2 <<= 8;
1722 info->device_id2 |= flash_read_uchar (info,
1723 FLASH_OFFSET_DEVICE_ID3);
1724 }
90447ecb
TK		 1725 break;
1726 default:
1727 break;
0ddf06dd
HS		 1728 }
1729 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1730 udelay(1);
0ddf06dd
HS		 1731}
1732
1733static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1734{
1735 info->cmd_reset = AMD_CMD_RESET;
1736
1737 cmdset_amd_read_jedec_ids(info);
1738 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1739
66863b05 1740#ifdef CONFIG_SYS_FLASH_PROTECTION
11dc4010
KP		 1741 if (info->ext_addr && info->manufacturer_id ==
1742 ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
66863b05
AG		 1743 ushort spus;
1744
1745 /* read sector protect/unprotect scheme */
1746 spus = flash_read_uchar(info, info->ext_addr + 9);
1747 if (spus == 0x8)
1748 info->legacy_unlock = 1;
1749 }
1750#endif
1751
0ddf06dd
HS		 1752 return 0;
1753}
1754
1755#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR		 1756static void flash_read_jedec_ids (flash_info_t * info)
1757{
1758 info->manufacturer_id = 0;
1759 info->device_id = 0;
1760 info->device_id2 = 0;
1761
1762 switch (info->vendor) {
9c048b52 1763 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1764 case CFI_CMDSET_INTEL_STANDARD:
1765 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1766 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1767 break;
1768 case CFI_CMDSET_AMD_STANDARD:
1769 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1770 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1771 break;
1772 default:
1773 break;
1774 }
1775}
1776
5653fc33 1777/*-----------------------------------------------------------------------
be60a902
HS		 1778 * Call board code to request info about non-CFI flash.
1779 * board_flash_get_legacy needs to fill in at least:
1780 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1781 */
09ce9921 1782static int flash_detect_legacy(phys_addr_t base, int banknum)
5653fc33 1783{
be60a902 1784 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1785
be60a902
HS		 1786 if (board_flash_get_legacy(base, banknum, info)) {
1787 /* board code may have filled info completely. If not, we
1788 use JEDEC ID probing. */
1789 if (!info->vendor) {
1790 int modes[] = {
1791 CFI_CMDSET_AMD_STANDARD,
1792 CFI_CMDSET_INTEL_STANDARD
1793 };
1794 int i;
7e5b9b47 1795
be60a902
HS		 1796 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1797 info->vendor = modes[i];
09ce9921
BB		 1798 info->start[0] =
1799 (ulong)map_physmem(base,
e1fb6d0d 1800 info->portwidth,
09ce9921 1801 MAP_NOCACHE);
be60a902
HS		 1802 if (info->portwidth == FLASH_CFI_8BIT
1803 && info->interface == FLASH_CFI_X8X16) {
1804 info->addr_unlock1 = 0x2AAA;
1805 info->addr_unlock2 = 0x5555;
1806 } else {
1807 info->addr_unlock1 = 0x5555;
1808 info->addr_unlock2 = 0x2AAA;
1809 }
1810 flash_read_jedec_ids(info);
1811 debug("JEDEC PROBE: ID %x %x %x\n",
1812 info->manufacturer_id,
1813 info->device_id,
1814 info->device_id2);
09ce9921 1815 if (jedec_flash_match(info, info->start[0]))
be60a902 1816 break;
09ce9921 1817 else
e1fb6d0d 1818 unmap_physmem((void *)info->start[0],
09ce9921 1819 MAP_NOCACHE);
be60a902
HS		 1820 }
1821 }
1822
1823 switch(info->vendor) {
9c048b52 1824 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1825 case CFI_CMDSET_INTEL_STANDARD:
1826 case CFI_CMDSET_INTEL_EXTENDED:
1827 info->cmd_reset = FLASH_CMD_RESET;
1828 break;
1829 case CFI_CMDSET_AMD_STANDARD:
1830 case CFI_CMDSET_AMD_EXTENDED:
1831 case CFI_CMDSET_AMD_LEGACY:
1832 info->cmd_reset = AMD_CMD_RESET;
1833 break;
1834 }
1835 info->flash_id = FLASH_MAN_CFI;
1836 return 1;
1837 }
1838 return 0; /* use CFI */
1839}
1840#else
09ce9921 1841static inline int flash_detect_legacy(phys_addr_t base, int banknum)
be60a902
HS		 1842{
1843 return 0; /* use CFI */
1844}
1845#endif
1846
1847/*-----------------------------------------------------------------------
1848 * detect if flash is compatible with the Common Flash Interface (CFI)
1849 * http://www.jedec.org/download/search/jesd68.pdf
1850 */
e23741f4
HS		 1851static void flash_read_cfi (flash_info_t *info, void *buf,
1852 unsigned int start, size_t len)
1853{
1854 u8 *p = buf;
1855 unsigned int i;
1856
1857 for (i = 0; i < len; i++)
1858 p[i] = flash_read_uchar(info, start + i);
1859}
1860
11dc4010 1861static void __flash_cmd_reset(flash_info_t *info)
fa36ae79
SR		 1862{
1863 /*
1864 * We do not yet know what kind of commandset to use, so we issue
1865 * the reset command in both Intel and AMD variants, in the hope
1866 * that AMD flash roms ignore the Intel command.
1867 */
1868 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1869 udelay(1);
fa36ae79
SR		 1870 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1871}
1872void flash_cmd_reset(flash_info_t *info)
1873 __attribute__((weak,alias("__flash_cmd_reset")));
1874
e23741f4 1875static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS		 1876{
1877 int cfi_offset;
1878
fa36ae79
SR		 1879 /* Issue FLASH reset command */
1880 flash_cmd_reset(info);
1ba639da 1881
be60a902
HS		 1882 for (cfi_offset=0;
1883 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1884 cfi_offset++) {
1885 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1886 FLASH_CMD_CFI);
1887 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1888 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1889 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS		 1890 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1891 sizeof(struct cfi_qry));
1892 info->interface = le16_to_cpu(qry->interface_desc);
1893
be60a902
HS		 1894 info->cfi_offset = flash_offset_cfi[cfi_offset];
1895 debug ("device interface is %d\n",
1896 info->interface);
1897 debug ("found port %d chip %d ",
1898 info->portwidth, info->chipwidth);
1899 debug ("port %d bits chip %d bits\n",
1900 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1901 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1902
1903 /* calculate command offsets as in the Linux driver */
1904 info->addr_unlock1 = 0x555;
7e5b9b47
HS		 1905 info->addr_unlock2 = 0x2aa;
1906
1907 /*
1908 * modify the unlock address if we are
1909 * in compatibility mode
1910 */
1911 if ( /* x8/x16 in x8 mode */
1912 ((info->chipwidth == FLASH_CFI_BY8) &&
1913 (info->interface == FLASH_CFI_X8X16)) ||
1914 /* x16/x32 in x16 mode */
1915 ((info->chipwidth == FLASH_CFI_BY16) &&
1916 (info->interface == FLASH_CFI_X16X32)))
1917 {
1918 info->addr_unlock1 = 0xaaa;
1919 info->addr_unlock2 = 0x555;
1920 }
1921
1922 info->name = "CFI conformant";
1923 return 1;
1924 }
1925 }
1926
1927 return 0;
1928}
1929
e23741f4 1930static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1931{
bf9e3b38
WD		 1932 debug ("flash detect cfi\n");
1933
6d0f6bcf 1934 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1935 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1936 for (info->chipwidth = FLASH_CFI_BY8;
1937 info->chipwidth <= info->portwidth;
7e5b9b47 1938 info->chipwidth <<= 1)
e23741f4 1939 if (__flash_detect_cfi(info, qry))
7e5b9b47 1940 return 1;
5653fc33 1941 }
bf9e3b38 1942 debug ("not found\n");
5653fc33
WD		 1943 return 0;
1944}
bf9e3b38 1945
467bcee1
HS		 1946/*
1947 * Manufacturer-specific quirks. Add workarounds for geometry
1948 * reversal, etc. here.
1949 */
1950static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1951{
1952 /* check if flash geometry needs reversal */
1953 if (qry->num_erase_regions > 1) {
1954 /* reverse geometry if top boot part */
1955 if (info->cfi_version < 0x3131) {
1956 /* CFI < 1.1, try to guess from device id */
1957 if ((info->device_id & 0x80) != 0)
1958 cfi_reverse_geometry(qry);
1959 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1960 /* CFI >= 1.1, deduct from top/bottom flag */
1961 /* note: ext_addr is valid since cfi_version > 0 */
1962 cfi_reverse_geometry(qry);
1963 }
1964 }
1965}
1966
1967static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1968{
1969 int reverse_geometry = 0;
1970
1971 /* Check the "top boot" bit in the PRI */
1972 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1973 reverse_geometry = 1;
1974
1975 /* AT49BV6416(T) list the erase regions in the wrong order.
1976 * However, the device ID is identical with the non-broken
cb82a532 1977 * AT49BV642D they differ in the high byte.
467bcee1 1978 */
467bcee1
HS		 1979 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1980 reverse_geometry = !reverse_geometry;
467bcee1
HS		 1981
1982 if (reverse_geometry)
1983 cfi_reverse_geometry(qry);
1984}
1985
e8eac437
RR		 1986static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
1987{
1988 /* check if flash geometry needs reversal */
1989 if (qry->num_erase_regions > 1) {
1990 /* reverse geometry if top boot part */
1991 if (info->cfi_version < 0x3131) {
6a011ce8
MF		 1992 /* CFI < 1.1, guess by device id */
1993 if (info->device_id == 0x22CA || /* M29W320DT */
1994 info->device_id == 0x2256 || /* M29W320ET */
1995 info->device_id == 0x22D7) { /* M29W800DT */
e8eac437
RR		 1996 cfi_reverse_geometry(qry);
1997 }
4c2105cb
MF		 1998 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1999 /* CFI >= 1.1, deduct from top/bottom flag */
2000 /* note: ext_addr is valid since cfi_version > 0 */
2001 cfi_reverse_geometry(qry);
e8eac437
RR		 2002 }
2003 }
2004}
2005
5653fc33
WD		 2006/*
2007 * The following code cannot be run from FLASH!
2008 *
2009 */
34bbb8fb 2010ulong flash_get_size (phys_addr_t base, int banknum)
5653fc33 2011{
bf9e3b38 2012 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 2013 int i, j;
2014 flash_sect_t sect_cnt;
09ce9921 2015 phys_addr_t sector;
5653fc33
WD		 2016 unsigned long tmp;
2017 int size_ratio;
2018 uchar num_erase_regions;
bf9e3b38
WD		 2019 int erase_region_size;
2020 int erase_region_count;
e23741f4 2021 struct cfi_qry qry;
34bbb8fb 2022 unsigned long max_size;
260421a2 2023
f979690e
KG		 2024 memset(&qry, 0, sizeof(qry));
2025
260421a2
SR		 2026 info->ext_addr = 0;
2027 info->cfi_version = 0;
6d0f6bcf 2028#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR		 2029 info->legacy_unlock = 0;
2030#endif
5653fc33 2031
09ce9921 2032 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
5653fc33 2033
e23741f4
HS		 2034 if (flash_detect_cfi (info, &qry)) {
2035 info->vendor = le16_to_cpu(qry.p_id);
2036 info->ext_addr = le16_to_cpu(qry.p_adr);
2037 num_erase_regions = qry.num_erase_regions;
2038
260421a2
SR		 2039 if (info->ext_addr) {
2040 info->cfi_version = (ushort) flash_read_uchar (info,
2041 info->ext_addr + 3) << 8;
2042 info->cfi_version |= (ushort) flash_read_uchar (info,
2043 info->ext_addr + 4);
2044 }
0ddf06dd 2045
bf9e3b38 2046#ifdef DEBUG
e23741f4 2047 flash_printqry (&qry);
bf9e3b38 2048#endif
0ddf06dd 2049
bf9e3b38 2050 switch (info->vendor) {
9c048b52 2051 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 2052 case CFI_CMDSET_INTEL_STANDARD:
2053 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 2054 cmdset_intel_init(info, &qry);
5653fc33
WD		 2055 break;
2056 case CFI_CMDSET_AMD_STANDARD:
2057 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 2058 cmdset_amd_init(info, &qry);
5653fc33 2059 break;
0ddf06dd
HS		 2060 default:
2061 printf("CFI: Unknown command set 0x%x\n",
2062 info->vendor);
2063 /*
2064 * Unfortunately, this means we don't know how
2065 * to get the chip back to Read mode. Might
2066 * as well try an Intel-style reset...
2067 */
2068 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
2069 return 0;
5653fc33 2070 }
cd37d9e6 2071
467bcee1
HS		 2072 /* Do manufacturer-specific fixups */
2073 switch (info->manufacturer_id) {
2c9f48af
MS		 2074 case 0x0001: /* AMD */
2075 case 0x0037: /* AMIC */
467bcee1
HS		 2076 flash_fixup_amd(info, &qry);
2077 break;
2078 case 0x001f:
2079 flash_fixup_atmel(info, &qry);
2080 break;
e8eac437
RR		 2081 case 0x0020:
2082 flash_fixup_stm(info, &qry);
2083 break;
467bcee1
HS		 2084 }
2085
bf9e3b38 2086 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR		 2087 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
2088 debug ("device id is 0x%x\n", info->device_id);
2089 debug ("device id2 is 0x%x\n", info->device_id2);
2090 debug ("cfi version is 0x%04x\n", info->cfi_version);
2091
5653fc33 2092 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD		 2093 /* if the chip is x8/x16 reduce the ratio by half */
2094 if ((info->interface == FLASH_CFI_X8X16)
2095 && (info->chipwidth == FLASH_CFI_BY8)) {
2096 size_ratio >>= 1;
2097 }
bf9e3b38
WD		 2098 debug ("size_ratio %d port %d bits chip %d bits\n",
2099 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
2100 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
ec50a8e3
IY		 2101 info->size = 1 << qry.dev_size;
2102 /* multiply the size by the number of chips */
2103 info->size *= size_ratio;
34bbb8fb 2104 max_size = cfi_flash_bank_size(banknum);
ec50a8e3
IY		 2105 if (max_size && (info->size > max_size)) {
2106 debug("[truncated from %ldMiB]", info->size >> 20);
2107 info->size = max_size;
2108 }
bf9e3b38 2109 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 2110 sect_cnt = 0;
2111 sector = base;
bf9e3b38
WD		 2112 for (i = 0; i < num_erase_regions; i++) {
2113 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD		 2114 printf ("%d erase regions found, only %d used\n",
2115 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 2116 break;
2117 }
e23741f4 2118
0ddf06dd
HS		 2119 tmp = le32_to_cpu(qry.erase_region_info[i]);
2120 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 2121
2122 erase_region_count = (tmp & 0xffff) + 1;
2123 tmp >>= 16;
bf9e3b38
WD		 2124 erase_region_size =
2125 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 2126 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 2127 erase_region_count, erase_region_size);
bf9e3b38 2128 for (j = 0; j < erase_region_count; j++) {
ec50a8e3
IY		 2129 if (sector - base >= info->size)
2130 break;
6d0f6bcf 2131 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS		 2132 printf("ERROR: too many flash sectors\n");
2133 break;
2134 }
09ce9921
BB		 2135 info->start[sect_cnt] =
2136 (ulong)map_physmem(sector,
2137 info->portwidth,
2138 MAP_NOCACHE);
5653fc33 2139 sector += (erase_region_size * size_ratio);
a1191902
WD		 2140
2141 /*
7e5b9b47
HS		 2142 * Only read protection status from
2143 * supported devices (intel...)
a1191902
WD		 2144 */
2145 switch (info->vendor) {
9c048b52 2146 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 2147 case CFI_CMDSET_INTEL_EXTENDED:
2148 case CFI_CMDSET_INTEL_STANDARD:
df4e813b
SR		 2149 /*
2150 * Set flash to read-id mode. Otherwise
2151 * reading protected status is not
2152 * guaranteed.
2153 */
2154 flash_write_cmd(info, sect_cnt, 0,
2155 FLASH_CMD_READ_ID);
a1191902
WD		 2156 info->protect[sect_cnt] =
2157 flash_isset (info, sect_cnt,
2158 FLASH_OFFSET_PROTECT,
2159 FLASH_STATUS_PROTECT);
2160 break;
2161 default:
7e5b9b47
HS		 2162 /* default: not protected */
2163 info->protect[sect_cnt] = 0;
a1191902
WD		 2164 }
2165
5653fc33
WD		 2166 sect_cnt++;
2167 }
2168 }
2169
2170 info->sector_count = sect_cnt;
e23741f4
HS		 2171 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
2172 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 2173 info->erase_blk_tout = tmp *
e23741f4
HS		 2174 (1 << qry.block_erase_timeout_max);
2175 tmp = (1 << qry.buf_write_timeout_typ) *
2176 (1 << qry.buf_write_timeout_max);
2177
7e5b9b47 2178 /* round up when converting to ms */
e23741f4
HS		 2179 info->buffer_write_tout = (tmp + 999) / 1000;
2180 tmp = (1 << qry.word_write_timeout_typ) *
2181 (1 << qry.word_write_timeout_max);
7e5b9b47 2182 /* round up when converting to ms */
e23741f4 2183 info->write_tout = (tmp + 999) / 1000;
5653fc33 2184 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS		 2185 if ((info->interface == FLASH_CFI_X8X16) &&
2186 (info->chipwidth == FLASH_CFI_BY8)) {
2187 /* XXX - Need to test on x8/x16 in parallel. */
2188 info->portwidth >>= 1;
855a496f 2189 }
2215987e
MF		 2190
2191 flash_write_cmd (info, 0, 0, info->cmd_reset);
5653fc33
WD		 2192 }
2193
bf9e3b38 2194 return (info->size);
5653fc33
WD		 2195}
2196
4ffeab2c 2197#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef
PZ		 2198void flash_set_verbose(uint v)
2199{
2200 flash_verbose = v;
2201}
4ffeab2c 2202#endif
6ea808ef 2203
6f726f95
SR		 2204static void cfi_flash_set_config_reg(u32 base, u16 val)
2205{
2206#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
2207 /*
2208 * Only set this config register if really defined
2209 * to a valid value (0xffff is invalid)
2210 */
2211 if (val == 0xffff)
2212 return;
2213
2214 /*
2215 * Set configuration register. Data is "encrypted" in the 16 lower
2216 * address bits.
2217 */
2218 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
2219 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
2220
2221 /*
2222 * Finally issue reset-command to bring device back to
2223 * read-array mode
2224 */
2225 flash_write16(FLASH_CMD_RESET, (void *)base);
2226#endif
2227}
2228
5653fc33
WD		 2229/*-----------------------------------------------------------------------
2230 */
6ee1416e
HS		 2231
2232void flash_protect_default(void)
2233{
2c51983b
PT		 2234#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2235 int i;
2236 struct apl_s {
2237 ulong start;
2238 ulong size;
2239 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
2240#endif
2241
6ee1416e
HS		 2242 /* Monitor protection ON by default */
2243#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
2244 (!defined(CONFIG_MONITOR_IS_IN_RAM))
2245 flash_protect(FLAG_PROTECT_SET,
2246 CONFIG_SYS_MONITOR_BASE,
2247 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2248 flash_get_info(CONFIG_SYS_MONITOR_BASE));
2249#endif
2250
2251 /* Environment protection ON by default */
2252#ifdef CONFIG_ENV_IS_IN_FLASH
2253 flash_protect(FLAG_PROTECT_SET,
2254 CONFIG_ENV_ADDR,
2255 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2256 flash_get_info(CONFIG_ENV_ADDR));
2257#endif
2258
2259 /* Redundant environment protection ON by default */
2260#ifdef CONFIG_ENV_ADDR_REDUND
2261 flash_protect(FLAG_PROTECT_SET,
2262 CONFIG_ENV_ADDR_REDUND,
2263 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
2264 flash_get_info(CONFIG_ENV_ADDR_REDUND));
2265#endif
2266
2267#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2268 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
31d34143 2269 debug("autoprotecting from %08lx to %08lx\n",
6ee1416e
HS		 2270 apl[i].start, apl[i].start + apl[i].size - 1);
2271 flash_protect(FLAG_PROTECT_SET,
2272 apl[i].start,
2273 apl[i].start + apl[i].size - 1,
2274 flash_get_info(apl[i].start));
2275 }
2276#endif
2277}
2278
be60a902 2279unsigned long flash_init (void)
5653fc33 2280{
be60a902
HS		 2281 unsigned long size = 0;
2282 int i;
5653fc33 2283
6d0f6bcf 2284#ifdef CONFIG_SYS_FLASH_PROTECTION
3a3baf3e
ES		 2285 /* read environment from EEPROM */
2286 char s[64];
cdb74977 2287 getenv_f("unlock", s, sizeof(s));
81b20ccc 2288#endif
5653fc33 2289
be60a902 2290 /* Init: no FLASHes known */
6d0f6bcf 2291 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
be60a902 2292 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 2293
6f726f95
SR		 2294 /* Optionally write flash configuration register */
2295 cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
2296 cfi_flash_config_reg(i));
2297
b00e19cc 2298 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
34bbb8fb 2299 flash_get_size(cfi_flash_bank_addr(i), i);
be60a902
HS		 2300 size += flash_info[i].size;
2301 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 2302#ifndef CONFIG_SYS_FLASH_QUIET_TEST
eddf52b5 2303 printf ("## Unknown flash on Bank %d "
be60a902
HS		 2304 "- Size = 0x%08lx = %ld MB\n",
2305 i+1, flash_info[i].size,
0e3fa01a 2306 flash_info[i].size >> 20);
6d0f6bcf 2307#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 2308 }
6d0f6bcf 2309#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS		 2310 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
2311 /*
2312 * Only the U-Boot image and it's environment
2313 * is protected, all other sectors are
2314 * unprotected (unlocked) if flash hardware
6d0f6bcf 2315 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS		 2316 * and the environment variable "unlock" is
2317 * set to "yes".
2318 */
2319 if (flash_info[i].legacy_unlock) {
2320 int k;
5653fc33 2321
be60a902
HS		 2322 /*
2323 * Disable legacy_unlock temporarily,
2324 * since flash_real_protect would
2325 * relock all other sectors again
2326 * otherwise.
2327 */
2328 flash_info[i].legacy_unlock = 0;
5653fc33 2329
be60a902
HS		 2330 /*
2331 * Legacy unlocking (e.g. Intel J3) ->
2332 * unlock only one sector. This will
2333 * unlock all sectors.
2334 */
2335 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 2336
be60a902 2337 flash_info[i].legacy_unlock = 1;
5653fc33 2338
be60a902
HS		 2339 /*
2340 * Manually mark other sectors as
2341 * unlocked (unprotected)
2342 */
2343 for (k = 1; k < flash_info[i].sector_count; k++)
2344 flash_info[i].protect[k] = 0;
2345 } else {
2346 /*
2347 * No legancy unlocking -> unlock all sectors
2348 */
2349 flash_protect (FLAG_PROTECT_CLEAR,
2350 flash_info[i].start[0],
2351 flash_info[i].start[0]
2352 + flash_info[i].size - 1,
2353 &flash_info[i]);
79b4cda0 2354 }
79b4cda0 2355 }
6d0f6bcf 2356#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2357 }
79b4cda0 2358
6ee1416e 2359 flash_protect_default();
91809ed5
PZ		 2360#ifdef CONFIG_FLASH_CFI_MTD
2361 cfi_mtd_init();
2362#endif
2363
be60a902 2364 return (size);
5653fc33 2365}
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