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[J-u-boot.git] / arch / powerpc / include / asm / immap_83xx.h
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f046ccd1 1/*
d29d17d7 2 * Copyright 2004-2011 Freescale Semiconductor, Inc.
f6eda7f8
DL		 3 *
4 * MPC83xx Internal Memory Map
5 *
e080313c
DL		 6 * Contributors:
7 * Dave Liu <[email protected]>
8 * Tanya Jiang <[email protected]>
9 * Mandy Lavi <[email protected]>
10 * Eran Liberty <[email protected]>
f6eda7f8 11 *
1a459660 12 * SPDX-License-Identifier: GPL-2.0+
f046ccd1 13 */
f6eda7f8
DL		 14#ifndef __IMMAP_83xx__
15#define __IMMAP_83xx__
f046ccd1
EL		 16
17#include <asm/types.h>
be5e6181 18#include <asm/fsl_i2c.h>
04a9e118 19#include <asm/mpc8xxx_spi.h>
4e190b03 20#include <asm/fsl_lbc.h>
e94e460c 21#include <asm/fsl_dma.h>
f046ccd1 22
de1d0a69 23/*
e080313c 24 * Local Access Window
f046ccd1 25 */
f6eda7f8 26typedef struct law83xx {
b701652a 27 u32 bar; /* LBIU local access window base address register */
b701652a 28 u32 ar; /* LBIU local access window attribute register */
f6eda7f8 29} law83xx_t;
f046ccd1 30
de1d0a69 31/*
e080313c 32 * System configuration registers
f046ccd1 33 */
f6eda7f8 34typedef struct sysconf83xx {
b701652a 35 u32 immrbar; /* Internal memory map base address register */
f046ccd1 36 u8 res0[0x04];
b701652a 37 u32 altcbar; /* Alternate configuration base address register */
f046ccd1 38 u8 res1[0x14];
b701652a 39 law83xx_t lblaw[4]; /* LBIU local access window */
f046ccd1 40 u8 res2[0x20];
b701652a 41 law83xx_t pcilaw[2]; /* PCI local access window */
fd6646c0
AV		 42 u8 res3[0x10];
43 law83xx_t pcielaw[2]; /* PCI Express local access window */
44 u8 res4[0x10];
b701652a 45 law83xx_t ddrlaw[2]; /* DDR local access window */
fd6646c0 46 u8 res5[0x50];
b701652a
DL		 47 u32 sgprl; /* System General Purpose Register Low */
48 u32 sgprh; /* System General Purpose Register High */
49 u32 spridr; /* System Part and Revision ID Register */
fd6646c0 50 u8 res6[0x04];
b701652a 51 u32 spcr; /* System Priority Configuration Register */
e080313c
DL		 52 u32 sicrl; /* System I/O Configuration Register Low */
53 u32 sicrh; /* System I/O Configuration Register High */
fd6646c0 54 u8 res7[0x04];
002d27ca
NS		 55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
56 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
24c3aca3
DL		 57 u32 ddrcdr; /* DDR Control Driver Register */
58 u32 ddrdsr; /* DDR Debug Status Register */
03051c3d 59 u32 obir; /* Output Buffer Impedance Register */
fd6646c0
AV		 60 u8 res8[0xC];
61 u32 pecr1; /* PCI Express control register 1 */
8afad91f
GF		 62#if defined(CONFIG_MPC830x)
63 u32 sdhccr; /* eSDHC Control Registers for MPC830x */
7c619ddc 64#else
fd6646c0 65 u32 pecr2; /* PCI Express control register 2 */
7c619ddc 66#endif
a88731a6
GF		 67#if defined(CONFIG_MPC8309)
68 u32 can_dbg_ctrl;
69 u32 res9a;
70 u32 gpr1;
71 u8 res9b[0xAC];
72#else
fd6646c0 73 u8 res9[0xB8];
a88731a6 74#endif
f6eda7f8 75} sysconf83xx_t;
f046ccd1 76
de1d0a69 77/*
f046ccd1
EL		 78 * Watch Dog Timer (WDT) Registers
79 */
f6eda7f8 80typedef struct wdt83xx {
de1d0a69 81 u8 res0[4];
b701652a
DL		 82 u32 swcrr; /* System watchdog control register */
83 u32 swcnr; /* System watchdog count register */
de1d0a69 84 u8 res1[2];
b701652a 85 u16 swsrr; /* System watchdog service register */
f046ccd1 86 u8 res2[0xF0];
f6eda7f8 87} wdt83xx_t;
de1d0a69 88
f046ccd1
EL		 89/*
90 * RTC/PIT Module Registers
91 */
f6eda7f8 92typedef struct rtclk83xx {
b701652a 93 u32 cnr; /* control register */
b701652a 94 u32 ldr; /* load register */
b701652a 95 u32 psr; /* prescale register */
e080313c 96 u32 ctr; /* counter value field register */
b701652a 97 u32 evr; /* event register */
b701652a 98 u32 alr; /* alarm register */
f046ccd1 99 u8 res0[0xE8];
f6eda7f8 100} rtclk83xx_t;
f046ccd1
EL		 101
102/*
e080313c 103 * Global timer module
f046ccd1 104 */
f6eda7f8 105typedef struct gtm83xx {
e080313c 106 u8 cfr1; /* Timer1/2 Configuration */
b701652a 107 u8 res0[3];
e080313c 108 u8 cfr2; /* Timer3/4 Configuration */
63063cc7 109 u8 res1[11];
e080313c
DL		 110 u16 mdr1; /* Timer1 Mode Register */
111 u16 mdr2; /* Timer2 Mode Register */
112 u16 rfr1; /* Timer1 Reference Register */
113 u16 rfr2; /* Timer2 Reference Register */
114 u16 cpr1; /* Timer1 Capture Register */
115 u16 cpr2; /* Timer2 Capture Register */
116 u16 cnr1; /* Timer1 Counter Register */
117 u16 cnr2; /* Timer2 Counter Register */
118 u16 mdr3; /* Timer3 Mode Register */
119 u16 mdr4; /* Timer4 Mode Register */
120 u16 rfr3; /* Timer3 Reference Register */
121 u16 rfr4; /* Timer4 Reference Register */
122 u16 cpr3; /* Timer3 Capture Register */
123 u16 cpr4; /* Timer4 Capture Register */
124 u16 cnr3; /* Timer3 Counter Register */
125 u16 cnr4; /* Timer4 Counter Register */
126 u16 evr1; /* Timer1 Event Register */
127 u16 evr2; /* Timer2 Event Register */
128 u16 evr3; /* Timer3 Event Register */
129 u16 evr4; /* Timer4 Event Register */
130 u16 psr1; /* Timer1 Prescaler Register */
131 u16 psr2; /* Timer2 Prescaler Register */
132 u16 psr3; /* Timer3 Prescaler Register */
133 u16 psr4; /* Timer4 Prescaler Register */
b701652a 134 u8 res[0xC0];
f6eda7f8 135} gtm83xx_t;
f046ccd1
EL		 136
137/*
138 * Integrated Programmable Interrupt Controller
139 */
f6eda7f8 140typedef struct ipic83xx {
e080313c
DL		 141 u32 sicfr; /* System Global Interrupt Configuration Register */
142 u32 sivcr; /* System Global Interrupt Vector Register */
143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
144 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
145 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
4713db66
JH		 146 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
147 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
e080313c
DL		 148 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
149 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
150 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
4713db66 151 u32 sicnr; /* System Internal Interrupt Control Register */
e080313c
DL		 152 u32 sepnr; /* System External Interrupt Pending Register */
153 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
154 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
155 u32 semsr; /* System External Interrupt Mask Register */
156 u32 secnr; /* System External Interrupt Control Register */
157 u32 sersr; /* System Error Status Register */
158 u32 sermr; /* System Error Mask Register */
159 u32 sercr; /* System Error Control Register */
4713db66 160 u32 sepcr; /* System External Interrupt Polarity Control Register */
e080313c
DL		 161 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
162 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
163 u32 sefcr; /* System External Interrupt Force Register */
164 u32 serfr; /* System Error Force Register */
b701652a 165 u32 scvcr; /* System Critical Interrupt Vector Register */
b701652a 166 u32 smvcr; /* System Management Interrupt Vector Register */
4713db66 167 u8 res[0x98];
f6eda7f8 168} ipic83xx_t;
f046ccd1
EL		 169
170/*
171 * System Arbiter Registers
172 */
f6eda7f8 173typedef struct arbiter83xx {
b701652a 174 u32 acr; /* Arbiter Configuration Register */
b701652a 175 u32 atr; /* Arbiter Timers Register */
f046ccd1 176 u8 res[4];
e080313c
DL		 177 u32 aer; /* Arbiter Event Register */
178 u32 aidr; /* Arbiter Interrupt Definition Register */
179 u32 amr; /* Arbiter Mask Register */
b701652a 180 u32 aeatr; /* Arbiter Event Attributes Register */
b701652a 181 u32 aeadr; /* Arbiter Event Address Register */
e080313c 182 u32 aerr; /* Arbiter Event Response Register */
f046ccd1 183 u8 res1[0xDC];
f6eda7f8 184} arbiter83xx_t;
f046ccd1
EL		 185
186/*
187 * Reset Module
188 */
f6eda7f8 189typedef struct reset83xx {
e080313c
DL		 190 u32 rcwl; /* Reset Configuration Word Low Register */
191 u32 rcwh; /* Reset Configuration Word High Register */
b701652a 192 u8 res0[8];
e080313c
DL		 193 u32 rsr; /* Reset Status Register */
194 u32 rmr; /* Reset Mode Register */
195 u32 rpr; /* Reset protection Register */
196 u32 rcr; /* Reset Control Register */
197 u32 rcer; /* Reset Control Enable Register */
b701652a 198 u8 res1[0xDC];
f6eda7f8 199} reset83xx_t;
de1d0a69 200
e080313c
DL		 201/*
202 * Clock Module
203 */
f6eda7f8 204typedef struct clk83xx {
e080313c
DL		 205 u32 spmr; /* system PLL mode Register */
206 u32 occr; /* output clock control Register */
207 u32 sccr; /* system clock control Register */
b701652a 208 u8 res0[0xF4];
f6eda7f8 209} clk83xx_t;
f046ccd1
EL		 210
211/*
212 * Power Management Control Module
213 */
f6eda7f8 214typedef struct pmc83xx {
e080313c
DL		 215 u32 pmccr; /* PMC Configuration Register */
216 u32 pmcer; /* PMC Event Register */
217 u32 pmcmr; /* PMC Mask Register */
d87c57b2
SW		 218 u32 pmccr1; /* PMC Configuration Register 1 */
219 u32 pmccr2; /* PMC Configuration Register 2 */
220 u8 res0[0xEC];
f6eda7f8 221} pmc83xx_t;
f046ccd1
EL		 222
223/*
e080313c 224 * General purpose I/O module
f046ccd1 225 */
f6eda7f8 226typedef struct gpio83xx {
b701652a
DL		 227 u32 dir; /* direction register */
228 u32 odr; /* open drain register */
229 u32 dat; /* data register */
230 u32 ier; /* interrupt event register */
231 u32 imr; /* interrupt mask register */
232 u32 icr; /* external interrupt control register */
f046ccd1 233 u8 res0[0xE8];
f6eda7f8 234} gpio83xx_t;
b701652a 235
b701652a
DL		 236/*
237 * QE Ports Interrupts Registers
238 */
239typedef struct qepi83xx {
240 u8 res0[0xC];
241 u32 qepier; /* QE Ports Interrupt Event Register */
b701652a 242 u32 qepimr; /* QE Ports Interrupt Mask Register */
b701652a 243 u32 qepicr; /* QE Ports Interrupt Control Register */
b701652a
DL		 244 u8 res1[0xE8];
245} qepi83xx_t;
246
247/*
e080313c 248 * QE Parallel I/O Ports
b701652a
DL		 249 */
250typedef struct gpio_n {
251 u32 podr; /* Open Drain Register */
252 u32 pdat; /* Data Register */
253 u32 dir1; /* direction register 1 */
254 u32 dir2; /* direction register 2 */
255 u32 ppar1; /* Pin Assignment Register 1 */
256 u32 ppar2; /* Pin Assignment Register 2 */
257} gpio_n_t;
258
e080313c 259typedef struct qegpio83xx {
b701652a
DL		 260 gpio_n_t ioport[0x7];
261 u8 res0[0x358];
e080313c 262} qepio83xx_t;
b701652a
DL		 263
264/*
265 * QE Secondary Bus Access Windows
266 */
b701652a
DL		 267typedef struct qesba83xx {
268 u32 lbmcsar; /* Local bus memory controller start address */
b701652a 269 u32 sdmcsar; /* Secondary DDR memory controller start address */
b701652a
DL		 270 u8 res0[0x38];
271 u32 lbmcear; /* Local bus memory controller end address */
b701652a 272 u32 sdmcear; /* Secondary DDR memory controller end address */
b701652a 273 u8 res1[0x38];
e080313c 274 u32 lbmcar; /* Local bus memory controller attributes */
b701652a 275 u32 sdmcar; /* Secondary DDR memory controller attributes */
e080313c 276 u8 res2[0x378];
b701652a 277} qesba83xx_t;
f046ccd1 278
de1d0a69 279/*
f046ccd1
EL		 280 * DDR Memory Controller Memory Map
281 */
d29d17d7
YS		 282#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
283typedef struct ccsr_ddr {
284 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
285 u8 res1[4];
286 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
287 u8 res2[4];
288 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
289 u8 res3[4];
290 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
291 u8 res4[100];
292 u32 cs0_config; /* Chip Select Configuration */
293 u32 cs1_config; /* Chip Select Configuration */
294 u32 cs2_config; /* Chip Select Configuration */
295 u32 cs3_config; /* Chip Select Configuration */
296 u8 res4a[48];
297 u32 cs0_config_2; /* Chip Select Configuration 2 */
298 u32 cs1_config_2; /* Chip Select Configuration 2 */
299 u32 cs2_config_2; /* Chip Select Configuration 2 */
300 u32 cs3_config_2; /* Chip Select Configuration 2 */
301 u8 res5[48];
302 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
303 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
304 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
305 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
306 u32 sdram_cfg; /* SDRAM Control Configuration */
307 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
308 u32 sdram_mode; /* SDRAM Mode Configuration */
309 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
310 u32 sdram_md_cntl; /* SDRAM Mode Control */
311 u32 sdram_interval; /* SDRAM Interval Configuration */
312 u32 sdram_data_init; /* SDRAM Data initialization */
313 u8 res6[4];
314 u32 sdram_clk_cntl; /* SDRAM Clock Control */
315 u8 res7[20];
316 u32 init_addr; /* training init addr */
317 u32 init_ext_addr; /* training init extended addr */
318 u8 res8_1[16];
319 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
320 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
321 u8 reg8_1a[8];
322 u32 ddr_zq_cntl; /* ZQ calibration control*/
323 u32 ddr_wrlvl_cntl; /* write leveling control*/
324 u8 reg8_1aa[4];
325 u32 ddr_sr_cntr; /* self refresh counter */
326 u32 ddr_sdram_rcw_1; /* Control Words 1 */
327 u32 ddr_sdram_rcw_2; /* Control Words 2 */
328 u8 reg_1ab[8];
329 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
330 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
331 u8 res8_1b[104];
332 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
333 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
334 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
335 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
336 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
337 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
338 u8 res8_1ba[0x908];
339 u32 ddr_dsr1; /* Debug Status 1 */
340 u32 ddr_dsr2; /* Debug Status 2 */
341 u32 ddr_cdr1; /* Control Driver 1 */
342 u32 ddr_cdr2; /* Control Driver 2 */
343 u8 res8_1c[200];
344 u32 ip_rev1; /* IP Block Revision 1 */
345 u32 ip_rev2; /* IP Block Revision 2 */
346 u32 eor; /* Enhanced Optimization Register */
347 u8 res8_2[252];
348 u32 mtcr; /* Memory Test Control Register */
349 u8 res8_3[28];
350 u32 mtp1; /* Memory Test Pattern 1 */
351 u32 mtp2; /* Memory Test Pattern 2 */
352 u32 mtp3; /* Memory Test Pattern 3 */
353 u32 mtp4; /* Memory Test Pattern 4 */
354 u32 mtp5; /* Memory Test Pattern 5 */
355 u32 mtp6; /* Memory Test Pattern 6 */
356 u32 mtp7; /* Memory Test Pattern 7 */
357 u32 mtp8; /* Memory Test Pattern 8 */
358 u32 mtp9; /* Memory Test Pattern 9 */
359 u32 mtp10; /* Memory Test Pattern 10 */
360 u8 res8_4[184];
361 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
362 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
363 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
364 u8 res9[20];
365 u32 capture_data_hi; /* Data Path Read Capture High */
366 u32 capture_data_lo; /* Data Path Read Capture Low */
367 u32 capture_ecc; /* Data Path Read Capture ECC */
368 u8 res10[20];
369 u32 err_detect; /* Error Detect */
370 u32 err_disable; /* Error Disable */
371 u32 err_int_en;
372 u32 capture_attributes; /* Error Attrs Capture */
373 u32 capture_address; /* Error Addr Capture */
374 u32 capture_ext_address; /* Error Extended Addr Capture */
375 u32 err_sbe; /* Single-Bit ECC Error Management */
376 u8 res11[164];
377 u32 debug[32]; /* debug_1 to debug_32 */
378 u8 res12[128];
379} ccsr_ddr_t;
380#else
b701652a 381typedef struct ddr_cs_bnds {
de1d0a69 382 u32 csbnds;
b701652a 383 u8 res0[4];
f046ccd1
EL		 384} ddr_cs_bnds_t;
385
f6eda7f8 386typedef struct ddr83xx {
e080313c 387 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
de1d0a69 388 u8 res0[0x60];
e080313c 389 u32 cs_config[4]; /* Chip Select x Configuration */
24c3aca3
DL		 390 u8 res1[0x70];
391 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
392 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
e080313c
DL		 393 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
394 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
395 u32 sdram_cfg; /* SDRAM Control Configuration */
24c3aca3 396 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
e080313c 397 u32 sdram_mode; /* SDRAM Mode Configuration */
24c3aca3
DL		 398 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
399 u32 sdram_md_cntl; /* SDRAM Mode Control */
e080313c 400 u32 sdram_interval; /* SDRAM Interval Configuration */
24c3aca3
DL		 401 u32 ddr_data_init; /* SDRAM Data Initialization */
402 u8 res2[4];
403 u32 sdram_clk_cntl; /* SDRAM Clock Control */
404 u8 res3[0x14];
405 u32 ddr_init_addr; /* DDR training initialization address */
406 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
407 u8 res4[0xAA8];
408 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
409 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
410 u8 res5[0x200];
e080313c
DL		 411 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
412 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
413 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
24c3aca3 414 u8 res6[0x14];
e080313c
DL		 415 u32 capture_data_hi; /* Memory Data Path Read Capture High */
416 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
417 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
24c3aca3 418 u8 res7[0x14];
e080313c
DL		 419 u32 err_detect; /* Memory Error Detect */
420 u32 err_disable; /* Memory Error Disable */
421 u32 err_int_en; /* Memory Error Interrupt Enable */
422 u32 capture_attributes; /* Memory Error Attributes Capture */
423 u32 capture_address; /* Memory Error Address Capture */
424 u32 capture_ext_address;/* Memory Error Extended Address Capture */
425 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
24c3aca3 426 u8 res8[0xA4];
f046ccd1 427 u32 debug_reg;
24c3aca3 428 u8 res9[0xFC];
f6eda7f8 429} ddr83xx_t;
d29d17d7 430#endif
f046ccd1 431
f046ccd1
EL		 432/*
433 * DUART
434 */
b701652a 435typedef struct duart83xx {
e080313c
DL		 436 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
437 u8 uier_udmb; /* combined register for UIER and UDMB */
438 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
439 u8 ulcr; /* line control register */
440 u8 umcr; /* MODEM control register */
441 u8 ulsr; /* line status register */
442 u8 umsr; /* MODEM status register */
443 u8 uscr; /* scratch register */
de1d0a69 444 u8 res0[8];
e080313c 445 u8 udsr; /* DMA status register */
de1d0a69
JL		 446 u8 res1[3];
447 u8 res2[0xEC];
f6eda7f8 448} duart83xx_t;
f046ccd1 449
61f25155
MB		 450/*
451 * DMA/Messaging Unit
452 */
f6eda7f8 453typedef struct dma83xx {
b701652a
DL		 454 u32 res0[0xC]; /* 0x0-0x29 reseverd */
455 u32 omisr; /* 0x30 Outbound message interrupt status register */
456 u32 omimr; /* 0x34 Outbound message interrupt mask register */
457 u32 res1[0x6]; /* 0x38-0x49 reserved */
b701652a
DL		 458 u32 imr0; /* 0x50 Inbound message register 0 */
459 u32 imr1; /* 0x54 Inbound message register 1 */
460 u32 omr0; /* 0x58 Outbound message register 0 */
461 u32 omr1; /* 0x5C Outbound message register 1 */
b701652a
DL		 462 u32 odr; /* 0x60 Outbound doorbell register */
463 u32 res2; /* 0x64-0x67 reserved */
464 u32 idr; /* 0x68 Inbound doorbell register */
465 u32 res3[0x5]; /* 0x6C-0x79 reserved */
b701652a
DL		 466 u32 imisr; /* 0x80 Inbound message interrupt status register */
467 u32 imimr; /* 0x84 Inbound message interrupt mask register */
468 u32 res4[0x1E]; /* 0x88-0x99 reserved */
e94e460c 469 struct fsl_dma dma[4];
f6eda7f8 470} dma83xx_t;
f046ccd1
EL		 471
472/*
473 * PCI Software Configuration Registers
474 */
f6eda7f8 475typedef struct pciconf83xx {
b701652a 476 u32 config_address;
f046ccd1
EL		 477 u32 config_data;
478 u32 int_ack;
b701652a 479 u8 res[116];
f6eda7f8 480} pciconf83xx_t;
f046ccd1
EL		 481
482/*
483 * PCI Outbound Translation Register
484 */
485typedef struct pci_outbound_window {
b701652a
DL		 486 u32 potar;
487 u8 res0[4];
488 u32 pobar;
489 u8 res1[4];
490 u32 pocmr;
491 u8 res2[4];
f6eda7f8 492} pot83xx_t;
b701652a 493
f046ccd1
EL		 494/*
495 * Sequencer
de1d0a69 496 */
f6eda7f8 497typedef struct ios83xx {
b701652a 498 pot83xx_t pot[6];
b701652a
DL		 499 u8 res0[0x60];
500 u32 pmcr;
501 u8 res1[4];
502 u32 dtcr;
503 u8 res2[4];
f6eda7f8 504} ios83xx_t;
f046ccd1
EL		 505
506/*
507 * PCI Controller Control and Status Registers
508 */
f6eda7f8 509typedef struct pcictrl83xx {
b701652a 510 u32 esr;
b701652a 511 u32 ecdr;
f046ccd1 512 u32 eer;
b701652a 513 u32 eatcr;
b701652a
DL		 514 u32 eacr;
515 u32 eeacr;
b701652a
DL		 516 u32 edlcr;
517 u32 edhcr;
b701652a
DL		 518 u32 gcr;
519 u32 ecr;
520 u32 gsr;
521 u8 res0[12];
522 u32 pitar2;
523 u8 res1[4];
524 u32 pibar2;
525 u32 piebar2;
526 u32 piwar2;
527 u8 res2[4];
528 u32 pitar1;
529 u8 res3[4];
530 u32 pibar1;
531 u32 piebar1;
532 u32 piwar1;
533 u8 res4[4];
534 u32 pitar0;
535 u8 res5[4];
536 u32 pibar0;
537 u8 res6[4];
538 u32 piwar0;
539 u8 res7[132];
f6eda7f8 540} pcictrl83xx_t;
f046ccd1
EL		 541
542/*
de1d0a69 543 * USB
f046ccd1 544 */
f6eda7f8 545typedef struct usb83xx {
d87c57b2 546 u8 fixme[0x1000];
f6eda7f8 547} usb83xx_t;
f046ccd1
EL		 548
549/*
550 * TSEC
551 */
f6eda7f8 552typedef struct tsec83xx {
f046ccd1 553 u8 fixme[0x1000];
f6eda7f8 554} tsec83xx_t;
f046ccd1
EL		 555
556/*
557 * Security
558 */
f6eda7f8 559typedef struct security83xx {
f046ccd1 560 u8 fixme[0x10000];
f6eda7f8 561} security83xx_t;
f046ccd1 562
03051c3d
DL		 563/*
564 * PCI Express
565 */
fd6646c0
AV		 566struct pex_inbound_window {
567 u32 ar;
568 u32 tar;
569 u32 barl;
570 u32 barh;
571};
572
573struct pex_outbound_window {
574 u32 ar;
575 u32 bar;
576 u32 tarl;
577 u32 tarh;
578};
579
580struct pex_csb_bridge {
581 u32 pex_csb_ver;
582 u32 pex_csb_cab;
583 u32 pex_csb_ctrl;
584 u8 res0[8];
585 u32 pex_dms_dstmr;
586 u8 res1[4];
587 u32 pex_cbs_stat;
588 u8 res2[0x20];
589 u32 pex_csb_obctrl;
590 u32 pex_csb_obstat;
591 u8 res3[0x98];
592 u32 pex_csb_ibctrl;
593 u32 pex_csb_ibstat;
594 u8 res4[0xb8];
595 u32 pex_wdma_ctrl;
596 u32 pex_wdma_addr;
597 u32 pex_wdma_stat;
598 u8 res5[0x94];
599 u32 pex_rdma_ctrl;
600 u32 pex_rdma_addr;
601 u32 pex_rdma_stat;
602 u8 res6[0xd4];
603 u32 pex_ombcr;
604 u32 pex_ombdr;
605 u8 res7[0x38];
606 u32 pex_imbcr;
607 u32 pex_imbdr;
608 u8 res8[0x38];
609 u32 pex_int_enb;
610 u32 pex_int_stat;
611 u32 pex_int_apio_vec1;
612 u32 pex_int_apio_vec2;
613 u8 res9[0x10];
614 u32 pex_int_ppio_vec1;
615 u32 pex_int_ppio_vec2;
616 u32 pex_int_wdma_vec1;
617 u32 pex_int_wdma_vec2;
618 u32 pex_int_rdma_vec1;
619 u32 pex_int_rdma_vec2;
620 u32 pex_int_misc_vec;
621 u8 res10[4];
622 u32 pex_int_axi_pio_enb;
623 u32 pex_int_axi_wdma_enb;
624 u32 pex_int_axi_rdma_enb;
625 u32 pex_int_axi_misc_enb;
626 u32 pex_int_axi_pio_stat;
627 u32 pex_int_axi_wdma_stat;
628 u32 pex_int_axi_rdma_stat;
629 u32 pex_int_axi_misc_stat;
630 u8 res11[0xa0];
631 struct pex_outbound_window pex_outbound_win[4];
632 u8 res12[0x100];
633 u32 pex_epiwtar0;
634 u32 pex_epiwtar1;
635 u32 pex_epiwtar2;
636 u32 pex_epiwtar3;
637 u8 res13[0x70];
638 struct pex_inbound_window pex_inbound_win[4];
639};
640
03051c3d 641typedef struct pex83xx {
fd6646c0
AV		 642 u8 pex_cfg_header[0x404];
643 u32 pex_ltssm_stat;
644 u8 res0[0x30];
645 u32 pex_ack_replay_timeout;
646 u8 res1[4];
647 u32 pex_gclk_ratio;
648 u8 res2[0xc];
649 u32 pex_pm_timer;
650 u32 pex_pme_timeout;
651 u8 res3[4];
652 u32 pex_aspm_req_timer;
653 u8 res4[0x18];
654 u32 pex_ssvid_update;
655 u8 res5[0x34];
656 u32 pex_cfg_ready;
657 u8 res6[0x24];
658 u32 pex_bar_sizel;
659 u8 res7[4];
660 u32 pex_bar_sel;
661 u8 res8[0x20];
662 u32 pex_bar_pf;
663 u8 res9[0x88];
664 u32 pex_pme_to_ack_tor;
665 u8 res10[0xc];
666 u32 pex_ss_intr_mask;
667 u8 res11[0x25c];
668 struct pex_csb_bridge bridge;
669 u8 res12[0x160];
03051c3d
DL		 670} pex83xx_t;
671
672/*
673 * SATA
674 */
675typedef struct sata83xx {
676 u8 fixme[0x1000];
677} sata83xx_t;
678
679/*
680 * eSDHC
681 */
682typedef struct sdhc83xx {
683 u8 fixme[0x1000];
684} sdhc83xx_t;
685
686/*
687 * SerDes
688 */
689typedef struct serdes83xx {
7c619ddc
IY		 690 u32 srdscr0;
691 u32 srdscr1;
692 u32 srdscr2;
693 u32 srdscr3;
694 u32 srdscr4;
695 u8 res0[0xc];
696 u32 srdsrstctl;
697 u8 res1[0xdc];
03051c3d
DL		 698} serdes83xx_t;
699
700/*
701 * On Chip ROM
702 */
703typedef struct rom83xx {
a88731a6
GF		 704#if defined(CONFIG_MPC8309)
705 u8 mem[0x8000];
706#else
03051c3d 707 u8 mem[0x10000];
a88731a6 708#endif
03051c3d
DL		 709} rom83xx_t;
710
555da617
DL		 711/*
712 * TDM
713 */
714typedef struct tdm83xx {
715 u8 fixme[0x200];
716} tdm83xx_t;
717
718/*
719 * TDM DMAC
720 */
721typedef struct tdmdmac83xx {
722 u8 fixme[0x2000];
723} tdmdmac83xx_t;
724
2c7920af 725#if defined(CONFIG_MPC834x)
e080313c
DL		 726typedef struct immap {
727 sysconf83xx_t sysconf; /* System configuration */
728 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
729 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
730 rtclk83xx_t pit; /* Periodic Interval Timer */
731 gtm83xx_t gtm[2]; /* Global Timers Module */
732 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
733 arbiter83xx_t arbiter; /* System Arbiter Registers */
734 reset83xx_t reset; /* Reset Module */
735 clk83xx_t clk; /* System Clock Module */
736 pmc83xx_t pmc; /* Power Management Control Module */
737 gpio83xx_t gpio[2]; /* General purpose I/O module */
738 u8 res0[0x200];
739 u8 dll_ddr[0x100];
740 u8 dll_lbc[0x100];
741 u8 res1[0xE00];
d29d17d7
YS		 742#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
743 ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
744#else
745 ddr83xx_t ddr; /* DDR Memory Controller Memory */
746#endif
e080313c
DL		 747 fsl_i2c_t i2c[2]; /* I2C Controllers */
748 u8 res2[0x1300];
749 duart83xx_t duart[2]; /* DUART */
750 u8 res3[0x900];
f51cdaf1 751 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c 752 u8 res4[0x1000];
04a9e118 753 spi8xxx_t spi; /* Serial Peripheral Interface */
e080313c
DL		 754 dma83xx_t dma; /* DMA */
755 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
756 ios83xx_t ios; /* Sequencer */
757 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
758 u8 res5[0x19900];
d87c57b2
SW		 759 usb83xx_t usb[2];
760 tsec83xx_t tsec[2];
761 u8 res6[0xA000];
762 security83xx_t security;
763 u8 res7[0xC0000];
764} immap_t;
765
d89e1c36 766#ifdef CONFIG_HAS_FSL_MPH_USB
77354e9d 767#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
768#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
d89e1c36 769#else
77354e9d 770#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
771#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
d89e1c36
VG		 772#endif
773
555da617 774#elif defined(CONFIG_MPC8313)
d87c57b2
SW		 775typedef struct immap {
776 sysconf83xx_t sysconf; /* System configuration */
777 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
778 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
779 rtclk83xx_t pit; /* Periodic Interval Timer */
780 gtm83xx_t gtm[2]; /* Global Timers Module */
781 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
782 arbiter83xx_t arbiter; /* System Arbiter Registers */
783 reset83xx_t reset; /* Reset Module */
784 clk83xx_t clk; /* System Clock Module */
785 pmc83xx_t pmc; /* Power Management Control Module */
786 gpio83xx_t gpio[1]; /* General purpose I/O module */
787 u8 res0[0x1300];
788 ddr83xx_t ddr; /* DDR Memory Controller Memory */
789 fsl_i2c_t i2c[2]; /* I2C Controllers */
790 u8 res1[0x1300];
791 duart83xx_t duart[2]; /* DUART */
792 u8 res2[0x900];
f51cdaf1 793 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
d87c57b2 794 u8 res3[0x1000];
04a9e118 795 spi8xxx_t spi; /* Serial Peripheral Interface */
d87c57b2
SW		 796 dma83xx_t dma; /* DMA */
797 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
798 u8 res4[0x80];
799 ios83xx_t ios; /* Sequencer */
800 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
801 u8 res5[0x1aa00];
802 usb83xx_t usb[1];
e080313c
DL		 803 tsec83xx_t tsec[2];
804 u8 res6[0xA000];
805 security83xx_t security;
806 u8 res7[0xC0000];
807} immap_t;
b701652a 808
7c619ddc 809#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
555da617
DL		 810typedef struct immap {
811 sysconf83xx_t sysconf; /* System configuration */
812 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
813 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
814 rtclk83xx_t pit; /* Periodic Interval Timer */
815 gtm83xx_t gtm[2]; /* Global Timers Module */
816 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
817 arbiter83xx_t arbiter; /* System Arbiter Registers */
818 reset83xx_t reset; /* Reset Module */
819 clk83xx_t clk; /* System Clock Module */
820 pmc83xx_t pmc; /* Power Management Control Module */
821 gpio83xx_t gpio[1]; /* General purpose I/O module */
822 u8 res0[0x1300];
823 ddr83xx_t ddr; /* DDR Memory Controller Memory */
824 fsl_i2c_t i2c[2]; /* I2C Controllers */
825 u8 res1[0x1300];
826 duart83xx_t duart[2]; /* DUART */
827 u8 res2[0x900];
f51cdaf1 828 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
555da617 829 u8 res3[0x1000];
04a9e118 830 spi8xxx_t spi; /* Serial Peripheral Interface */
555da617
DL		 831 dma83xx_t dma; /* DMA */
832 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
833 u8 res4[0x80];
834 ios83xx_t ios; /* Sequencer */
835 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
836 u8 res5[0xa00];
837 pex83xx_t pciexp[2]; /* PCI Express Controller */
838 u8 res6[0xb000];
839 tdm83xx_t tdm; /* TDM Controller */
840 u8 res7[0x1e00];
841 sata83xx_t sata[2]; /* SATA Controller */
842 u8 res8[0x9000];
843 usb83xx_t usb[1]; /* USB DR Controller */
844 tsec83xx_t tsec[2];
845 u8 res9[0x6000];
846 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
847 u8 res10[0x2000];
848 security83xx_t security;
849 u8 res11[0xA3000];
850 serdes83xx_t serdes[1]; /* SerDes Registers */
851 u8 res12[0x1CF00];
852} immap_t;
853
2c7920af 854#elif defined(CONFIG_MPC837x)
03051c3d
DL		 855typedef struct immap {
856 sysconf83xx_t sysconf; /* System configuration */
857 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
858 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
859 rtclk83xx_t pit; /* Periodic Interval Timer */
860 gtm83xx_t gtm[2]; /* Global Timers Module */
861 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
862 arbiter83xx_t arbiter; /* System Arbiter Registers */
863 reset83xx_t reset; /* Reset Module */
864 clk83xx_t clk; /* System Clock Module */
865 pmc83xx_t pmc; /* Power Management Control Module */
866 gpio83xx_t gpio[2]; /* General purpose I/O module */
867 u8 res0[0x1200];
868 ddr83xx_t ddr; /* DDR Memory Controller Memory */
869 fsl_i2c_t i2c[2]; /* I2C Controllers */
870 u8 res1[0x1300];
871 duart83xx_t duart[2]; /* DUART */
872 u8 res2[0x900];
f51cdaf1 873 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
03051c3d 874 u8 res3[0x1000];
04a9e118 875 spi8xxx_t spi; /* Serial Peripheral Interface */
03051c3d
DL		 876 dma83xx_t dma; /* DMA */
877 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
878 u8 res4[0x80];
879 ios83xx_t ios; /* Sequencer */
880 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
881 u8 res5[0xa00];
882 pex83xx_t pciexp[2]; /* PCI Express Controller */
883 u8 res6[0xd000];
884 sata83xx_t sata[4]; /* SATA Controller */
885 u8 res7[0x7000];
886 usb83xx_t usb[1]; /* USB DR Controller */
887 tsec83xx_t tsec[2];
888 u8 res8[0x8000];
889 sdhc83xx_t sdhc; /* SDHC Controller */
890 u8 res9[0x1000];
891 security83xx_t security;
892 u8 res10[0xA3000];
893 serdes83xx_t serdes[2]; /* SerDes Registers */
894 u8 res11[0xCE00];
895 rom83xx_t rom; /* On Chip ROM */
896} immap_t;
897
e080313c 898#elif defined(CONFIG_MPC8360)
f046ccd1 899typedef struct immap {
e080313c
DL		 900 sysconf83xx_t sysconf; /* System configuration */
901 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
902 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
903 rtclk83xx_t pit; /* Periodic Interval Timer */
904 u8 res0[0x200];
905 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
906 arbiter83xx_t arbiter; /* System Arbiter Registers */
907 reset83xx_t reset; /* Reset Module */
908 clk83xx_t clk; /* System Clock Module */
909 pmc83xx_t pmc; /* Power Management Control Module */
910 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
911 u8 res1[0x300];
912 u8 dll_ddr[0x100];
913 u8 dll_lbc[0x100];
914 u8 res2[0x200];
915 qepio83xx_t qepio; /* QE Parallel I/O ports */
916 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
917 u8 res3[0x400];
918 ddr83xx_t ddr; /* DDR Memory Controller Memory */
919 fsl_i2c_t i2c[2]; /* I2C Controllers */
920 u8 res4[0x1300];
921 duart83xx_t duart[2]; /* DUART */
922 u8 res5[0x900];
f51cdaf1 923 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c
DL		 924 u8 res6[0x2000];
925 dma83xx_t dma; /* DMA */
926 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
927 u8 res7[128];
928 ios83xx_t ios; /* Sequencer (IOS) */
929 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
930 u8 res8[0x4A00];
931 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
932 u8 res9[0x22000];
933 security83xx_t security;
934 u8 res10[0xC0000];
935 u8 qe[0x100000]; /* QE block */
f046ccd1 936} immap_t;
24c3aca3 937
2c7920af 938#elif defined(CONFIG_MPC832x)
24c3aca3
DL		 939typedef struct immap {
940 sysconf83xx_t sysconf; /* System configuration */
941 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
942 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
943 rtclk83xx_t pit; /* Periodic Interval Timer */
944 gtm83xx_t gtm[2]; /* Global Timers Module */
945 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
946 arbiter83xx_t arbiter; /* System Arbiter Registers */
947 reset83xx_t reset; /* Reset Module */
948 clk83xx_t clk; /* System Clock Module */
949 pmc83xx_t pmc; /* Power Management Control Module */
950 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
951 u8 res0[0x300];
952 u8 dll_ddr[0x100];
953 u8 dll_lbc[0x100];
954 u8 res1[0x200];
955 qepio83xx_t qepio; /* QE Parallel I/O ports */
956 u8 res2[0x800];
957 ddr83xx_t ddr; /* DDR Memory Controller Memory */
958 fsl_i2c_t i2c[2]; /* I2C Controllers */
959 u8 res3[0x1300];
960 duart83xx_t duart[2]; /* DUART */
961 u8 res4[0x900];
f51cdaf1 962 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
24c3aca3
DL		 963 u8 res5[0x2000];
964 dma83xx_t dma; /* DMA */
965 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
966 u8 res6[128];
967 ios83xx_t ios; /* Sequencer (IOS) */
968 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
969 u8 res7[0x27A00];
970 security83xx_t security;
971 u8 res8[0xC0000];
972 u8 qe[0x100000]; /* QE block */
973} immap_t;
a88731a6
GF		 974#elif defined(CONFIG_MPC8309)
975typedef struct immap {
976 sysconf83xx_t sysconf; /* System configuration */
977 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
978 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
979 rtclk83xx_t pit; /* Periodic Interval Timer */
980 gtm83xx_t gtm[2]; /* Global Timers Module */
981 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
982 arbiter83xx_t arbiter; /* System Arbiter Registers */
983 reset83xx_t reset; /* Reset Module */
984 clk83xx_t clk; /* System Clock Module */
985 pmc83xx_t pmc; /* Power Management Control Module */
986 gpio83xx_t gpio[2]; /* General purpose I/O module */
987 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
988 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
989 qepio83xx_t qepio; /* QE Parallel I/O ports */
990 u8 res1[0x800];
991 ddr83xx_t ddr; /* DDR Memory Controller Memory */
992 fsl_i2c_t i2c[2]; /* I2C Controllers */
993 u8 res2[0x1300];
994 duart83xx_t duart[2]; /* DUART */
995 u8 res3[0x200];
996 duart83xx_t duart1[2]; /* DUART */
997 u8 res4[0x500];
998 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
999 u8 res5[0x1000];
1000 u8 spi[0x100];
1001 u8 res6[0xf00];
1002 dma83xx_t dma; /* DMA */
1003 pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
1004 u8 res7[0x80];
1005 ios83xx_t ios; /* Sequencer (IOS) */
1006 pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
1007 u8 res8[0x13A00];
1008 u8 can1[0x1000]; /* Flexcan 1 */
1009 u8 can2[0x1000]; /* Flexcan 2 */
1010 u8 res9[0x5000];
1011 usb83xx_t usb;
1012 u8 res10[0x5000];
1013 u8 can3[0x1000]; /* Flexcan 3 */
1014 u8 can4[0x1000]; /* Flexcan 4 */
1015 u8 res11[0x1000];
1016 u8 dma1[0x2000]; /* DMA */
1017 sdhc83xx_t sdhc; /* SDHC Controller */
1018 u8 res12[0xC1000];
1019 rom83xx_t rom; /* On Chip ROM */
1020 u8 res13[0x8000];
1021 u8 qe[0x100000]; /* QE block */
1022 u8 res14[0xE00000];/* Added for 8309 */
1023} immap_t;
e080313c 1024#endif
f046ccd1 1025
e76cd5d4
AF		 1026#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
1027#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
1028 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
e94e460c 1029#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
d29d17d7
YS		 1030#define CONFIG_SYS_MPC83xx_DMA_ADDR \
1031 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
e1ac387f 1032#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
d29d17d7
YS		 1033#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
1034 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
d89e1c36 1035
77354e9d 1036#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
1037#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
1038#endif
1039#define CONFIG_SYS_MPC83xx_USB1_ADDR \
1040 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
1041#if defined(CONFIG_MPC834x)
1042#define CONFIG_SYS_MPC83xx_USB2_ADDR \
1043 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
d89e1c36 1044#endif
f51cdaf1 1045#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
b9e186fc
SG		 1046
1047#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e 1048#define CONFIG_SYS_MDIO1_OFFSET 0x24000
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SG		 1049
1050#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1051#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
b701652a 1052#endif /* __IMMAP_83xx__ */
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