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cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
[J-u-boot.git] / arch / powerpc / include / asm / immap_83xx.h
CommitLineData
f046ccd1 1/*
d29d17d7 2 * Copyright 2004-2011 Freescale Semiconductor, Inc.
f6eda7f8
DL		 3 *
4 * MPC83xx Internal Memory Map
5 *
e080313c
DL		 6 * Contributors:
7 * Dave Liu <[email protected]>
8 * Tanya Jiang <[email protected]>
9 * Mandy Lavi <[email protected]>
10 * Eran Liberty <[email protected]>
f6eda7f8
DL		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
e080313c 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
f6eda7f8
DL		 20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
de1d0a69 26 *
f046ccd1 27 */
f6eda7f8
DL		 28#ifndef __IMMAP_83xx__
29#define __IMMAP_83xx__
f046ccd1
EL		 30
31#include <asm/types.h>
be5e6181 32#include <asm/fsl_i2c.h>
04a9e118 33#include <asm/mpc8xxx_spi.h>
4e190b03 34#include <asm/fsl_lbc.h>
e94e460c 35#include <asm/fsl_dma.h>
f046ccd1 36
de1d0a69 37/*
e080313c 38 * Local Access Window
f046ccd1 39 */
f6eda7f8 40typedef struct law83xx {
b701652a 41 u32 bar; /* LBIU local access window base address register */
b701652a 42 u32 ar; /* LBIU local access window attribute register */
f6eda7f8 43} law83xx_t;
f046ccd1 44
de1d0a69 45/*
e080313c 46 * System configuration registers
f046ccd1 47 */
f6eda7f8 48typedef struct sysconf83xx {
b701652a 49 u32 immrbar; /* Internal memory map base address register */
f046ccd1 50 u8 res0[0x04];
b701652a 51 u32 altcbar; /* Alternate configuration base address register */
f046ccd1 52 u8 res1[0x14];
b701652a 53 law83xx_t lblaw[4]; /* LBIU local access window */
f046ccd1 54 u8 res2[0x20];
b701652a 55 law83xx_t pcilaw[2]; /* PCI local access window */
fd6646c0
AV		 56 u8 res3[0x10];
57 law83xx_t pcielaw[2]; /* PCI Express local access window */
58 u8 res4[0x10];
b701652a 59 law83xx_t ddrlaw[2]; /* DDR local access window */
fd6646c0 60 u8 res5[0x50];
b701652a
DL		 61 u32 sgprl; /* System General Purpose Register Low */
62 u32 sgprh; /* System General Purpose Register High */
63 u32 spridr; /* System Part and Revision ID Register */
fd6646c0 64 u8 res6[0x04];
b701652a 65 u32 spcr; /* System Priority Configuration Register */
e080313c
DL		 66 u32 sicrl; /* System I/O Configuration Register Low */
67 u32 sicrh; /* System I/O Configuration Register High */
fd6646c0 68 u8 res7[0x04];
002d27ca
NS		 69 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
70 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
24c3aca3
DL		 71 u32 ddrcdr; /* DDR Control Driver Register */
72 u32 ddrdsr; /* DDR Debug Status Register */
03051c3d 73 u32 obir; /* Output Buffer Impedance Register */
fd6646c0
AV		 74 u8 res8[0xC];
75 u32 pecr1; /* PCI Express control register 1 */
7c619ddc
IY		 76#ifdef CONFIG_MPC8308
77 u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
78#else
fd6646c0 79 u32 pecr2; /* PCI Express control register 2 */
7c619ddc 80#endif
fd6646c0 81 u8 res9[0xB8];
f6eda7f8 82} sysconf83xx_t;
f046ccd1 83
de1d0a69 84/*
f046ccd1
EL		 85 * Watch Dog Timer (WDT) Registers
86 */
f6eda7f8 87typedef struct wdt83xx {
de1d0a69 88 u8 res0[4];
b701652a
DL		 89 u32 swcrr; /* System watchdog control register */
90 u32 swcnr; /* System watchdog count register */
de1d0a69 91 u8 res1[2];
b701652a 92 u16 swsrr; /* System watchdog service register */
f046ccd1 93 u8 res2[0xF0];
f6eda7f8 94} wdt83xx_t;
de1d0a69 95
f046ccd1
EL		 96/*
97 * RTC/PIT Module Registers
98 */
f6eda7f8 99typedef struct rtclk83xx {
b701652a 100 u32 cnr; /* control register */
b701652a 101 u32 ldr; /* load register */
b701652a 102 u32 psr; /* prescale register */
e080313c 103 u32 ctr; /* counter value field register */
b701652a 104 u32 evr; /* event register */
b701652a 105 u32 alr; /* alarm register */
f046ccd1 106 u8 res0[0xE8];
f6eda7f8 107} rtclk83xx_t;
f046ccd1
EL		 108
109/*
e080313c 110 * Global timer module
f046ccd1 111 */
f6eda7f8 112typedef struct gtm83xx {
e080313c 113 u8 cfr1; /* Timer1/2 Configuration */
b701652a 114 u8 res0[3];
e080313c 115 u8 cfr2; /* Timer3/4 Configuration */
63063cc7 116 u8 res1[11];
e080313c
DL		 117 u16 mdr1; /* Timer1 Mode Register */
118 u16 mdr2; /* Timer2 Mode Register */
119 u16 rfr1; /* Timer1 Reference Register */
120 u16 rfr2; /* Timer2 Reference Register */
121 u16 cpr1; /* Timer1 Capture Register */
122 u16 cpr2; /* Timer2 Capture Register */
123 u16 cnr1; /* Timer1 Counter Register */
124 u16 cnr2; /* Timer2 Counter Register */
125 u16 mdr3; /* Timer3 Mode Register */
126 u16 mdr4; /* Timer4 Mode Register */
127 u16 rfr3; /* Timer3 Reference Register */
128 u16 rfr4; /* Timer4 Reference Register */
129 u16 cpr3; /* Timer3 Capture Register */
130 u16 cpr4; /* Timer4 Capture Register */
131 u16 cnr3; /* Timer3 Counter Register */
132 u16 cnr4; /* Timer4 Counter Register */
133 u16 evr1; /* Timer1 Event Register */
134 u16 evr2; /* Timer2 Event Register */
135 u16 evr3; /* Timer3 Event Register */
136 u16 evr4; /* Timer4 Event Register */
137 u16 psr1; /* Timer1 Prescaler Register */
138 u16 psr2; /* Timer2 Prescaler Register */
139 u16 psr3; /* Timer3 Prescaler Register */
140 u16 psr4; /* Timer4 Prescaler Register */
b701652a 141 u8 res[0xC0];
f6eda7f8 142} gtm83xx_t;
f046ccd1
EL		 143
144/*
145 * Integrated Programmable Interrupt Controller
146 */
f6eda7f8 147typedef struct ipic83xx {
e080313c
DL		 148 u32 sicfr; /* System Global Interrupt Configuration Register */
149 u32 sivcr; /* System Global Interrupt Vector Register */
150 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
151 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
152 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
4713db66
JH		 153 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
154 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
e080313c
DL		 155 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
156 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
157 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
4713db66 158 u32 sicnr; /* System Internal Interrupt Control Register */
e080313c
DL		 159 u32 sepnr; /* System External Interrupt Pending Register */
160 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
161 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
162 u32 semsr; /* System External Interrupt Mask Register */
163 u32 secnr; /* System External Interrupt Control Register */
164 u32 sersr; /* System Error Status Register */
165 u32 sermr; /* System Error Mask Register */
166 u32 sercr; /* System Error Control Register */
4713db66 167 u32 sepcr; /* System External Interrupt Polarity Control Register */
e080313c
DL		 168 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
169 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
170 u32 sefcr; /* System External Interrupt Force Register */
171 u32 serfr; /* System Error Force Register */
b701652a 172 u32 scvcr; /* System Critical Interrupt Vector Register */
b701652a 173 u32 smvcr; /* System Management Interrupt Vector Register */
4713db66 174 u8 res[0x98];
f6eda7f8 175} ipic83xx_t;
f046ccd1
EL		 176
177/*
178 * System Arbiter Registers
179 */
f6eda7f8 180typedef struct arbiter83xx {
b701652a 181 u32 acr; /* Arbiter Configuration Register */
b701652a 182 u32 atr; /* Arbiter Timers Register */
f046ccd1 183 u8 res[4];
e080313c
DL		 184 u32 aer; /* Arbiter Event Register */
185 u32 aidr; /* Arbiter Interrupt Definition Register */
186 u32 amr; /* Arbiter Mask Register */
b701652a 187 u32 aeatr; /* Arbiter Event Attributes Register */
b701652a 188 u32 aeadr; /* Arbiter Event Address Register */
e080313c 189 u32 aerr; /* Arbiter Event Response Register */
f046ccd1 190 u8 res1[0xDC];
f6eda7f8 191} arbiter83xx_t;
f046ccd1
EL		 192
193/*
194 * Reset Module
195 */
f6eda7f8 196typedef struct reset83xx {
e080313c
DL		 197 u32 rcwl; /* Reset Configuration Word Low Register */
198 u32 rcwh; /* Reset Configuration Word High Register */
b701652a 199 u8 res0[8];
e080313c
DL		 200 u32 rsr; /* Reset Status Register */
201 u32 rmr; /* Reset Mode Register */
202 u32 rpr; /* Reset protection Register */
203 u32 rcr; /* Reset Control Register */
204 u32 rcer; /* Reset Control Enable Register */
b701652a 205 u8 res1[0xDC];
f6eda7f8 206} reset83xx_t;
de1d0a69 207
e080313c
DL		 208/*
209 * Clock Module
210 */
f6eda7f8 211typedef struct clk83xx {
e080313c
DL		 212 u32 spmr; /* system PLL mode Register */
213 u32 occr; /* output clock control Register */
214 u32 sccr; /* system clock control Register */
b701652a 215 u8 res0[0xF4];
f6eda7f8 216} clk83xx_t;
f046ccd1
EL		 217
218/*
219 * Power Management Control Module
220 */
f6eda7f8 221typedef struct pmc83xx {
e080313c
DL		 222 u32 pmccr; /* PMC Configuration Register */
223 u32 pmcer; /* PMC Event Register */
224 u32 pmcmr; /* PMC Mask Register */
d87c57b2
SW		 225 u32 pmccr1; /* PMC Configuration Register 1 */
226 u32 pmccr2; /* PMC Configuration Register 2 */
227 u8 res0[0xEC];
f6eda7f8 228} pmc83xx_t;
f046ccd1
EL		 229
230/*
e080313c 231 * General purpose I/O module
f046ccd1 232 */
f6eda7f8 233typedef struct gpio83xx {
b701652a
DL		 234 u32 dir; /* direction register */
235 u32 odr; /* open drain register */
236 u32 dat; /* data register */
237 u32 ier; /* interrupt event register */
238 u32 imr; /* interrupt mask register */
239 u32 icr; /* external interrupt control register */
f046ccd1 240 u8 res0[0xE8];
f6eda7f8 241} gpio83xx_t;
b701652a 242
b701652a
DL		 243/*
244 * QE Ports Interrupts Registers
245 */
246typedef struct qepi83xx {
247 u8 res0[0xC];
248 u32 qepier; /* QE Ports Interrupt Event Register */
b701652a 249 u32 qepimr; /* QE Ports Interrupt Mask Register */
b701652a 250 u32 qepicr; /* QE Ports Interrupt Control Register */
b701652a
DL		 251 u8 res1[0xE8];
252} qepi83xx_t;
253
254/*
e080313c 255 * QE Parallel I/O Ports
b701652a
DL		 256 */
257typedef struct gpio_n {
258 u32 podr; /* Open Drain Register */
259 u32 pdat; /* Data Register */
260 u32 dir1; /* direction register 1 */
261 u32 dir2; /* direction register 2 */
262 u32 ppar1; /* Pin Assignment Register 1 */
263 u32 ppar2; /* Pin Assignment Register 2 */
264} gpio_n_t;
265
e080313c 266typedef struct qegpio83xx {
b701652a
DL		 267 gpio_n_t ioport[0x7];
268 u8 res0[0x358];
e080313c 269} qepio83xx_t;
b701652a
DL		 270
271/*
272 * QE Secondary Bus Access Windows
273 */
b701652a
DL		 274typedef struct qesba83xx {
275 u32 lbmcsar; /* Local bus memory controller start address */
b701652a 276 u32 sdmcsar; /* Secondary DDR memory controller start address */
b701652a
DL		 277 u8 res0[0x38];
278 u32 lbmcear; /* Local bus memory controller end address */
b701652a 279 u32 sdmcear; /* Secondary DDR memory controller end address */
b701652a 280 u8 res1[0x38];
e080313c 281 u32 lbmcar; /* Local bus memory controller attributes */
b701652a 282 u32 sdmcar; /* Secondary DDR memory controller attributes */
e080313c 283 u8 res2[0x378];
b701652a 284} qesba83xx_t;
f046ccd1 285
de1d0a69 286/*
f046ccd1
EL		 287 * DDR Memory Controller Memory Map
288 */
d29d17d7
YS		 289#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
290typedef struct ccsr_ddr {
291 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
292 u8 res1[4];
293 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
294 u8 res2[4];
295 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
296 u8 res3[4];
297 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
298 u8 res4[100];
299 u32 cs0_config; /* Chip Select Configuration */
300 u32 cs1_config; /* Chip Select Configuration */
301 u32 cs2_config; /* Chip Select Configuration */
302 u32 cs3_config; /* Chip Select Configuration */
303 u8 res4a[48];
304 u32 cs0_config_2; /* Chip Select Configuration 2 */
305 u32 cs1_config_2; /* Chip Select Configuration 2 */
306 u32 cs2_config_2; /* Chip Select Configuration 2 */
307 u32 cs3_config_2; /* Chip Select Configuration 2 */
308 u8 res5[48];
309 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
310 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
311 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
312 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
313 u32 sdram_cfg; /* SDRAM Control Configuration */
314 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
315 u32 sdram_mode; /* SDRAM Mode Configuration */
316 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
317 u32 sdram_md_cntl; /* SDRAM Mode Control */
318 u32 sdram_interval; /* SDRAM Interval Configuration */
319 u32 sdram_data_init; /* SDRAM Data initialization */
320 u8 res6[4];
321 u32 sdram_clk_cntl; /* SDRAM Clock Control */
322 u8 res7[20];
323 u32 init_addr; /* training init addr */
324 u32 init_ext_addr; /* training init extended addr */
325 u8 res8_1[16];
326 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
327 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
328 u8 reg8_1a[8];
329 u32 ddr_zq_cntl; /* ZQ calibration control*/
330 u32 ddr_wrlvl_cntl; /* write leveling control*/
331 u8 reg8_1aa[4];
332 u32 ddr_sr_cntr; /* self refresh counter */
333 u32 ddr_sdram_rcw_1; /* Control Words 1 */
334 u32 ddr_sdram_rcw_2; /* Control Words 2 */
335 u8 reg_1ab[8];
336 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
337 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
338 u8 res8_1b[104];
339 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
340 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
341 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
342 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
343 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
344 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
345 u8 res8_1ba[0x908];
346 u32 ddr_dsr1; /* Debug Status 1 */
347 u32 ddr_dsr2; /* Debug Status 2 */
348 u32 ddr_cdr1; /* Control Driver 1 */
349 u32 ddr_cdr2; /* Control Driver 2 */
350 u8 res8_1c[200];
351 u32 ip_rev1; /* IP Block Revision 1 */
352 u32 ip_rev2; /* IP Block Revision 2 */
353 u32 eor; /* Enhanced Optimization Register */
354 u8 res8_2[252];
355 u32 mtcr; /* Memory Test Control Register */
356 u8 res8_3[28];
357 u32 mtp1; /* Memory Test Pattern 1 */
358 u32 mtp2; /* Memory Test Pattern 2 */
359 u32 mtp3; /* Memory Test Pattern 3 */
360 u32 mtp4; /* Memory Test Pattern 4 */
361 u32 mtp5; /* Memory Test Pattern 5 */
362 u32 mtp6; /* Memory Test Pattern 6 */
363 u32 mtp7; /* Memory Test Pattern 7 */
364 u32 mtp8; /* Memory Test Pattern 8 */
365 u32 mtp9; /* Memory Test Pattern 9 */
366 u32 mtp10; /* Memory Test Pattern 10 */
367 u8 res8_4[184];
368 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
369 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
370 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
371 u8 res9[20];
372 u32 capture_data_hi; /* Data Path Read Capture High */
373 u32 capture_data_lo; /* Data Path Read Capture Low */
374 u32 capture_ecc; /* Data Path Read Capture ECC */
375 u8 res10[20];
376 u32 err_detect; /* Error Detect */
377 u32 err_disable; /* Error Disable */
378 u32 err_int_en;
379 u32 capture_attributes; /* Error Attrs Capture */
380 u32 capture_address; /* Error Addr Capture */
381 u32 capture_ext_address; /* Error Extended Addr Capture */
382 u32 err_sbe; /* Single-Bit ECC Error Management */
383 u8 res11[164];
384 u32 debug[32]; /* debug_1 to debug_32 */
385 u8 res12[128];
386} ccsr_ddr_t;
387#else
b701652a 388typedef struct ddr_cs_bnds {
de1d0a69 389 u32 csbnds;
b701652a 390 u8 res0[4];
f046ccd1
EL		 391} ddr_cs_bnds_t;
392
f6eda7f8 393typedef struct ddr83xx {
e080313c 394 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
de1d0a69 395 u8 res0[0x60];
e080313c 396 u32 cs_config[4]; /* Chip Select x Configuration */
24c3aca3
DL		 397 u8 res1[0x70];
398 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
399 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
e080313c
DL		 400 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
401 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
402 u32 sdram_cfg; /* SDRAM Control Configuration */
24c3aca3 403 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
e080313c 404 u32 sdram_mode; /* SDRAM Mode Configuration */
24c3aca3
DL		 405 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
406 u32 sdram_md_cntl; /* SDRAM Mode Control */
e080313c 407 u32 sdram_interval; /* SDRAM Interval Configuration */
24c3aca3
DL		 408 u32 ddr_data_init; /* SDRAM Data Initialization */
409 u8 res2[4];
410 u32 sdram_clk_cntl; /* SDRAM Clock Control */
411 u8 res3[0x14];
412 u32 ddr_init_addr; /* DDR training initialization address */
413 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
414 u8 res4[0xAA8];
415 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
416 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
417 u8 res5[0x200];
e080313c
DL		 418 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
419 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
420 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
24c3aca3 421 u8 res6[0x14];
e080313c
DL		 422 u32 capture_data_hi; /* Memory Data Path Read Capture High */
423 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
424 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
24c3aca3 425 u8 res7[0x14];
e080313c
DL		 426 u32 err_detect; /* Memory Error Detect */
427 u32 err_disable; /* Memory Error Disable */
428 u32 err_int_en; /* Memory Error Interrupt Enable */
429 u32 capture_attributes; /* Memory Error Attributes Capture */
430 u32 capture_address; /* Memory Error Address Capture */
431 u32 capture_ext_address;/* Memory Error Extended Address Capture */
432 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
24c3aca3 433 u8 res8[0xA4];
f046ccd1 434 u32 debug_reg;
24c3aca3 435 u8 res9[0xFC];
f6eda7f8 436} ddr83xx_t;
d29d17d7 437#endif
f046ccd1 438
f046ccd1
EL		 439/*
440 * DUART
441 */
b701652a 442typedef struct duart83xx {
e080313c
DL		 443 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
444 u8 uier_udmb; /* combined register for UIER and UDMB */
445 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
446 u8 ulcr; /* line control register */
447 u8 umcr; /* MODEM control register */
448 u8 ulsr; /* line status register */
449 u8 umsr; /* MODEM status register */
450 u8 uscr; /* scratch register */
de1d0a69 451 u8 res0[8];
e080313c 452 u8 udsr; /* DMA status register */
de1d0a69
JL		 453 u8 res1[3];
454 u8 res2[0xEC];
f6eda7f8 455} duart83xx_t;
f046ccd1 456
61f25155
MB		 457/*
458 * DMA/Messaging Unit
459 */
f6eda7f8 460typedef struct dma83xx {
b701652a
DL		 461 u32 res0[0xC]; /* 0x0-0x29 reseverd */
462 u32 omisr; /* 0x30 Outbound message interrupt status register */
463 u32 omimr; /* 0x34 Outbound message interrupt mask register */
464 u32 res1[0x6]; /* 0x38-0x49 reserved */
b701652a
DL		 465 u32 imr0; /* 0x50 Inbound message register 0 */
466 u32 imr1; /* 0x54 Inbound message register 1 */
467 u32 omr0; /* 0x58 Outbound message register 0 */
468 u32 omr1; /* 0x5C Outbound message register 1 */
b701652a
DL		 469 u32 odr; /* 0x60 Outbound doorbell register */
470 u32 res2; /* 0x64-0x67 reserved */
471 u32 idr; /* 0x68 Inbound doorbell register */
472 u32 res3[0x5]; /* 0x6C-0x79 reserved */
b701652a
DL		 473 u32 imisr; /* 0x80 Inbound message interrupt status register */
474 u32 imimr; /* 0x84 Inbound message interrupt mask register */
475 u32 res4[0x1E]; /* 0x88-0x99 reserved */
e94e460c 476 struct fsl_dma dma[4];
f6eda7f8 477} dma83xx_t;
f046ccd1
EL		 478
479/*
480 * PCI Software Configuration Registers
481 */
f6eda7f8 482typedef struct pciconf83xx {
b701652a 483 u32 config_address;
f046ccd1
EL		 484 u32 config_data;
485 u32 int_ack;
b701652a 486 u8 res[116];
f6eda7f8 487} pciconf83xx_t;
f046ccd1
EL		 488
489/*
490 * PCI Outbound Translation Register
491 */
492typedef struct pci_outbound_window {
b701652a
DL		 493 u32 potar;
494 u8 res0[4];
495 u32 pobar;
496 u8 res1[4];
497 u32 pocmr;
498 u8 res2[4];
f6eda7f8 499} pot83xx_t;
b701652a 500
f046ccd1
EL		 501/*
502 * Sequencer
de1d0a69 503 */
f6eda7f8 504typedef struct ios83xx {
b701652a 505 pot83xx_t pot[6];
b701652a
DL		 506 u8 res0[0x60];
507 u32 pmcr;
508 u8 res1[4];
509 u32 dtcr;
510 u8 res2[4];
f6eda7f8 511} ios83xx_t;
f046ccd1
EL		 512
513/*
514 * PCI Controller Control and Status Registers
515 */
f6eda7f8 516typedef struct pcictrl83xx {
b701652a 517 u32 esr;
b701652a 518 u32 ecdr;
f046ccd1 519 u32 eer;
b701652a 520 u32 eatcr;
b701652a
DL		 521 u32 eacr;
522 u32 eeacr;
b701652a
DL		 523 u32 edlcr;
524 u32 edhcr;
b701652a
DL		 525 u32 gcr;
526 u32 ecr;
527 u32 gsr;
528 u8 res0[12];
529 u32 pitar2;
530 u8 res1[4];
531 u32 pibar2;
532 u32 piebar2;
533 u32 piwar2;
534 u8 res2[4];
535 u32 pitar1;
536 u8 res3[4];
537 u32 pibar1;
538 u32 piebar1;
539 u32 piwar1;
540 u8 res4[4];
541 u32 pitar0;
542 u8 res5[4];
543 u32 pibar0;
544 u8 res6[4];
545 u32 piwar0;
546 u8 res7[132];
f6eda7f8 547} pcictrl83xx_t;
f046ccd1
EL		 548
549/*
de1d0a69 550 * USB
f046ccd1 551 */
f6eda7f8 552typedef struct usb83xx {
d87c57b2 553 u8 fixme[0x1000];
f6eda7f8 554} usb83xx_t;
f046ccd1
EL		 555
556/*
557 * TSEC
558 */
f6eda7f8 559typedef struct tsec83xx {
f046ccd1 560 u8 fixme[0x1000];
f6eda7f8 561} tsec83xx_t;
f046ccd1
EL		 562
563/*
564 * Security
565 */
f6eda7f8 566typedef struct security83xx {
f046ccd1 567 u8 fixme[0x10000];
f6eda7f8 568} security83xx_t;
f046ccd1 569
03051c3d
DL		 570/*
571 * PCI Express
572 */
fd6646c0
AV		 573struct pex_inbound_window {
574 u32 ar;
575 u32 tar;
576 u32 barl;
577 u32 barh;
578};
579
580struct pex_outbound_window {
581 u32 ar;
582 u32 bar;
583 u32 tarl;
584 u32 tarh;
585};
586
587struct pex_csb_bridge {
588 u32 pex_csb_ver;
589 u32 pex_csb_cab;
590 u32 pex_csb_ctrl;
591 u8 res0[8];
592 u32 pex_dms_dstmr;
593 u8 res1[4];
594 u32 pex_cbs_stat;
595 u8 res2[0x20];
596 u32 pex_csb_obctrl;
597 u32 pex_csb_obstat;
598 u8 res3[0x98];
599 u32 pex_csb_ibctrl;
600 u32 pex_csb_ibstat;
601 u8 res4[0xb8];
602 u32 pex_wdma_ctrl;
603 u32 pex_wdma_addr;
604 u32 pex_wdma_stat;
605 u8 res5[0x94];
606 u32 pex_rdma_ctrl;
607 u32 pex_rdma_addr;
608 u32 pex_rdma_stat;
609 u8 res6[0xd4];
610 u32 pex_ombcr;
611 u32 pex_ombdr;
612 u8 res7[0x38];
613 u32 pex_imbcr;
614 u32 pex_imbdr;
615 u8 res8[0x38];
616 u32 pex_int_enb;
617 u32 pex_int_stat;
618 u32 pex_int_apio_vec1;
619 u32 pex_int_apio_vec2;
620 u8 res9[0x10];
621 u32 pex_int_ppio_vec1;
622 u32 pex_int_ppio_vec2;
623 u32 pex_int_wdma_vec1;
624 u32 pex_int_wdma_vec2;
625 u32 pex_int_rdma_vec1;
626 u32 pex_int_rdma_vec2;
627 u32 pex_int_misc_vec;
628 u8 res10[4];
629 u32 pex_int_axi_pio_enb;
630 u32 pex_int_axi_wdma_enb;
631 u32 pex_int_axi_rdma_enb;
632 u32 pex_int_axi_misc_enb;
633 u32 pex_int_axi_pio_stat;
634 u32 pex_int_axi_wdma_stat;
635 u32 pex_int_axi_rdma_stat;
636 u32 pex_int_axi_misc_stat;
637 u8 res11[0xa0];
638 struct pex_outbound_window pex_outbound_win[4];
639 u8 res12[0x100];
640 u32 pex_epiwtar0;
641 u32 pex_epiwtar1;
642 u32 pex_epiwtar2;
643 u32 pex_epiwtar3;
644 u8 res13[0x70];
645 struct pex_inbound_window pex_inbound_win[4];
646};
647
03051c3d 648typedef struct pex83xx {
fd6646c0
AV		 649 u8 pex_cfg_header[0x404];
650 u32 pex_ltssm_stat;
651 u8 res0[0x30];
652 u32 pex_ack_replay_timeout;
653 u8 res1[4];
654 u32 pex_gclk_ratio;
655 u8 res2[0xc];
656 u32 pex_pm_timer;
657 u32 pex_pme_timeout;
658 u8 res3[4];
659 u32 pex_aspm_req_timer;
660 u8 res4[0x18];
661 u32 pex_ssvid_update;
662 u8 res5[0x34];
663 u32 pex_cfg_ready;
664 u8 res6[0x24];
665 u32 pex_bar_sizel;
666 u8 res7[4];
667 u32 pex_bar_sel;
668 u8 res8[0x20];
669 u32 pex_bar_pf;
670 u8 res9[0x88];
671 u32 pex_pme_to_ack_tor;
672 u8 res10[0xc];
673 u32 pex_ss_intr_mask;
674 u8 res11[0x25c];
675 struct pex_csb_bridge bridge;
676 u8 res12[0x160];
03051c3d
DL		 677} pex83xx_t;
678
679/*
680 * SATA
681 */
682typedef struct sata83xx {
683 u8 fixme[0x1000];
684} sata83xx_t;
685
686/*
687 * eSDHC
688 */
689typedef struct sdhc83xx {
690 u8 fixme[0x1000];
691} sdhc83xx_t;
692
693/*
694 * SerDes
695 */
696typedef struct serdes83xx {
7c619ddc
IY		 697 u32 srdscr0;
698 u32 srdscr1;
699 u32 srdscr2;
700 u32 srdscr3;
701 u32 srdscr4;
702 u8 res0[0xc];
703 u32 srdsrstctl;
704 u8 res1[0xdc];
03051c3d
DL		 705} serdes83xx_t;
706
707/*
708 * On Chip ROM
709 */
710typedef struct rom83xx {
711 u8 mem[0x10000];
712} rom83xx_t;
713
555da617
DL		 714/*
715 * TDM
716 */
717typedef struct tdm83xx {
718 u8 fixme[0x200];
719} tdm83xx_t;
720
721/*
722 * TDM DMAC
723 */
724typedef struct tdmdmac83xx {
725 u8 fixme[0x2000];
726} tdmdmac83xx_t;
727
2c7920af 728#if defined(CONFIG_MPC834x)
e080313c
DL		 729typedef struct immap {
730 sysconf83xx_t sysconf; /* System configuration */
731 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
732 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
733 rtclk83xx_t pit; /* Periodic Interval Timer */
734 gtm83xx_t gtm[2]; /* Global Timers Module */
735 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
736 arbiter83xx_t arbiter; /* System Arbiter Registers */
737 reset83xx_t reset; /* Reset Module */
738 clk83xx_t clk; /* System Clock Module */
739 pmc83xx_t pmc; /* Power Management Control Module */
740 gpio83xx_t gpio[2]; /* General purpose I/O module */
741 u8 res0[0x200];
742 u8 dll_ddr[0x100];
743 u8 dll_lbc[0x100];
744 u8 res1[0xE00];
d29d17d7
YS		 745#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
746 ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
747#else
748 ddr83xx_t ddr; /* DDR Memory Controller Memory */
749#endif
e080313c
DL		 750 fsl_i2c_t i2c[2]; /* I2C Controllers */
751 u8 res2[0x1300];
752 duart83xx_t duart[2]; /* DUART */
753 u8 res3[0x900];
f51cdaf1 754 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c 755 u8 res4[0x1000];
04a9e118 756 spi8xxx_t spi; /* Serial Peripheral Interface */
e080313c
DL		 757 dma83xx_t dma; /* DMA */
758 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
759 ios83xx_t ios; /* Sequencer */
760 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
761 u8 res5[0x19900];
d87c57b2
SW		 762 usb83xx_t usb[2];
763 tsec83xx_t tsec[2];
764 u8 res6[0xA000];
765 security83xx_t security;
766 u8 res7[0xC0000];
767} immap_t;
768
d89e1c36
VG		 769#ifdef CONFIG_HAS_FSL_MPH_USB
770#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
771#else
772#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
773#endif
774
555da617 775#elif defined(CONFIG_MPC8313)
d87c57b2
SW		 776typedef struct immap {
777 sysconf83xx_t sysconf; /* System configuration */
778 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
779 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
780 rtclk83xx_t pit; /* Periodic Interval Timer */
781 gtm83xx_t gtm[2]; /* Global Timers Module */
782 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
783 arbiter83xx_t arbiter; /* System Arbiter Registers */
784 reset83xx_t reset; /* Reset Module */
785 clk83xx_t clk; /* System Clock Module */
786 pmc83xx_t pmc; /* Power Management Control Module */
787 gpio83xx_t gpio[1]; /* General purpose I/O module */
788 u8 res0[0x1300];
789 ddr83xx_t ddr; /* DDR Memory Controller Memory */
790 fsl_i2c_t i2c[2]; /* I2C Controllers */
791 u8 res1[0x1300];
792 duart83xx_t duart[2]; /* DUART */
793 u8 res2[0x900];
f51cdaf1 794 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
d87c57b2 795 u8 res3[0x1000];
04a9e118 796 spi8xxx_t spi; /* Serial Peripheral Interface */
d87c57b2
SW		 797 dma83xx_t dma; /* DMA */
798 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
799 u8 res4[0x80];
800 ios83xx_t ios; /* Sequencer */
801 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
802 u8 res5[0x1aa00];
803 usb83xx_t usb[1];
e080313c
DL		 804 tsec83xx_t tsec[2];
805 u8 res6[0xA000];
806 security83xx_t security;
807 u8 res7[0xC0000];
808} immap_t;
b701652a 809
7c619ddc 810#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
555da617
DL		 811typedef struct immap {
812 sysconf83xx_t sysconf; /* System configuration */
813 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
814 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
815 rtclk83xx_t pit; /* Periodic Interval Timer */
816 gtm83xx_t gtm[2]; /* Global Timers Module */
817 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
818 arbiter83xx_t arbiter; /* System Arbiter Registers */
819 reset83xx_t reset; /* Reset Module */
820 clk83xx_t clk; /* System Clock Module */
821 pmc83xx_t pmc; /* Power Management Control Module */
822 gpio83xx_t gpio[1]; /* General purpose I/O module */
823 u8 res0[0x1300];
824 ddr83xx_t ddr; /* DDR Memory Controller Memory */
825 fsl_i2c_t i2c[2]; /* I2C Controllers */
826 u8 res1[0x1300];
827 duart83xx_t duart[2]; /* DUART */
828 u8 res2[0x900];
f51cdaf1 829 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
555da617 830 u8 res3[0x1000];
04a9e118 831 spi8xxx_t spi; /* Serial Peripheral Interface */
555da617
DL		 832 dma83xx_t dma; /* DMA */
833 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
834 u8 res4[0x80];
835 ios83xx_t ios; /* Sequencer */
836 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
837 u8 res5[0xa00];
838 pex83xx_t pciexp[2]; /* PCI Express Controller */
839 u8 res6[0xb000];
840 tdm83xx_t tdm; /* TDM Controller */
841 u8 res7[0x1e00];
842 sata83xx_t sata[2]; /* SATA Controller */
843 u8 res8[0x9000];
844 usb83xx_t usb[1]; /* USB DR Controller */
845 tsec83xx_t tsec[2];
846 u8 res9[0x6000];
847 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
848 u8 res10[0x2000];
849 security83xx_t security;
850 u8 res11[0xA3000];
851 serdes83xx_t serdes[1]; /* SerDes Registers */
852 u8 res12[0x1CF00];
853} immap_t;
854
2c7920af 855#elif defined(CONFIG_MPC837x)
03051c3d
DL		 856typedef struct immap {
857 sysconf83xx_t sysconf; /* System configuration */
858 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
859 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
860 rtclk83xx_t pit; /* Periodic Interval Timer */
861 gtm83xx_t gtm[2]; /* Global Timers Module */
862 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
863 arbiter83xx_t arbiter; /* System Arbiter Registers */
864 reset83xx_t reset; /* Reset Module */
865 clk83xx_t clk; /* System Clock Module */
866 pmc83xx_t pmc; /* Power Management Control Module */
867 gpio83xx_t gpio[2]; /* General purpose I/O module */
868 u8 res0[0x1200];
869 ddr83xx_t ddr; /* DDR Memory Controller Memory */
870 fsl_i2c_t i2c[2]; /* I2C Controllers */
871 u8 res1[0x1300];
872 duart83xx_t duart[2]; /* DUART */
873 u8 res2[0x900];
f51cdaf1 874 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
03051c3d 875 u8 res3[0x1000];
04a9e118 876 spi8xxx_t spi; /* Serial Peripheral Interface */
03051c3d
DL		 877 dma83xx_t dma; /* DMA */
878 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
879 u8 res4[0x80];
880 ios83xx_t ios; /* Sequencer */
881 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
882 u8 res5[0xa00];
883 pex83xx_t pciexp[2]; /* PCI Express Controller */
884 u8 res6[0xd000];
885 sata83xx_t sata[4]; /* SATA Controller */
886 u8 res7[0x7000];
887 usb83xx_t usb[1]; /* USB DR Controller */
888 tsec83xx_t tsec[2];
889 u8 res8[0x8000];
890 sdhc83xx_t sdhc; /* SDHC Controller */
891 u8 res9[0x1000];
892 security83xx_t security;
893 u8 res10[0xA3000];
894 serdes83xx_t serdes[2]; /* SerDes Registers */
895 u8 res11[0xCE00];
896 rom83xx_t rom; /* On Chip ROM */
897} immap_t;
898
e080313c 899#elif defined(CONFIG_MPC8360)
f046ccd1 900typedef struct immap {
e080313c
DL		 901 sysconf83xx_t sysconf; /* System configuration */
902 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
903 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
904 rtclk83xx_t pit; /* Periodic Interval Timer */
905 u8 res0[0x200];
906 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
907 arbiter83xx_t arbiter; /* System Arbiter Registers */
908 reset83xx_t reset; /* Reset Module */
909 clk83xx_t clk; /* System Clock Module */
910 pmc83xx_t pmc; /* Power Management Control Module */
911 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
912 u8 res1[0x300];
913 u8 dll_ddr[0x100];
914 u8 dll_lbc[0x100];
915 u8 res2[0x200];
916 qepio83xx_t qepio; /* QE Parallel I/O ports */
917 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
918 u8 res3[0x400];
919 ddr83xx_t ddr; /* DDR Memory Controller Memory */
920 fsl_i2c_t i2c[2]; /* I2C Controllers */
921 u8 res4[0x1300];
922 duart83xx_t duart[2]; /* DUART */
923 u8 res5[0x900];
f51cdaf1 924 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
e080313c
DL		 925 u8 res6[0x2000];
926 dma83xx_t dma; /* DMA */
927 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
928 u8 res7[128];
929 ios83xx_t ios; /* Sequencer (IOS) */
930 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
931 u8 res8[0x4A00];
932 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
933 u8 res9[0x22000];
934 security83xx_t security;
935 u8 res10[0xC0000];
936 u8 qe[0x100000]; /* QE block */
f046ccd1 937} immap_t;
24c3aca3 938
2c7920af 939#elif defined(CONFIG_MPC832x)
24c3aca3
DL		 940typedef struct immap {
941 sysconf83xx_t sysconf; /* System configuration */
942 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
943 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
944 rtclk83xx_t pit; /* Periodic Interval Timer */
945 gtm83xx_t gtm[2]; /* Global Timers Module */
946 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
947 arbiter83xx_t arbiter; /* System Arbiter Registers */
948 reset83xx_t reset; /* Reset Module */
949 clk83xx_t clk; /* System Clock Module */
950 pmc83xx_t pmc; /* Power Management Control Module */
951 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
952 u8 res0[0x300];
953 u8 dll_ddr[0x100];
954 u8 dll_lbc[0x100];
955 u8 res1[0x200];
956 qepio83xx_t qepio; /* QE Parallel I/O ports */
957 u8 res2[0x800];
958 ddr83xx_t ddr; /* DDR Memory Controller Memory */
959 fsl_i2c_t i2c[2]; /* I2C Controllers */
960 u8 res3[0x1300];
961 duart83xx_t duart[2]; /* DUART */
962 u8 res4[0x900];
f51cdaf1 963 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
24c3aca3
DL		 964 u8 res5[0x2000];
965 dma83xx_t dma; /* DMA */
966 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
967 u8 res6[128];
968 ios83xx_t ios; /* Sequencer (IOS) */
969 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
970 u8 res7[0x27A00];
971 security83xx_t security;
972 u8 res8[0xC0000];
973 u8 qe[0x100000]; /* QE block */
974} immap_t;
e080313c 975#endif
f046ccd1 976
d29d17d7
YS		 977#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
978#define CONFIG_SYS_MPC83xx_DDR_ADDR \
979 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
e94e460c 980#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
d29d17d7
YS		 981#define CONFIG_SYS_MPC83xx_DMA_ADDR \
982 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
e1ac387f 983#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
d29d17d7
YS		 984#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
985 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
d89e1c36
VG		 986
987#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
988#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
989#endif
4ef01010
VM		 990#define CONFIG_SYS_MPC83xx_USB_ADDR \
991 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
f51cdaf1 992#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
b9e186fc
SG		 993
994#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e 995#define CONFIG_SYS_MDIO1_OFFSET 0x24000
b9e186fc
SG		 996
997#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
998#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
b701652a 999#endif /* __IMMAP_83xx__ */
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