[J-u-boot.git] / arch / avr32 / include / asm / sdram.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __ASM_AVR32_SDRAM_H
#define __ASM_AVR32_SDRAM_H

struct sdram_config {
	/* Number of data bits. */
	enum {
		SDRAM_DATA_16BIT = 16,
		SDRAM_DATA_32BIT = 32,
	} data_bits;

	/* Number of address bits */
	uint8_t row_bits, col_bits, bank_bits;

	/* SDRAM timings in cycles */
	uint8_t cas, twr, trc, trp, trcd, tras, txsr;

	/* SDRAM refresh period in cycles */
	unsigned long refresh_period;
};

/*
 * Attempt to initialize the SDRAM controller using the specified
 * parameters. Return the expected size of the memory area based on
 * the number of address and data bits.
 *
 * The caller should verify that the configuration is correct by
 * running a memory test, e.g. get_ram_size().
 */
extern unsigned long sdram_init(void *sdram_base,
			const struct sdram_config *config);

#endif /* __ASM_AVR32_SDRAM_H */
Commit	Line	Data
7b64fef3 WD	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
7b64fef3 WD	5	*/
	6	#ifndef __ASM_AVR32_SDRAM_H
	7	#define __ASM_AVR32_SDRAM_H
	8
a23e277c HS	9	struct sdram_config {
	10	/* Number of data bits. */
	11	enum {
4c24e828 HS	12	SDRAM_DATA_16BIT = 16,
4c24e828 HS	13	SDRAM_DATA_32BIT = 32,
a23e277c HS	14	} data_bits;
	15
	16	/* Number of address bits */
	17	uint8_t row_bits, col_bits, bank_bits;
	18
	19	/* SDRAM timings in cycles */
	20	uint8_t cas, twr, trc, trp, trcd, tras, txsr;
d38da537 HS	21
	22	/* SDRAM refresh period in cycles */
	23	unsigned long refresh_period;
7b64fef3 WD	24	};
7b64fef3 WD	25
a23e277c HS	26	/*
	27	* Attempt to initialize the SDRAM controller using the specified
	28	* parameters. Return the expected size of the memory area based on
	29	* the number of address and data bits.
	30	*
	31	* The caller should verify that the configuration is correct by
	32	* running a memory test, e.g. get_ram_size().
	33	*/
	34	extern unsigned long sdram_init(void *sdram_base,
	35	const struct sdram_config *config);
7b64fef3 WD	36
7b64fef3 WD	37	#endif /* __ASM_AVR32_SDRAM_H */