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7b64fef3 WD |
1 | /* |
2 | * Copyright (C) 2006 Atmel Corporation | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | #ifndef __ASM_AVR32_SDRAM_H | |
23 | #define __ASM_AVR32_SDRAM_H | |
24 | ||
a23e277c HS |
25 | struct sdram_config { |
26 | /* Number of data bits. */ | |
27 | enum { | |
4c24e828 HS |
28 | SDRAM_DATA_16BIT = 16, |
29 | SDRAM_DATA_32BIT = 32, | |
a23e277c HS |
30 | } data_bits; |
31 | ||
32 | /* Number of address bits */ | |
33 | uint8_t row_bits, col_bits, bank_bits; | |
34 | ||
35 | /* SDRAM timings in cycles */ | |
36 | uint8_t cas, twr, trc, trp, trcd, tras, txsr; | |
d38da537 HS |
37 | |
38 | /* SDRAM refresh period in cycles */ | |
39 | unsigned long refresh_period; | |
7b64fef3 WD |
40 | }; |
41 | ||
a23e277c HS |
42 | /* |
43 | * Attempt to initialize the SDRAM controller using the specified | |
44 | * parameters. Return the expected size of the memory area based on | |
45 | * the number of address and data bits. | |
46 | * | |
47 | * The caller should verify that the configuration is correct by | |
48 | * running a memory test, e.g. get_ram_size(). | |
49 | */ | |
50 | extern unsigned long sdram_init(void *sdram_base, | |
51 | const struct sdram_config *config); | |
7b64fef3 WD |
52 | |
53 | #endif /* __ASM_AVR32_SDRAM_H */ |