[J-u-boot.git] / include / configs / Alaska8220.h

/*
 * (C) Copyright 2004
 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC8220		1
#define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
   determine the CPU speed. */
#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot	*/

/*
 * Serial console configuration
 */

/* Define this for PSC console
#define CONFIG_PSC_CONSOLE	1
*/

#define CONFIG_EXTUART_CONSOLE	1

#ifdef CONFIG_EXTUART_CONSOLE
#   define CONFIG_CONS_INDEX	1
#   define CONFIG_SYS_NS16550_SERIAL
#   define CONFIG_SYS_NS16550
#   define CONFIG_SYS_NS16550_REG_SIZE 1
#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
#   define CONFIG_SYS_NS16550_CLK	18432000
#endif

#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_TIMESTAMP			/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP


#define CONFIG_NET_MULTI
#define CONFIG_MII

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
#define CONFIG_BOOTARGS		"root=/dev/ram rw"
#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
#define CONFIG_IPADDR		192.162.1.2
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_SERVERIP		192.162.1.1
#define CONFIG_GATEWAYIP	192.162.1.1
#define CONFIG_HOSTNAME		Alaska
#define CONFIG_OVERWRITE_ETHADDR_ONCE


/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE		1

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
/*
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0
#define CONFIG_ENV_SIZE		256
*/

/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
   else undefined it will boot from Intel Strata flash */
#define CONFIG_SYS_AMD_BOOT		1

/*
 * Flexbus Chipselect configuration
 */
#if defined (CONFIG_SYS_AMD_BOOT)
#define CONFIG_SYS_CS0_BASE		0xfff0
#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
#define CONFIG_SYS_CS0_CTRL		0x003f0d40

#define CONFIG_SYS_CS1_BASE		0xfe00
#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
#define CONFIG_SYS_CS1_CTRL		0x003f1540
#else
#define CONFIG_SYS_CS0_BASE		0xff00
#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
#define CONFIG_SYS_CS0_CTRL		0x003f1540

#define CONFIG_SYS_CS1_BASE		0xfe08
#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
#define CONFIG_SYS_CS1_CTRL		0x003f0d40
#endif

#define CONFIG_SYS_CS2_BASE		0xf100
#define CONFIG_SYS_CS2_MASK		0x00040000
#define CONFIG_SYS_CS2_CTRL		0x003f1140

#define CONFIG_SYS_CS3_BASE		0xf200
#define CONFIG_SYS_CS3_MASK		0x00040000
#define CONFIG_SYS_CS3_CTRL		0x003f1100


#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)

#if defined (CONFIG_SYS_AMD_BOOT)
#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
#else
#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
#endif

#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)


#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */

#define CONFIG_SYS_FLASH_CHECKSUM
/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#if defined (CONFIG_SYS_AMD_BOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
#define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
#define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
#define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
#else
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
#define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
#define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
#define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
#endif

#define CONFIG_ENV_OVERWRITE	1

#if defined CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_EEPROM
#elif defined CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_EEPROM
#elif defined CONFIG_ENV_IS_IN_EEPROM
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
#define CONFIG_SYS_SRAM_SIZE		0x8000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/* SDRAM configuration */
#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */

/* SDRAM drive strength register */
#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))

/*
 * Ethernet configuration
 */
#define CONFIG_MPC8220_FEC	1
#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR		0x18


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */

#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */

#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

/*
 * JFFS2 partitions
 */

/* No command line, one static partition */
/*
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0x00400000
#define CONFIG_JFFS2_PART_OFFSET	0x00000000
*/

/* mtdparts command line support */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=alaska-0"
#define MTDPARTS_DEFAULT	"mtdparts=alaska-0:4m(user)"
*/

#endif /* __CONFIG_H */
Commit	Line	Data
983fda83 WD	1	/*
	2	* (C) Copyright 2004
	3	* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31	#define CONFIG_MPC8220 1
	32	#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
	33
31d82672 BB	34	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	35
983fda83 WD	36	/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
983fda83 WD	37	determine the CPU speed. */
6d0f6bcf JCPV	38	#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
6d0f6bcf JCPV	39	#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
983fda83 WD	40
	41	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	42	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	43
983fda83 WD	44	/*
	45	* Serial console configuration
	46	*/
7680c140 WD	47
	48	/* Define this for PSC console
	49	#define CONFIG_PSC_CONSOLE 1
	50	*/
	51
983fda83 WD	52	#define CONFIG_EXTUART_CONSOLE 1
	53
	54	#ifdef CONFIG_EXTUART_CONSOLE
7680c140	55	# define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	56	# define CONFIG_SYS_NS16550_SERIAL
	57	# define CONFIG_SYS_NS16550
	58	# define CONFIG_SYS_NS16550_REG_SIZE 1
	59	# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
	60	# define CONFIG_SYS_NS16550_CLK 18432000
983fda83 WD	61	#endif
	62
	63	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	64
6d0f6bcf	65	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
983fda83	66
7680c140	67	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35	68
498ff9a2	69
11799434 JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
	78
983fda83	79	/*
498ff9a2	80	* Command line configuration.
983fda83	81	*/
498ff9a2 JL	82	#include <config_cmd_default.h>
	83
	84	#define CONFIG_CMD_BOOTD
	85	#define CONFIG_CMD_CACHE
	86	#define CONFIG_CMD_DHCP
	87	#define CONFIG_CMD_DIAG
	88	#define CONFIG_CMD_EEPROM
	89	#define CONFIG_CMD_ELF
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_CMD_NET
	92	#define CONFIG_CMD_NFS
	93	#define CONFIG_CMD_PCI
	94	#define CONFIG_CMD_PING
	95	#define CONFIG_CMD_REGINFO
	96	#define CONFIG_CMD_SDRAM
	97	#define CONFIG_CMD_SNTP
	98
414eec35 WD	99
414eec35 WD	100	#define CONFIG_NET_MULTI
63ff004c	101	#define CONFIG_MII
983fda83	102
983fda83 WD	103	/*
	104	* Autobooting
	105	*/
	106	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	107	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	108	#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
e2ffd59b	109	#define CONFIG_HAS_ETH1
983fda83 WD	110	#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
	111	#define CONFIG_IPADDR 192.162.1.2
	112	#define CONFIG_NETMASK 255.255.255.0
	113	#define CONFIG_SERVERIP 192.162.1.1
	114	#define CONFIG_GATEWAYIP 192.162.1.1
	115	#define CONFIG_HOSTNAME Alaska
	116	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	117
	118
	119	/*
	120	* I2C configuration
	121	*/
	122	#define CONFIG_HARD_I2C 1
6d0f6bcf	123	#define CONFIG_SYS_I2C_MODULE 1
983fda83	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	126	#define CONFIG_SYS_I2C_SLAVE 0x7F
983fda83 WD	127
	128	/*
	129	* EEPROM configuration
	130	*/
6d0f6bcf JCPV	131	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
	132	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	133	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	134	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
983fda83	135	/*
bb1f8b4f	136	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	137	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	138	#define CONFIG_ENV_SIZE 256
983fda83 WD	139	*/
983fda83 WD	140
6d0f6bcf	141	/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
983fda83	142	else undefined it will boot from Intel Strata flash */
6d0f6bcf	143	#define CONFIG_SYS_AMD_BOOT 1
983fda83 WD	144
	145	/*
	146	* Flexbus Chipselect configuration
	147	*/
6d0f6bcf JCPV	148	#if defined (CONFIG_SYS_AMD_BOOT)
	149	#define CONFIG_SYS_CS0_BASE 0xfff0
	150	#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
	151	#define CONFIG_SYS_CS0_CTRL 0x003f0d40
	152
	153	#define CONFIG_SYS_CS1_BASE 0xfe00
	154	#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
	155	#define CONFIG_SYS_CS1_CTRL 0x003f1540
983fda83	156	#else
6d0f6bcf JCPV	157	#define CONFIG_SYS_CS0_BASE 0xff00
	158	#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
	159	#define CONFIG_SYS_CS0_CTRL 0x003f1540
983fda83	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_CS1_BASE 0xfe08
	162	#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
	163	#define CONFIG_SYS_CS1_CTRL 0x003f0d40
983fda83 WD	164	#endif
983fda83 WD	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_CS2_BASE 0xf100
	167	#define CONFIG_SYS_CS2_MASK 0x00040000
	168	#define CONFIG_SYS_CS2_CTRL 0x003f1140
983fda83	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_CS3_BASE 0xf200
	171	#define CONFIG_SYS_CS3_MASK 0x00040000
	172	#define CONFIG_SYS_CS3_CTRL 0x003f1100
983fda83 WD	173
983fda83 WD	174
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
983fda83	177
6d0f6bcf JCPV	178	#if defined (CONFIG_SYS_AMD_BOOT)
	179	#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
	180	#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
	181	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
983fda83	182	#else
6d0f6bcf JCPV	183	#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
	184	#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
	185	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
983fda83 WD	186	#endif
983fda83 WD	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
6d0f6bcf JCPV	189	#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
983fda83 WD	190
983fda83 WD	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
6d0f6bcf JCPV	193	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
983fda83	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	196	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	197	#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	198	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	199	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
983fda83 WD	200
	201	#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
	202	#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
	203
6d0f6bcf	204	#define CONFIG_SYS_FLASH_CHECKSUM
983fda83 WD	205	/*
	206	* Environment settings
	207	*/
5a1aceb0	208	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf JCPV	209	#if defined (CONFIG_SYS_AMD_BOOT)
6d0f6bcf JCPV	210	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
0e8d1586 JCPV	211	#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
0e8d1586 JCPV	212	#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
6d0f6bcf	213	#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
0e8d1586 JCPV	214	#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
0e8d1586 JCPV	215	#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
983fda83	216	#else
6d0f6bcf	217	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
0e8d1586 JCPV	218	#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
0e8d1586 JCPV	219	#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
6d0f6bcf	220	#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
0e8d1586 JCPV	221	#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
0e8d1586 JCPV	222	#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
983fda83 WD	223	#endif
	224
	225	#define CONFIG_ENV_OVERWRITE 1
	226
5a1aceb0	227	#if defined CONFIG_ENV_IS_IN_FLASH
9314cee6	228	#undef CONFIG_ENV_IS_IN_NVRAM
bb1f8b4f	229	#undef CONFIG_ENV_IS_IN_EEPROM
9314cee6	230	#elif defined CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	231	#undef CONFIG_ENV_IS_IN_FLASH
bb1f8b4f JCPV	232	#undef CONFIG_ENV_IS_IN_EEPROM
bb1f8b4f JCPV	233	#elif defined CONFIG_ENV_IS_IN_EEPROM
9314cee6	234	#undef CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	235	#undef CONFIG_ENV_IS_IN_FLASH
983fda83 WD	236	#endif
983fda83 WD	237
983fda83 WD	238	/*
	239	* Memory map
	240	*/
6d0f6bcf JCPV	241	#define CONFIG_SYS_MBAR 0xF0000000
	242	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	243	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	244	#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
	245	#define CONFIG_SYS_SRAM_SIZE 0x8000
983fda83 WD	246
983fda83 WD	247	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	248	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
6d0f6bcf JCPV	249	#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
983fda83	250
6d0f6bcf JCPV	251	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	252	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	253	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
983fda83	254
6d0f6bcf JCPV	255	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	256	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	257	# define CONFIG_SYS_RAMBOOT 1
983fda83 WD	258	#endif
983fda83 WD	259
6d0f6bcf JCPV	260	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	261	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	262	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
983fda83	263
12b43d51	264	/* SDRAM configuration */
6d0f6bcf JCPV	265	#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
	266	#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
	267	#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
	268	#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
7680c140 WD	269
7680c140 WD	270	/* SDRAM drive strength register */
6d0f6bcf	271	#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) \| \
7680c140 WD	272	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) \| \
	273	(DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) \| \
	274	(DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) \| \
	275	(DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
12b43d51	276
983fda83 WD	277	/*
	278	* Ethernet configuration
	279	*/
	280	#define CONFIG_MPC8220_FEC 1
	281	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
	282	#define CONFIG_PHY_ADDR 0x18
	283
	284
	285	/*
	286	* Miscellaneous configurable options
	287	*/
6d0f6bcf JCPV	288	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	289	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
498ff9a2	290	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	291	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
983fda83	292	#else
6d0f6bcf	293	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
983fda83	294	#endif
6d0f6bcf JCPV	295	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	296	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	297	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
983fda83	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	300	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
983fda83	301
6d0f6bcf	302	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
983fda83	303
6d0f6bcf	304	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
983fda83	305
6d0f6bcf	306	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
498ff9a2	307	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	308	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
498ff9a2 JL	309	#endif
498ff9a2 JL	310
983fda83 WD	311	/*
	312	* Various low-level settings
	313	*/
6d0f6bcf JCPV	314	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	315	#define CONFIG_SYS_HID0_FINAL HID0_ICE
983fda83	316
700a0c64 WD	317	/*
	318	* JFFS2 partitions
	319	*/
	320
	321	/* No command line, one static partition */
	322	/*
	323	#undef CONFIG_JFFS2_CMDLINE
	324	#define CONFIG_JFFS2_DEV "nor0"
	325	#define CONFIG_JFFS2_PART_SIZE 0x00400000
	326	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	327	*/
	328
	329	/* mtdparts command line support */
	330	/*
	331	#define CONFIG_JFFS2_CMDLINE
	332	#define MTDIDS_DEFAULT "nor0=alaska-0"
	333	#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
	334	*/
	335
983fda83	336	#endif /* __CONFIG_H */