[J-u-boot.git] / include / configs / Alaska8220.h

/*
 * (C) Copyright 2004
 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC8220		1
#define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
   determine the CPU speed. */
#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot	*/

/*
 * Serial console configuration
 */

/* Define this for PSC console
#define CONFIG_PSC_CONSOLE	1
*/

#define CONFIG_EXTUART_CONSOLE	1

#ifdef CONFIG_EXTUART_CONSOLE
#   define CONFIG_CONS_INDEX	1
#   define CFG_NS16550_SERIAL
#   define CFG_NS16550
#   define CFG_NS16550_REG_SIZE 1
#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
#   define CFG_NS16550_CLK	18432000
#endif

#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_TIMESTAMP			/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP


#define CONFIG_NET_MULTI
#define CONFIG_MII

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
#define CONFIG_BOOTARGS		"root=/dev/ram rw"
#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
#define CONFIG_IPADDR		192.162.1.2
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_SERVERIP		192.162.1.1
#define CONFIG_GATEWAYIP	192.162.1.1
#define CONFIG_HOSTNAME		Alaska
#define CONFIG_OVERWRITE_ETHADDR_ONCE


/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CFG_I2C_MODULE		1

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
/*
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0
#define CFG_ENV_SIZE		256
*/

/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
   else undefined it will boot from Intel Strata flash */
#define CFG_AMD_BOOT		1

/*
 * Flexbus Chipselect configuration
 */
#if defined (CFG_AMD_BOOT)
#define CFG_CS0_BASE		0xfff0
#define CFG_CS0_MASK		0x00080000  /* 512 KB */
#define CFG_CS0_CTRL		0x003f0d40

#define CFG_CS1_BASE		0xfe00
#define CFG_CS1_MASK		0x01000000  /* 16 MB */
#define CFG_CS1_CTRL		0x003f1540
#else
#define CFG_CS0_BASE		0xff00
#define CFG_CS0_MASK		0x01000000  /* 16 MB */
#define CFG_CS0_CTRL		0x003f1540

#define CFG_CS1_BASE		0xfe08
#define CFG_CS1_MASK		0x00080000  /* 512 KB */
#define CFG_CS1_CTRL		0x003f0d40
#endif

#define CFG_CS2_BASE		0xf100
#define CFG_CS2_MASK		0x00040000
#define CFG_CS2_CTRL		0x003f1140

#define CFG_CS3_BASE		0xf200
#define CFG_CS3_MASK		0x00040000
#define CFG_CS3_CTRL		0x003f1100


#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)

#if defined (CFG_AMD_BOOT)
#define CFG_AMD_BASE		CFG_FLASH0_BASE
#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
#define CFG_FLASH_BASE		CFG_AMD_BASE
#else
#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
#define CFG_AMD_BASE		CFG_FLASH1_BASE
#define CFG_FLASH_BASE		CFG_INTEL_BASE
#endif

#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)


#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */

#define CFG_FLASH_CHECKSUM
/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#if defined (CFG_AMD_BOOT)
#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
#define CFG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
#define CFG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
#else
#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
#define CFG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
#define CFG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
#define CFG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
#define CFG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
#endif

#define CONFIG_ENV_OVERWRITE	1

#if defined CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_EEPROM
#elif defined CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_EEPROM
#elif defined CFG_ENV_IS_IN_EEPROM
#undef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#endif

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000
#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
#define CFG_SRAM_SIZE		0x8000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */

#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/* SDRAM configuration */
#define CFG_SDRAM_TOTAL_BANKS		2
#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
#define CFG_SDRAM_SPD_SIZE		0x40
#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */

/* SDRAM drive strength register */
#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))

/*
 * Ethernet configuration
 */
#define CONFIG_MPC8220_FEC	1
#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR		0x18


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			    /* undef to save memory	*/
#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16	    /* max number of command args   */
#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */

#define CFG_LOAD_ADDR		0x100000    /* default load address */

#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

/*
 * JFFS2 partitions
 */

/* No command line, one static partition */
/*
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0x00400000
#define CONFIG_JFFS2_PART_OFFSET	0x00000000
*/

/* mtdparts command line support */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=alaska-0"
#define MTDPARTS_DEFAULT	"mtdparts=alaska-0:4m(user)"
*/

#endif /* __CONFIG_H */
Commit	Line	Data
983fda83 WD	1	/*
	2	* (C) Copyright 2004
	3	* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31	#define CONFIG_MPC8220 1
	32	#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
	33
31d82672 BB	34	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	35
983fda83 WD	36	/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
	37	determine the CPU speed. */
	38	#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
12b43d51	39	#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
983fda83 WD	40
	41	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	42	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	43
983fda83 WD	44	/*
	45	* Serial console configuration
	46	*/
7680c140 WD	47
	48	/* Define this for PSC console
	49	#define CONFIG_PSC_CONSOLE 1
	50	*/
	51
983fda83 WD	52	#define CONFIG_EXTUART_CONSOLE 1
	53
	54	#ifdef CONFIG_EXTUART_CONSOLE
7680c140 WD	55	# define CONFIG_CONS_INDEX 1
7680c140 WD	56	# define CFG_NS16550_SERIAL
983fda83 WD	57	# define CFG_NS16550
	58	# define CFG_NS16550_REG_SIZE 1
	59	# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
7680c140	60	# define CFG_NS16550_CLK 18432000
983fda83 WD	61	#endif
	62
	63	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	64
983fda83 WD	65	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
983fda83 WD	66
7680c140	67	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35	68
498ff9a2	69
11799434 JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
	78
983fda83	79	/*
498ff9a2	80	* Command line configuration.
983fda83	81	*/
498ff9a2 JL	82	#include <config_cmd_default.h>
	83
	84	#define CONFIG_CMD_BOOTD
	85	#define CONFIG_CMD_CACHE
	86	#define CONFIG_CMD_DHCP
	87	#define CONFIG_CMD_DIAG
	88	#define CONFIG_CMD_EEPROM
	89	#define CONFIG_CMD_ELF
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_CMD_NET
	92	#define CONFIG_CMD_NFS
	93	#define CONFIG_CMD_PCI
	94	#define CONFIG_CMD_PING
	95	#define CONFIG_CMD_REGINFO
	96	#define CONFIG_CMD_SDRAM
	97	#define CONFIG_CMD_SNTP
	98
414eec35 WD	99
414eec35 WD	100	#define CONFIG_NET_MULTI
63ff004c	101	#define CONFIG_MII
983fda83	102
983fda83 WD	103	/*
	104	* Autobooting
	105	*/
	106	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	107	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	108	#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
e2ffd59b	109	#define CONFIG_HAS_ETH1
983fda83 WD	110	#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
	111	#define CONFIG_IPADDR 192.162.1.2
	112	#define CONFIG_NETMASK 255.255.255.0
	113	#define CONFIG_SERVERIP 192.162.1.1
	114	#define CONFIG_GATEWAYIP 192.162.1.1
	115	#define CONFIG_HOSTNAME Alaska
	116	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	117
	118
	119	/*
	120	* I2C configuration
	121	*/
	122	#define CONFIG_HARD_I2C 1
	123	#define CFG_I2C_MODULE 1
	124
	125	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	126	#define CFG_I2C_SLAVE 0x7F
	127
	128	/*
	129	* EEPROM configuration
	130	*/
	131	#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
	132	#define CFG_I2C_EEPROM_ADDR_LEN 1
	133	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	134	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
	135	/*
	136	#define CFG_ENV_IS_IN_EEPROM 1
	137	#define CFG_ENV_OFFSET 0
	138	#define CFG_ENV_SIZE 256
	139	*/
	140
	141	/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
	142	else undefined it will boot from Intel Strata flash */
	143	#define CFG_AMD_BOOT 1
	144
	145	/*
	146	* Flexbus Chipselect configuration
	147	*/
	148	#if defined (CFG_AMD_BOOT)
	149	#define CFG_CS0_BASE 0xfff0
	150	#define CFG_CS0_MASK 0x00080000 /* 512 KB */
	151	#define CFG_CS0_CTRL 0x003f0d40
	152
	153	#define CFG_CS1_BASE 0xfe00
	154	#define CFG_CS1_MASK 0x01000000 /* 16 MB */
	155	#define CFG_CS1_CTRL 0x003f1540
	156	#else
	157	#define CFG_CS0_BASE 0xff00
	158	#define CFG_CS0_MASK 0x01000000 /* 16 MB */
	159	#define CFG_CS0_CTRL 0x003f1540
	160
	161	#define CFG_CS1_BASE 0xfe08
	162	#define CFG_CS1_MASK 0x00080000 /* 512 KB */
	163	#define CFG_CS1_CTRL 0x003f0d40
	164	#endif
	165
	166	#define CFG_CS2_BASE 0xf100
	167	#define CFG_CS2_MASK 0x00040000
	168	#define CFG_CS2_CTRL 0x003f1140
	169
	170	#define CFG_CS3_BASE 0xf200
	171	#define CFG_CS3_MASK 0x00040000
	172	#define CFG_CS3_CTRL 0x003f1100
	173
174
175	#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
176	#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
177
178	#if defined (CFG_AMD_BOOT)
179	#define CFG_AMD_BASE CFG_FLASH0_BASE
180	#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
181	#define CFG_FLASH_BASE CFG_AMD_BASE
182	#else
183	#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
184	#define CFG_AMD_BASE CFG_FLASH1_BASE
185	#define CFG_FLASH_BASE CFG_INTEL_BASE
186	#endif
187
188	#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
189	#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
190
191
192	#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
193	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
194
195	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
196	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
197	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
198	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
199	#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
200
201	#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
202	#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
203
204	#define CFG_FLASH_CHECKSUM
205	/*
206	* Environment settings
207	*/
208	#define CFG_ENV_IS_IN_FLASH 1
209	#if defined (CFG_AMD_BOOT)
210	#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
211	#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
212	#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
213	#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
214	#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
215	#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
216	#else
217	#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
218	#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
219	#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
220	#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
221	#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
222	#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
223	#endif
224
225	#define CONFIG_ENV_OVERWRITE 1
226
227	#if defined CFG_ENV_IS_IN_FLASH
228	#undef CFG_ENV_IS_IN_NVRAM
229	#undef CFG_ENV_IS_IN_EEPROM
230	#elif defined CFG_ENV_IS_IN_NVRAM
231	#undef CFG_ENV_IS_IN_FLASH
232	#undef CFG_ENV_IS_IN_EEPROM
233	#elif defined CFG_ENV_IS_IN_EEPROM
234	#undef CFG_ENV_IS_IN_NVRAM
235	#undef CFG_ENV_IS_IN_FLASH
236	#endif
237
983fda83 WD	238	/*
	239	* Memory map
	240	*/
	241	#define CFG_MBAR 0xF0000000
	242	#define CFG_SDRAM_BASE 0x00000000
	243	#define CFG_DEFAULT_MBAR 0x80000000
	244	#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
	245	#define CFG_SRAM_SIZE 0x8000
	246
	247	/* Use SRAM until RAM will be available */
	248	#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
	249	#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
	250
	251	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	252	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	253	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	254
	255	#define CFG_MONITOR_BASE TEXT_BASE
	256	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	257	# define CFG_RAMBOOT 1
	258	#endif
	259
	260	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	261	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	262	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	263
12b43d51	264	/* SDRAM configuration */
7680c140 WD	265	#define CFG_SDRAM_TOTAL_BANKS 2
	266	#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
	267	#define CFG_SDRAM_SPD_SIZE 0x40
	268	#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
	269
	270	/* SDRAM drive strength register */
	271	#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) \| \
	272	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) \| \
	273	(DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) \| \
	274	(DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) \| \
	275	(DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
12b43d51	276
983fda83 WD	277	/*
	278	* Ethernet configuration
	279	*/
	280	#define CONFIG_MPC8220_FEC 1
	281	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
	282	#define CONFIG_PHY_ADDR 0x18
	283
	284
	285	/*
	286	* Miscellaneous configurable options
	287	*/
	288	#define CFG_LONGHELP /* undef to save memory */
	289	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
498ff9a2	290	#if defined(CONFIG_CMD_KGDB)
983fda83 WD	291	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	292	#else
	293	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	294	#endif
	295	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	296	#define CFG_MAXARGS 16 /* max number of command args */
	297	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	298
	299	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	300	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	301
	302	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	303
	304	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	305
498ff9a2 JL	306	#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
	307	#if defined(CONFIG_CMD_KGDB)
	308	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	309	#endif
	310
983fda83 WD	311	/*
	312	* Various low-level settings
	313	*/
	314	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	315	#define CFG_HID0_FINAL HID0_ICE
	316
700a0c64 WD	317	/*
	318	* JFFS2 partitions
	319	*/
	320
	321	/* No command line, one static partition */
	322	/*
	323	#undef CONFIG_JFFS2_CMDLINE
	324	#define CONFIG_JFFS2_DEV "nor0"
	325	#define CONFIG_JFFS2_PART_SIZE 0x00400000
	326	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	327	*/
	328
	329	/* mtdparts command line support */
	330	/*
	331	#define CONFIG_JFFS2_CMDLINE
	332	#define MTDIDS_DEFAULT "nor0=alaska-0"
	333	#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
	334	*/
	335
983fda83	336	#endif /* __CONFIG_H */