[J-u-boot.git] / drivers / i2c / sun8i_rsb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 Hans de Goede <[email protected]>
 *
 * Based on allwinner u-boot sources rsb code which is:
 * (C) Copyright 2007-2013
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * lixiang <[email protected]>
 */

#include <axp_pmic.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
#include <sunxi_gpio.h>
#include <reset.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>

static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
{
	unsigned long tmo = timer_get_us() + 1000000;
	u32 stat;
	int ret;

	while (1) {
		stat = readl(&base->stat);
		if (stat & RSB_STAT_LBSY_INT) {
			ret = -EBUSY;
			break;
		}
		if (stat & RSB_STAT_TERR_INT) {
			ret = -EIO;
			break;
		}
		if (stat & RSB_STAT_TOVER_INT) {
			ret = 0;
			break;
		}
		if (timer_get_us() > tmo) {
			ret = -ETIME;
			break;
		}
	}
	writel(stat, &base->stat); /* Clear status bits */

	return ret;
}

static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
{
	setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);

	return sun8i_rsb_await_trans(base);
}

static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
			  u8 reg_addr, u8 *data)
{
	int ret;

	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	writel(reg_addr, &base->addr);
	writel(RSB_CMD_BYTE_READ, &base->cmd);

	ret = sun8i_rsb_do_trans(base);
	if (ret)
		return ret;

	*data = readl(&base->data) & 0xff;

	return 0;
}

static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
			   u8 reg_addr, u8 data)
{
	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	writel(reg_addr, &base->addr);
	writel(data, &base->data);
	writel(RSB_CMD_BYTE_WRITE, &base->cmd);

	return sun8i_rsb_do_trans(base);
}

static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
					u16 device_addr, u16 runtime_addr)
{
	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
	       RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
	writel(RSB_CMD_SET_RTSADDR, &base->cmd);

	return sun8i_rsb_do_trans(base);
}

static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
{
	u32 div = 0;
	u32 cd_odly = 0;

	/* Source is Hosc24M, set RSB clk to 3Mhz */
	div = 24000000 / 3000000 / 2 - 1;
	cd_odly = div >> 1;
	if (!cd_odly)
		cd_odly = 1;

	writel((cd_odly << 8) | div, &base->ccr);
}

static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
{
	unsigned long tmo = timer_get_us() + 1000000;

	writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
	       &base->dmcr);

	while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
		if (timer_get_us() > tmo)
			return -ETIME;
	}

	return sun8i_rsb_await_trans(base);
}

static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
{
	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
	sun8i_rsb_set_clk(base);

	return sun8i_rsb_set_device_mode(base);
}

#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
}

int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
}

int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
}

int rsb_init(void)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	/* Enable RSB and PIO clk, and de-assert their resets */
	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);

	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
	} else {
		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
	}

	return sun8i_rsb_init(base);
}
#endif

#if CONFIG_IS_ENABLED(DM_I2C)
struct sun8i_rsb_priv {
	struct sunxi_rsb_reg *base;
};

/*
 * The mapping from hardware address to runtime address is fixed, and shared
 * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
 */
static int sun8i_rsb_get_runtime_address(u16 device_addr)
{
	if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
		return AXP_PMIC_PRI_RUNTIME_ADDR;
	if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
		return AXP_PMIC_SEC_RUNTIME_ADDR;

	return -ENXIO;
}

static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
	int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);

	if (runtime_addr < 0)
		return runtime_addr;

	/* The hardware only supports SMBus-style transfers. */
	if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
		return sun8i_rsb_read(priv->base, runtime_addr,
				      msg[0].buf[0], &msg[1].buf[0]);

	if (nmsgs == 1 && msg[0].len == 2)
		return sun8i_rsb_write(priv->base, runtime_addr,
				       msg[0].buf[0], msg[0].buf[1]);

	return -EINVAL;
}

static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
				uint chip_flags)
{
	int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);

	if (runtime_addr < 0)
		return runtime_addr;

	return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
}

static int sun8i_rsb_probe(struct udevice *bus)
{
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	struct reset_ctl *reset;
	struct clk *clk;

	priv->base = dev_read_addr_ptr(bus);

	reset = devm_reset_control_get(bus, NULL);
	if (!IS_ERR(reset))
		reset_deassert(reset);

	clk = devm_clk_get(bus, NULL);
	if (!IS_ERR(clk))
		clk_enable(clk);

	return sun8i_rsb_init(priv->base);
}

static int sun8i_rsb_child_pre_probe(struct udevice *child)
{
	struct dm_i2c_chip *chip = dev_get_parent_plat(child);
	struct udevice *bus = child->parent;

	/* Ensure each transfer is for a single register. */
	chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;

	return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
}

static const struct dm_i2c_ops sun8i_rsb_ops = {
	.xfer		= sun8i_rsb_xfer,
	.probe_chip	= sun8i_rsb_probe_chip,
};

static const struct udevice_id sun8i_rsb_ids[] = {
	{ .compatible = "allwinner,sun8i-a23-rsb" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(sun8i_rsb) = {
	.name			= "sun8i_rsb",
	.id			= UCLASS_I2C,
	.of_match		= sun8i_rsb_ids,
	.probe			= sun8i_rsb_probe,
	.child_pre_probe	= sun8i_rsb_child_pre_probe,
	.priv_auto		= sizeof(struct sun8i_rsb_priv),
	.ops			= &sun8i_rsb_ops,
};
#endif /* CONFIG_IS_ENABLED(DM_I2C) */
Commit	Line	Data
3227c85f SH	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 Hans de Goede <[email protected]>
	4	*
	5	* Based on allwinner u-boot sources rsb code which is:
	6	* (C) Copyright 2007-2013
	7	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	8	* lixiang <[email protected]>
	9	*/
	10
	11	#include <axp_pmic.h>
f5bfe157	12	#include <clk.h>
3227c85f SH	13	#include <dm.h>
	14	#include <errno.h>
	15	#include <i2c.h>
207ed0a3	16	#include <sunxi_gpio.h>
f5bfe157	17	#include <reset.h>
3227c85f SH	18	#include <time.h>
3227c85f SH	19	#include <asm/arch/cpu.h>
3227c85f SH	20	#include <asm/arch/prcm.h>
	21	#include <asm/arch/rsb.h>
	22
	23	static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
	24	{
	25	unsigned long tmo = timer_get_us() + 1000000;
	26	u32 stat;
	27	int ret;
	28
	29	while (1) {
	30	stat = readl(&base->stat);
	31	if (stat & RSB_STAT_LBSY_INT) {
	32	ret = -EBUSY;
	33	break;
	34	}
	35	if (stat & RSB_STAT_TERR_INT) {
	36	ret = -EIO;
	37	break;
	38	}
	39	if (stat & RSB_STAT_TOVER_INT) {
	40	ret = 0;
	41	break;
	42	}
	43	if (timer_get_us() > tmo) {
	44	ret = -ETIME;
	45	break;
	46	}
	47	}
	48	writel(stat, &base->stat); /* Clear status bits */
	49
	50	return ret;
	51	}
	52
	53	static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
	54	{
	55	setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
	56
	57	return sun8i_rsb_await_trans(base);
	58	}
	59
	60	static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
	61	u8 reg_addr, u8 *data)
	62	{
	63	int ret;
	64
	65	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	66	writel(reg_addr, &base->addr);
	67	writel(RSB_CMD_BYTE_READ, &base->cmd);
	68
	69	ret = sun8i_rsb_do_trans(base);
	70	if (ret)
	71	return ret;
	72
	73	*data = readl(&base->data) & 0xff;
	74
	75	return 0;
	76	}
	77
	78	static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
	79	u8 reg_addr, u8 data)
	80	{
	81	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	82	writel(reg_addr, &base->addr);
	83	writel(data, &base->data);
84	writel(RSB_CMD_BYTE_WRITE, &base->cmd);
85
86	return sun8i_rsb_do_trans(base);
87	}
88
89	static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
90	u16 device_addr, u16 runtime_addr)
91	{
92	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) \|
93	RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
94	writel(RSB_CMD_SET_RTSADDR, &base->cmd);
95
96	return sun8i_rsb_do_trans(base);
97	}
98
3227c85f SH	99	static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
	100	{
	101	u32 div = 0;
	102	u32 cd_odly = 0;
	103
	104	/* Source is Hosc24M, set RSB clk to 3Mhz */
	105	div = 24000000 / 3000000 / 2 - 1;
	106	cd_odly = div >> 1;
	107	if (!cd_odly)
	108	cd_odly = 1;
	109
	110	writel((cd_odly << 8) \| div, &base->ccr);
	111	}
	112
	113	static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
	114	{
	115	unsigned long tmo = timer_get_us() + 1000000;
	116
	117	writel(RSB_DMCR_DEVICE_MODE_START \| RSB_DMCR_DEVICE_MODE_DATA,
	118	&base->dmcr);
	119
	120	while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
	121	if (timer_get_us() > tmo)
	122	return -ETIME;
	123	}
	124
	125	return sun8i_rsb_await_trans(base);
	126	}
	127
	128	static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
	129	{
3227c85f SH	130	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
	131	sun8i_rsb_set_clk(base);
	132
	133	return sun8i_rsb_set_device_mode(base);
	134	}
	135
	136	#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
	137	int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
	138	{
	139	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	140
	141	return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
	142	}
	143
	144	int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
	145	{
	146	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	147
	148	return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
	149	}
	150
	151	int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
	152	{
	153	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	154
	155	return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
	156	}
	157
	158	int rsb_init(void)
	159	{
	160	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	161
af2ec35c SH	162	/* Enable RSB and PIO clk, and de-assert their resets */
	163	prcm_apb0_enable(PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_RSB);
	164
	165	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
	166	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
	167	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
	168	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
	169	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
	170	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
	171	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
	172	} else {
	173	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
	174	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
	175	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
	176	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
	177	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
	178	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
	179	}
	180
3227c85f SH	181	return sun8i_rsb_init(base);
	182	}
	183	#endif
	184
	185	#if CONFIG_IS_ENABLED(DM_I2C)
	186	struct sun8i_rsb_priv {
	187	struct sunxi_rsb_reg *base;
	188	};
	189
	190	/*
	191	* The mapping from hardware address to runtime address is fixed, and shared
	192	* among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
	193	*/
	194	static int sun8i_rsb_get_runtime_address(u16 device_addr)
	195	{
	196	if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
	197	return AXP_PMIC_PRI_RUNTIME_ADDR;
	198	if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
	199	return AXP_PMIC_SEC_RUNTIME_ADDR;
	200
	201	return -ENXIO;
	202	}
	203
	204	static int sun8i_rsb_xfer(struct udevice bus, struct i2c_msg msg, int nmsgs)
	205	{
	206	int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
	207	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	208
	209	if (runtime_addr < 0)
	210	return runtime_addr;
	211
	212	/* The hardware only supports SMBus-style transfers. */
	213	if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
	214	return sun8i_rsb_read(priv->base, runtime_addr,
	215	msg[0].buf[0], &msg[1].buf[0]);
	216
	217	if (nmsgs == 1 && msg[0].len == 2)
	218	return sun8i_rsb_write(priv->base, runtime_addr,
	219	msg[0].buf[0], msg[0].buf[1]);
	220
	221	return -EINVAL;
	222	}
	223
	224	static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
	225	uint chip_flags)
	226	{
	227	int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
	228	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	229
	230	if (runtime_addr < 0)
	231	return runtime_addr;
	232
	233	return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
	234	}
	235
	236	static int sun8i_rsb_probe(struct udevice *bus)
	237	{
	238	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
f5bfe157 SH	239	struct reset_ctl *reset;
f5bfe157 SH	240	struct clk *clk;
3227c85f SH	241
	242	priv->base = dev_read_addr_ptr(bus);
	243
f5bfe157 SH	244	reset = devm_reset_control_get(bus, NULL);
	245	if (!IS_ERR(reset))
	246	reset_deassert(reset);
	247
	248	clk = devm_clk_get(bus, NULL);
	249	if (!IS_ERR(clk))
	250	clk_enable(clk);
	251
3227c85f SH	252	return sun8i_rsb_init(priv->base);
	253	}
	254
	255	static int sun8i_rsb_child_pre_probe(struct udevice *child)
	256	{
	257	struct dm_i2c_chip *chip = dev_get_parent_plat(child);
c9dd3caa	258	struct udevice *bus = child->parent;
3227c85f SH	259
	260	/* Ensure each transfer is for a single register. */
	261	chip->flags \|= DM_I2C_CHIP_RD_ADDRESS \| DM_I2C_CHIP_WR_ADDRESS;
	262
c9dd3caa	263	return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
3227c85f SH	264	}
	265
	266	static const struct dm_i2c_ops sun8i_rsb_ops = {
	267	.xfer = sun8i_rsb_xfer,
	268	.probe_chip = sun8i_rsb_probe_chip,
	269	};
	270
	271	static const struct udevice_id sun8i_rsb_ids[] = {
	272	{ .compatible = "allwinner,sun8i-a23-rsb" },
	273	{ /* sentinel */ }
	274	};
	275
	276	U_BOOT_DRIVER(sun8i_rsb) = {
	277	.name = "sun8i_rsb",
	278	.id = UCLASS_I2C,
	279	.of_match = sun8i_rsb_ids,
	280	.probe = sun8i_rsb_probe,
	281	.child_pre_probe = sun8i_rsb_child_pre_probe,
	282	.priv_auto = sizeof(struct sun8i_rsb_priv),
	283	.ops = &sun8i_rsb_ops,
	284	};
	285	#endif /* CONFIG_IS_ENABLED(DM_I2C) */