[J-u-boot.git] / drivers / i2c / sun8i_rsb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 Hans de Goede <[email protected]>
 *
 * Based on allwinner u-boot sources rsb code which is:
 * (C) Copyright 2007-2013
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * lixiang <[email protected]>
 */

#include <axp_pmic.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>

static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
{
	unsigned long tmo = timer_get_us() + 1000000;
	u32 stat;
	int ret;

	while (1) {
		stat = readl(&base->stat);
		if (stat & RSB_STAT_LBSY_INT) {
			ret = -EBUSY;
			break;
		}
		if (stat & RSB_STAT_TERR_INT) {
			ret = -EIO;
			break;
		}
		if (stat & RSB_STAT_TOVER_INT) {
			ret = 0;
			break;
		}
		if (timer_get_us() > tmo) {
			ret = -ETIME;
			break;
		}
	}
	writel(stat, &base->stat); /* Clear status bits */

	return ret;
}

static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
{
	setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);

	return sun8i_rsb_await_trans(base);
}

static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
			  u8 reg_addr, u8 *data)
{
	int ret;

	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	writel(reg_addr, &base->addr);
	writel(RSB_CMD_BYTE_READ, &base->cmd);

	ret = sun8i_rsb_do_trans(base);
	if (ret)
		return ret;

	*data = readl(&base->data) & 0xff;

	return 0;
}

static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
			   u8 reg_addr, u8 data)
{
	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
	writel(reg_addr, &base->addr);
	writel(data, &base->data);
	writel(RSB_CMD_BYTE_WRITE, &base->cmd);

	return sun8i_rsb_do_trans(base);
}

static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
					u16 device_addr, u16 runtime_addr)
{
	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
	       RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
	writel(RSB_CMD_SET_RTSADDR, &base->cmd);

	return sun8i_rsb_do_trans(base);
}

static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
{
	u32 div = 0;
	u32 cd_odly = 0;

	/* Source is Hosc24M, set RSB clk to 3Mhz */
	div = 24000000 / 3000000 / 2 - 1;
	cd_odly = div >> 1;
	if (!cd_odly)
		cd_odly = 1;

	writel((cd_odly << 8) | div, &base->ccr);
}

static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
{
	unsigned long tmo = timer_get_us() + 1000000;

	writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
	       &base->dmcr);

	while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
		if (timer_get_us() > tmo)
			return -ETIME;
	}

	return sun8i_rsb_await_trans(base);
}

static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
{
	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
	sun8i_rsb_set_clk(base);

	return sun8i_rsb_set_device_mode(base);
}

#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
}

int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
}

int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
}

int rsb_init(void)
{
	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;

	/* Enable RSB and PIO clk, and de-assert their resets */
	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);

	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
	} else {
		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
	}

	return sun8i_rsb_init(base);
}
#endif

#if CONFIG_IS_ENABLED(DM_I2C)
struct sun8i_rsb_priv {
	struct sunxi_rsb_reg *base;
};

/*
 * The mapping from hardware address to runtime address is fixed, and shared
 * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
 */
static int sun8i_rsb_get_runtime_address(u16 device_addr)
{
	if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
		return AXP_PMIC_PRI_RUNTIME_ADDR;
	if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
		return AXP_PMIC_SEC_RUNTIME_ADDR;

	return -ENXIO;
}

static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
	int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);

	if (runtime_addr < 0)
		return runtime_addr;

	/* The hardware only supports SMBus-style transfers. */
	if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
		return sun8i_rsb_read(priv->base, runtime_addr,
				      msg[0].buf[0], &msg[1].buf[0]);

	if (nmsgs == 1 && msg[0].len == 2)
		return sun8i_rsb_write(priv->base, runtime_addr,
				       msg[0].buf[0], msg[0].buf[1]);

	return -EINVAL;
}

static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
				uint chip_flags)
{
	int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);

	if (runtime_addr < 0)
		return runtime_addr;

	return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
}

static int sun8i_rsb_probe(struct udevice *bus)
{
	struct sun8i_rsb_priv *priv = dev_get_priv(bus);

	priv->base = dev_read_addr_ptr(bus);

	return sun8i_rsb_init(priv->base);
}

static int sun8i_rsb_child_pre_probe(struct udevice *child)
{
	struct dm_i2c_chip *chip = dev_get_parent_plat(child);
	struct udevice *bus = child->parent;

	/* Ensure each transfer is for a single register. */
	chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;

	return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
}

static const struct dm_i2c_ops sun8i_rsb_ops = {
	.xfer		= sun8i_rsb_xfer,
	.probe_chip	= sun8i_rsb_probe_chip,
};

static const struct udevice_id sun8i_rsb_ids[] = {
	{ .compatible = "allwinner,sun8i-a23-rsb" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(sun8i_rsb) = {
	.name			= "sun8i_rsb",
	.id			= UCLASS_I2C,
	.of_match		= sun8i_rsb_ids,
	.probe			= sun8i_rsb_probe,
	.child_pre_probe	= sun8i_rsb_child_pre_probe,
	.priv_auto		= sizeof(struct sun8i_rsb_priv),
	.ops			= &sun8i_rsb_ops,
};
#endif /* CONFIG_IS_ENABLED(DM_I2C) */
Commit	Line	Data
3227c85f SH	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 Hans de Goede <[email protected]>
	4	*
	5	* Based on allwinner u-boot sources rsb code which is:
	6	* (C) Copyright 2007-2013
	7	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	8	* lixiang <[email protected]>
	9	*/
	10
	11	#include <axp_pmic.h>
	12	#include <common.h>
	13	#include <dm.h>
	14	#include <errno.h>
	15	#include <i2c.h>
	16	#include <time.h>
	17	#include <asm/arch/cpu.h>
	18	#include <asm/arch/gpio.h>
	19	#include <asm/arch/prcm.h>
	20	#include <asm/arch/rsb.h>
	21
	22	static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
	23	{
	24	unsigned long tmo = timer_get_us() + 1000000;
	25	u32 stat;
	26	int ret;
	27
	28	while (1) {
	29	stat = readl(&base->stat);
	30	if (stat & RSB_STAT_LBSY_INT) {
	31	ret = -EBUSY;
	32	break;
	33	}
	34	if (stat & RSB_STAT_TERR_INT) {
	35	ret = -EIO;
	36	break;
	37	}
	38	if (stat & RSB_STAT_TOVER_INT) {
	39	ret = 0;
	40	break;
	41	}
	42	if (timer_get_us() > tmo) {
	43	ret = -ETIME;
	44	break;
	45	}
	46	}
	47	writel(stat, &base->stat); /* Clear status bits */
	48
	49	return ret;
	50	}
	51
	52	static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
	53	{
	54	setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
	55
	56	return sun8i_rsb_await_trans(base);
	57	}
	58
	59	static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
	60	u8 reg_addr, u8 *data)
	61	{
	62	int ret;
	63
	64	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
65	writel(reg_addr, &base->addr);
66	writel(RSB_CMD_BYTE_READ, &base->cmd);
67
68	ret = sun8i_rsb_do_trans(base);
69	if (ret)
70	return ret;
71
72	*data = readl(&base->data) & 0xff;
73
74	return 0;
75	}
76
77	static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
78	u8 reg_addr, u8 data)
79	{
80	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
81	writel(reg_addr, &base->addr);
82	writel(data, &base->data);
83	writel(RSB_CMD_BYTE_WRITE, &base->cmd);
84
85	return sun8i_rsb_do_trans(base);
86	}
87
88	static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
89	u16 device_addr, u16 runtime_addr)
90	{
91	writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) \|
92	RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
93	writel(RSB_CMD_SET_RTSADDR, &base->cmd);
94
95	return sun8i_rsb_do_trans(base);
96	}
97
3227c85f SH	98	static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
	99	{
	100	u32 div = 0;
	101	u32 cd_odly = 0;
	102
	103	/* Source is Hosc24M, set RSB clk to 3Mhz */
	104	div = 24000000 / 3000000 / 2 - 1;
	105	cd_odly = div >> 1;
	106	if (!cd_odly)
	107	cd_odly = 1;
	108
	109	writel((cd_odly << 8) \| div, &base->ccr);
	110	}
	111
	112	static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
	113	{
	114	unsigned long tmo = timer_get_us() + 1000000;
	115
	116	writel(RSB_DMCR_DEVICE_MODE_START \| RSB_DMCR_DEVICE_MODE_DATA,
	117	&base->dmcr);
	118
	119	while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
	120	if (timer_get_us() > tmo)
	121	return -ETIME;
	122	}
	123
	124	return sun8i_rsb_await_trans(base);
	125	}
	126
	127	static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
	128	{
3227c85f SH	129	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
	130	sun8i_rsb_set_clk(base);
	131
	132	return sun8i_rsb_set_device_mode(base);
	133	}
	134
	135	#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
	136	int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
	137	{
	138	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	139
	140	return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
	141	}
	142
	143	int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
	144	{
	145	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	146
	147	return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
	148	}
	149
	150	int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
	151	{
	152	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	153
	154	return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
	155	}
	156
	157	int rsb_init(void)
	158	{
	159	struct sunxi_rsb_reg base = (struct sunxi_rsb_reg )SUNXI_RSB_BASE;
	160
af2ec35c SH	161	/* Enable RSB and PIO clk, and de-assert their resets */
	162	prcm_apb0_enable(PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_RSB);
	163
	164	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
	165	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
	166	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
	167	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
	168	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
	169	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
	170	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
	171	} else {
	172	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
	173	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
	174	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
	175	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
	176	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
	177	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
	178	}
	179
3227c85f SH	180	return sun8i_rsb_init(base);
	181	}
	182	#endif
	183
	184	#if CONFIG_IS_ENABLED(DM_I2C)
	185	struct sun8i_rsb_priv {
	186	struct sunxi_rsb_reg *base;
	187	};
	188
	189	/*
	190	* The mapping from hardware address to runtime address is fixed, and shared
	191	* among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
	192	*/
	193	static int sun8i_rsb_get_runtime_address(u16 device_addr)
	194	{
	195	if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
	196	return AXP_PMIC_PRI_RUNTIME_ADDR;
	197	if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
	198	return AXP_PMIC_SEC_RUNTIME_ADDR;
	199
	200	return -ENXIO;
	201	}
	202
	203	static int sun8i_rsb_xfer(struct udevice bus, struct i2c_msg msg, int nmsgs)
	204	{
	205	int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
	206	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	207
	208	if (runtime_addr < 0)
	209	return runtime_addr;
	210
	211	/* The hardware only supports SMBus-style transfers. */
	212	if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
	213	return sun8i_rsb_read(priv->base, runtime_addr,
	214	msg[0].buf[0], &msg[1].buf[0]);
	215
	216	if (nmsgs == 1 && msg[0].len == 2)
	217	return sun8i_rsb_write(priv->base, runtime_addr,
	218	msg[0].buf[0], msg[0].buf[1]);
	219
	220	return -EINVAL;
	221	}
	222
	223	static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
	224	uint chip_flags)
	225	{
	226	int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
	227	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	228
	229	if (runtime_addr < 0)
	230	return runtime_addr;
	231
	232	return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
	233	}
	234
	235	static int sun8i_rsb_probe(struct udevice *bus)
	236	{
	237	struct sun8i_rsb_priv *priv = dev_get_priv(bus);
	238
	239	priv->base = dev_read_addr_ptr(bus);
	240
	241	return sun8i_rsb_init(priv->base);
	242	}
	243
244	static int sun8i_rsb_child_pre_probe(struct udevice *child)
245	{
246	struct dm_i2c_chip *chip = dev_get_parent_plat(child);
c9dd3caa	247	struct udevice *bus = child->parent;
3227c85f SH	248
	249	/* Ensure each transfer is for a single register. */
	250	chip->flags \|= DM_I2C_CHIP_RD_ADDRESS \| DM_I2C_CHIP_WR_ADDRESS;
	251
c9dd3caa	252	return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
3227c85f SH	253	}
	254
	255	static const struct dm_i2c_ops sun8i_rsb_ops = {
	256	.xfer = sun8i_rsb_xfer,
	257	.probe_chip = sun8i_rsb_probe_chip,
	258	};
	259
	260	static const struct udevice_id sun8i_rsb_ids[] = {
	261	{ .compatible = "allwinner,sun8i-a23-rsb" },
	262	{ /* sentinel */ }
	263	};
	264
	265	U_BOOT_DRIVER(sun8i_rsb) = {
	266	.name = "sun8i_rsb",
	267	.id = UCLASS_I2C,
	268	.of_match = sun8i_rsb_ids,
	269	.probe = sun8i_rsb_probe,
	270	.child_pre_probe = sun8i_rsb_child_pre_probe,
	271	.priv_auto = sizeof(struct sun8i_rsb_priv),
	272	.ops = &sun8i_rsb_ops,
	273	};
	274	#endif /* CONFIG_IS_ENABLED(DM_I2C) */