[J-u-boot.git] / board / Marvell / dreamplug / dreamplug.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2011
 * Jason Cooper <[email protected]>
 *
 * Based on work by:
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Siddarth Gore <[email protected]>
 */

#include <common.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include "dreamplug.h"

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
			  DREAMPLUG_OE_VAL_HIGH,
			  DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);

	/* Multi-Purpose Pins Functionality configuration */
	static const u32 kwmpp_config[] = {
		MPP0_SPI_SCn,		/* SPI Flash */
		MPP1_SPI_MOSI,
		MPP2_SPI_SCK,
		MPP3_SPI_MISO,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_TW_SDA,
		MPP9_TW_SCK,
		MPP10_UART0_TXD,	/* Serial */
		MPP11_UART0_RXD,
		MPP12_SD_CLK,		/* SDIO Slot */
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP20_GE1_0,		/* Gigabit Ethernet */
		MPP21_GE1_1,
		MPP22_GE1_2,
		MPP23_GE1_3,
		MPP24_GE1_4,
		MPP25_GE1_5,
		MPP26_GE1_6,
		MPP27_GE1_7,
		MPP28_GE1_8,
		MPP29_GE1_9,
		MPP30_GE1_10,
		MPP31_GE1_11,
		MPP32_GE1_12,
		MPP33_GE1_13,
		MPP34_GE1_14,
		MPP35_GE1_15,
		MPP36_GPIO,		/* 7 external GPIO pins (36 - 45) */
		MPP37_GPIO,
		MPP38_GPIO,
		MPP39_GPIO,
		MPP40_TDM_SPI_SCK,
		MPP41_TDM_SPI_MISO,
		MPP42_TDM_SPI_MOSI,
		MPP43_GPIO,
		MPP44_GPIO,
		MPP45_GPIO,
		MPP46_GPIO,
		MPP47_GPIO,		/* Bluetooth LED */
		MPP48_GPIO,		/* Wifi LED */
		MPP49_GPIO,		/* Wifi AP LED */
		0
	};
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void mv_phy_88e1116_init(char *name)
{
	u16 reg;
	u16 devadr;

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..%s could not read PHY dev address\n",
			__func__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}

void reset_phy(void)
{
	/* configure and initialize both PHY's */
	mv_phy_88e1116_init("egiga0");
	mv_phy_88e1116_init("egiga1");
}
#endif /* CONFIG_RESET_PHY_R */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2e0c1c7d JC	2	/*
	3	* (C) Copyright 2011
	4	* Jason Cooper <[email protected]>
	5	*
	6	* Based on work by:
	7	* Marvell Semiconductor <www.marvell.com>
	8	* Written-by: Siddarth Gore <[email protected]>
2e0c1c7d JC	9	*/
	10
	11	#include <common.h>
691d719d	12	#include <init.h>
2e0c1c7d	13	#include <miiphy.h>
5e6267af	14	#include <net.h>
0ac16bf3	15	#include <asm/arch/cpu.h>
3dc23f78	16	#include <asm/arch/soc.h>
2e0c1c7d JC	17	#include <asm/arch/mpp.h>
	18	#include "dreamplug.h"
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	int board_early_init_f(void)
	23	{
	24	/*
	25	* default gpio configuration
	26	* There are maximum 64 gpios controlled through 2 sets of registers
	27	* the below configuration configures mainly initial LED status
	28	*/
d5c5132f SR	29	mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
	30	DREAMPLUG_OE_VAL_HIGH,
	31	DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
2e0c1c7d JC	32
2e0c1c7d JC	33	/* Multi-Purpose Pins Functionality configuration */
9d86f0c3	34	static const u32 kwmpp_config[] = {
2e0c1c7d JC	35	MPP0_SPI_SCn, /* SPI Flash */
	36	MPP1_SPI_MOSI,
	37	MPP2_SPI_SCK,
	38	MPP3_SPI_MISO,
	39	MPP4_NF_IO6,
	40	MPP5_NF_IO7,
	41	MPP6_SYSRST_OUTn,
	42	MPP7_GPO,
	43	MPP8_TW_SDA,
	44	MPP9_TW_SCK,
	45	MPP10_UART0_TXD, /* Serial */
	46	MPP11_UART0_RXD,
	47	MPP12_SD_CLK, /* SDIO Slot */
	48	MPP13_SD_CMD,
	49	MPP14_SD_D0,
	50	MPP15_SD_D1,
	51	MPP16_SD_D2,
	52	MPP17_SD_D3,
	53	MPP18_NF_IO0,
	54	MPP19_NF_IO1,
	55	MPP20_GE1_0, /* Gigabit Ethernet */
	56	MPP21_GE1_1,
	57	MPP22_GE1_2,
	58	MPP23_GE1_3,
	59	MPP24_GE1_4,
	60	MPP25_GE1_5,
	61	MPP26_GE1_6,
	62	MPP27_GE1_7,
	63	MPP28_GE1_8,
	64	MPP29_GE1_9,
	65	MPP30_GE1_10,
	66	MPP31_GE1_11,
	67	MPP32_GE1_12,
	68	MPP33_GE1_13,
	69	MPP34_GE1_14,
	70	MPP35_GE1_15,
	71	MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
	72	MPP37_GPIO,
	73	MPP38_GPIO,
	74	MPP39_GPIO,
	75	MPP40_TDM_SPI_SCK,
	76	MPP41_TDM_SPI_MISO,
	77	MPP42_TDM_SPI_MOSI,
	78	MPP43_GPIO,
	79	MPP44_GPIO,
	80	MPP45_GPIO,
	81	MPP46_GPIO,
	82	MPP47_GPIO, /* Bluetooth LED */
	83	MPP48_GPIO, /* Wifi LED */
	84	MPP49_GPIO, /* Wifi AP LED */
	85	0
	86	};
84683638	87	kirkwood_mpp_conf(kwmpp_config, NULL);
2e0c1c7d JC	88	return 0;
	89	}
	90
	91	int board_init(void)
	92	{
	93	/* adress of boot parameters */
96c5f081	94	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
2e0c1c7d JC	95
	96	return 0;
	97	}
	98
	99	#ifdef CONFIG_RESET_PHY_R
	100	void mv_phy_88e1116_init(char *name)
	101	{
	102	u16 reg;
	103	u16 devadr;
	104
	105	if (miiphy_set_current_dev(name))
	106	return;
	107
	108	/* command to read PHY dev address */
	109	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
	110	printf("Err..%s could not read PHY dev address\n",
	111	__func__);
	112	return;
	113	}
	114
	115	/*
	116	* Enable RGMII delay on Tx and Rx for CPU port
	117	* Ref: sec 4.7.2 of chip datasheet
	118	*/
	119	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	120	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
	121	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	122	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
	123	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	124
	125	/* reset the phy */
	126	miiphy_reset(name, devadr);
	127
	128	printf("88E1116 Initialized on %s\n", name);
	129	}
	130
	131	void reset_phy(void)
	132	{
	133	/* configure and initialize both PHY's */
	134	mv_phy_88e1116_init("egiga0");
	135	mv_phy_88e1116_init("egiga1");
	136	}
	137	#endif /* CONFIG_RESET_PHY_R */