[J-u-boot.git] / board / Marvell / dreamplug / dreamplug.c

/*
 * (C) Copyright 2011
 * Jason Cooper <[email protected]>
 *
 * Based on work by:
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Siddarth Gore <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "dreamplug.h"

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
			DREAMPLUG_OE_VAL_HIGH,
			DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);

	/* Multi-Purpose Pins Functionality configuration */
	u32 kwmpp_config[] = {
		MPP0_SPI_SCn,		/* SPI Flash */
		MPP1_SPI_MOSI,
		MPP2_SPI_SCK,
		MPP3_SPI_MISO,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_TW_SDA,
		MPP9_TW_SCK,
		MPP10_UART0_TXD,	/* Serial */
		MPP11_UART0_RXD,
		MPP12_SD_CLK,		/* SDIO Slot */
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP20_GE1_0,		/* Gigabit Ethernet */
		MPP21_GE1_1,
		MPP22_GE1_2,
		MPP23_GE1_3,
		MPP24_GE1_4,
		MPP25_GE1_5,
		MPP26_GE1_6,
		MPP27_GE1_7,
		MPP28_GE1_8,
		MPP29_GE1_9,
		MPP30_GE1_10,
		MPP31_GE1_11,
		MPP32_GE1_12,
		MPP33_GE1_13,
		MPP34_GE1_14,
		MPP35_GE1_15,
		MPP36_GPIO,		/* 7 external GPIO pins (36 - 45) */
		MPP37_GPIO,
		MPP38_GPIO,
		MPP39_GPIO,
		MPP40_TDM_SPI_SCK,
		MPP41_TDM_SPI_MISO,
		MPP42_TDM_SPI_MOSI,
		MPP43_GPIO,
		MPP44_GPIO,
		MPP45_GPIO,
		MPP46_GPIO,
		MPP47_GPIO,		/* Bluetooth LED */
		MPP48_GPIO,		/* Wifi LED */
		MPP49_GPIO,		/* Wifi AP LED */
		0
	};
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void mv_phy_88e1116_init(char *name)
{
	u16 reg;
	u16 devadr;

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..%s could not read PHY dev address\n",
			__func__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}

void reset_phy(void)
{
	/* configure and initialize both PHY's */
	mv_phy_88e1116_init("egiga0");
	mv_phy_88e1116_init("egiga1");
}
#endif /* CONFIG_RESET_PHY_R */
Commit	Line	Data
2e0c1c7d JC	1	/*
	2	* (C) Copyright 2011
	3	* Jason Cooper <[email protected]>
	4	*
	5	* Based on work by:
	6	* Marvell Semiconductor <www.marvell.com>
	7	* Written-by: Siddarth Gore <[email protected]>
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	25	* MA 02110-1301 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <miiphy.h>
0ac16bf3	30	#include <asm/arch/cpu.h>
2e0c1c7d JC	31	#include <asm/arch/kirkwood.h>
	32	#include <asm/arch/mpp.h>
	33	#include "dreamplug.h"
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	int board_early_init_f(void)
	38	{
	39	/*
	40	* default gpio configuration
	41	* There are maximum 64 gpios controlled through 2 sets of registers
	42	* the below configuration configures mainly initial LED status
	43	*/
	44	kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
	45	DREAMPLUG_OE_VAL_HIGH,
	46	DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
	47
	48	/* Multi-Purpose Pins Functionality configuration */
	49	u32 kwmpp_config[] = {
	50	MPP0_SPI_SCn, /* SPI Flash */
	51	MPP1_SPI_MOSI,
	52	MPP2_SPI_SCK,
	53	MPP3_SPI_MISO,
	54	MPP4_NF_IO6,
	55	MPP5_NF_IO7,
	56	MPP6_SYSRST_OUTn,
	57	MPP7_GPO,
	58	MPP8_TW_SDA,
	59	MPP9_TW_SCK,
	60	MPP10_UART0_TXD, /* Serial */
	61	MPP11_UART0_RXD,
	62	MPP12_SD_CLK, /* SDIO Slot */
	63	MPP13_SD_CMD,
	64	MPP14_SD_D0,
	65	MPP15_SD_D1,
	66	MPP16_SD_D2,
	67	MPP17_SD_D3,
	68	MPP18_NF_IO0,
	69	MPP19_NF_IO1,
	70	MPP20_GE1_0, /* Gigabit Ethernet */
	71	MPP21_GE1_1,
	72	MPP22_GE1_2,
	73	MPP23_GE1_3,
	74	MPP24_GE1_4,
	75	MPP25_GE1_5,
	76	MPP26_GE1_6,
	77	MPP27_GE1_7,
	78	MPP28_GE1_8,
	79	MPP29_GE1_9,
	80	MPP30_GE1_10,
	81	MPP31_GE1_11,
	82	MPP32_GE1_12,
	83	MPP33_GE1_13,
	84	MPP34_GE1_14,
	85	MPP35_GE1_15,
	86	MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
	87	MPP37_GPIO,
	88	MPP38_GPIO,
	89	MPP39_GPIO,
	90	MPP40_TDM_SPI_SCK,
	91	MPP41_TDM_SPI_MISO,
	92	MPP42_TDM_SPI_MOSI,
	93	MPP43_GPIO,
	94	MPP44_GPIO,
95	MPP45_GPIO,
96	MPP46_GPIO,
97	MPP47_GPIO, /* Bluetooth LED */
98	MPP48_GPIO, /* Wifi LED */
99	MPP49_GPIO, /* Wifi AP LED */
100	0
101	};
84683638	102	kirkwood_mpp_conf(kwmpp_config, NULL);
2e0c1c7d JC	103	return 0;
	104	}
	105
	106	int board_init(void)
	107	{
	108	/* adress of boot parameters */
	109	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
	110
	111	return 0;
	112	}
	113
	114	#ifdef CONFIG_RESET_PHY_R
	115	void mv_phy_88e1116_init(char *name)
	116	{
	117	u16 reg;
	118	u16 devadr;
	119
	120	if (miiphy_set_current_dev(name))
	121	return;
	122
	123	/* command to read PHY dev address */
	124	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
	125	printf("Err..%s could not read PHY dev address\n",
	126	__func__);
	127	return;
	128	}
	129
	130	/*
	131	* Enable RGMII delay on Tx and Rx for CPU port
	132	* Ref: sec 4.7.2 of chip datasheet
	133	*/
	134	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	135	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
	136	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	137	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
	138	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	139
	140	/* reset the phy */
	141	miiphy_reset(name, devadr);
	142
	143	printf("88E1116 Initialized on %s\n", name);
	144	}
	145
	146	void reset_phy(void)
	147	{
	148	/* configure and initialize both PHY's */
	149	mv_phy_88e1116_init("egiga0");
	150	mv_phy_88e1116_init("egiga1");
	151	}
	152	#endif /* CONFIG_RESET_PHY_R */