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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d67b0d97 EN |
2 | /* |
3 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * Configuration settings for the Boundary Devices Nitrogen6X | |
6 | * and Freescale i.MX6Q Sabre Lite boards. | |
d67b0d97 EN |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
02824dc7 | 12 | #include "mx6_common.h" |
d67b0d97 EN |
13 | |
14 | #define CONFIG_MACH_TYPE 3769 | |
15 | ||
d67b0d97 EN |
16 | /* Size of malloc() pool */ |
17 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
18 | ||
f3d7cff5 | 19 | #define CONFIG_USBD_HS |
d67b0d97 | 20 | |
d67b0d97 EN |
21 | #define CONFIG_MXC_UART_BASE UART2_BASE |
22 | ||
d67b0d97 | 23 | /* I2C Configs */ |
b089d039 | 24 | #define CONFIG_SYS_I2C_MXC |
03544c66 AA |
25 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
26 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 27 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
d67b0d97 | 28 | #define CONFIG_SYS_I2C_SPEED 100000 |
5dbdc3cf | 29 | #define CONFIG_I2C_EDID |
d67b0d97 | 30 | |
d67b0d97 | 31 | /* MMC Configs */ |
d67b0d97 EN |
32 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
33 | #define CONFIG_SYS_FSL_USDHC_NUM 2 | |
34 | ||
d67b0d97 EN |
35 | /* |
36 | * SATA Configs | |
37 | */ | |
38 | #ifdef CONFIG_CMD_SATA | |
d67b0d97 EN |
39 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
40 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
41 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
42 | #define CONFIG_LBA48 | |
d67b0d97 EN |
43 | #endif |
44 | ||
d67b0d97 | 45 | #define CONFIG_FEC_MXC |
d67b0d97 EN |
46 | #define IMX_FEC_BASE ENET_BASE_ADDR |
47 | #define CONFIG_FEC_XCV_TYPE RGMII | |
48 | #define CONFIG_ETHPRIME "FEC" | |
49 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
d67b0d97 EN |
50 | |
51 | /* USB Configs */ | |
d1a52860 TK |
52 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
53 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
d67b0d97 EN |
54 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
55 | #define CONFIG_MXC_USB_FLAGS 0 | |
56 | ||
d67b0d97 | 57 | /* Framebuffer and LCD */ |
761bc195 | 58 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) |
5ea7f0e3 | 59 | #define CONFIG_IMX_HDMI |
a47e4495 | 60 | #define CONFIG_IMX_VIDEO_SKIP |
d67b0d97 | 61 | |
cc5d7dcb GG |
62 | #ifdef CONFIG_CMD_MMC |
63 | #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) | |
d67b0d97 | 64 | #else |
cc5d7dcb | 65 | #define DISTRO_BOOT_DEV_MMC(func) |
d67b0d97 EN |
66 | #endif |
67 | ||
cc5d7dcb GG |
68 | #ifdef CONFIG_CMD_SATA |
69 | #define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0) | |
d67b0d97 | 70 | #else |
cc5d7dcb | 71 | #define DISTRO_BOOT_DEV_SATA(func) |
d67b0d97 EN |
72 | #endif |
73 | ||
5b7103e0 | 74 | #ifdef CONFIG_USB_STORAGE |
cc5d7dcb | 75 | #define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0) |
5b7103e0 | 76 | #else |
cc5d7dcb GG |
77 | #define DISTRO_BOOT_DEV_USB(func) |
78 | #endif | |
79 | ||
80 | #ifdef CONFIG_CMD_PXE | |
81 | #define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na) | |
82 | #else | |
83 | #define DISTRO_BOOT_DEV_PXE(func) | |
84 | #endif | |
85 | ||
86 | #ifdef CONFIG_CMD_DHCP | |
87 | #define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na) | |
88 | #else | |
89 | #define DISTRO_BOOT_DEV_DHCP(func) | |
5b7103e0 DR |
90 | #endif |
91 | ||
d67b0d97 | 92 | |
f8b1e86d | 93 | #if defined(CONFIG_SABRELITE) |
cc5d7dcb GG |
94 | #define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" |
95 | #else | |
96 | /* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ | |
97 | #define FDTFILE | |
98 | #endif | |
99 | ||
100 | #define BOOT_TARGET_DEVICES(func) \ | |
101 | DISTRO_BOOT_DEV_MMC(func) \ | |
102 | DISTRO_BOOT_DEV_SATA(func) \ | |
103 | DISTRO_BOOT_DEV_USB(func) \ | |
104 | DISTRO_BOOT_DEV_PXE(func) \ | |
105 | DISTRO_BOOT_DEV_DHCP(func) | |
106 | ||
107 | #include <config_distro_bootcmd.h> | |
1af3c7f4 | 108 | #include <linux/stringify.h> |
cc5d7dcb | 109 | |
f8b1e86d | 110 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
f8b1e86d FE |
111 | "console=ttymxc1\0" \ |
112 | "fdt_high=0xffffffff\0" \ | |
113 | "initrd_high=0xffffffff\0" \ | |
cc5d7dcb GG |
114 | "fdt_addr_r=0x18000000\0" \ |
115 | FDTFILE \ | |
116 | "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ | |
117 | "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ | |
118 | "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ | |
119 | "ramdisk_addr_r=0x13000000\0" \ | |
120 | "ramdiskaddr=0x13000000\0" \ | |
f8b1e86d | 121 | "ip_dyn=yes\0" \ |
1c3e62d6 | 122 | "usb_pgood_delay=2000\0" \ |
cc5d7dcb | 123 | BOOTENV |
d67b0d97 EN |
124 | |
125 | /* Miscellaneous configurable options */ | |
d67b0d97 | 126 | |
d67b0d97 | 127 | /* Physical Memory Map */ |
d67b0d97 EN |
128 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
129 | ||
130 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
131 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
132 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
133 | ||
134 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
135 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
136 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
137 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
138 | ||
056845c2 | 139 | /* Environment organization */ |
d67b0d97 | 140 | |
147f8fa3 MV |
141 | /* |
142 | * PCI express | |
143 | */ | |
147f8fa3 | 144 | #ifdef CONFIG_CMD_PCI |
147f8fa3 MV |
145 | #define CONFIG_PCI_SCAN_SHOW |
146 | #define CONFIG_PCIE_IMX | |
147 | #endif | |
148 | ||
d67b0d97 | 149 | #endif /* __CONFIG_H */ |