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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d67b0d97 EN |
2 | /* |
3 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * Configuration settings for the Boundary Devices Nitrogen6X | |
6 | * and Freescale i.MX6Q Sabre Lite boards. | |
d67b0d97 EN |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
02824dc7 | 12 | #include "mx6_common.h" |
d67b0d97 EN |
13 | |
14 | #define CONFIG_MACH_TYPE 3769 | |
15 | ||
d67b0d97 EN |
16 | /* Size of malloc() pool */ |
17 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
18 | ||
f3d7cff5 | 19 | #define CONFIG_USBD_HS |
f3d7cff5 | 20 | #define CONFIG_NETCONSOLE |
d67b0d97 EN |
21 | |
22 | #define CONFIG_MXC_UART | |
23 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
24 | ||
d67b0d97 | 25 | /* I2C Configs */ |
b089d039 | 26 | #define CONFIG_SYS_I2C |
27 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
28 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
29 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 30 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
d67b0d97 | 31 | #define CONFIG_SYS_I2C_SPEED 100000 |
5dbdc3cf | 32 | #define CONFIG_I2C_EDID |
d67b0d97 | 33 | |
d67b0d97 | 34 | /* MMC Configs */ |
d67b0d97 EN |
35 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
36 | #define CONFIG_SYS_FSL_USDHC_NUM 2 | |
37 | ||
d67b0d97 EN |
38 | /* |
39 | * SATA Configs | |
40 | */ | |
41 | #ifdef CONFIG_CMD_SATA | |
d67b0d97 EN |
42 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
43 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
44 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
45 | #define CONFIG_LBA48 | |
d67b0d97 EN |
46 | #endif |
47 | ||
d67b0d97 | 48 | #define CONFIG_FEC_MXC |
d67b0d97 EN |
49 | #define IMX_FEC_BASE ENET_BASE_ADDR |
50 | #define CONFIG_FEC_XCV_TYPE RGMII | |
51 | #define CONFIG_ETHPRIME "FEC" | |
52 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
d67b0d97 EN |
53 | |
54 | /* USB Configs */ | |
d1a52860 TK |
55 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
56 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
d67b0d97 EN |
57 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
58 | #define CONFIG_MXC_USB_FLAGS 0 | |
59 | ||
d67b0d97 | 60 | /* Framebuffer and LCD */ |
d67b0d97 EN |
61 | #define CONFIG_VIDEO_BMP_RLE8 |
62 | #define CONFIG_SPLASH_SCREEN | |
761bc195 EN |
63 | #define CONFIG_SPLASH_SCREEN_ALIGN |
64 | #define CONFIG_VIDEO_BMP_GZIP | |
65 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) | |
d67b0d97 | 66 | #define CONFIG_BMP_16BPP |
5ea7f0e3 | 67 | #define CONFIG_IMX_HDMI |
a47e4495 | 68 | #define CONFIG_IMX_VIDEO_SKIP |
d67b0d97 | 69 | |
cc5d7dcb GG |
70 | #ifdef CONFIG_CMD_MMC |
71 | #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) | |
d67b0d97 | 72 | #else |
cc5d7dcb | 73 | #define DISTRO_BOOT_DEV_MMC(func) |
d67b0d97 EN |
74 | #endif |
75 | ||
cc5d7dcb GG |
76 | #ifdef CONFIG_CMD_SATA |
77 | #define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0) | |
d67b0d97 | 78 | #else |
cc5d7dcb | 79 | #define DISTRO_BOOT_DEV_SATA(func) |
d67b0d97 EN |
80 | #endif |
81 | ||
5b7103e0 | 82 | #ifdef CONFIG_USB_STORAGE |
cc5d7dcb | 83 | #define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0) |
5b7103e0 | 84 | #else |
cc5d7dcb GG |
85 | #define DISTRO_BOOT_DEV_USB(func) |
86 | #endif | |
87 | ||
88 | #ifdef CONFIG_CMD_PXE | |
89 | #define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na) | |
90 | #else | |
91 | #define DISTRO_BOOT_DEV_PXE(func) | |
92 | #endif | |
93 | ||
94 | #ifdef CONFIG_CMD_DHCP | |
95 | #define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na) | |
96 | #else | |
97 | #define DISTRO_BOOT_DEV_DHCP(func) | |
5b7103e0 DR |
98 | #endif |
99 | ||
d67b0d97 | 100 | |
f8b1e86d | 101 | #if defined(CONFIG_SABRELITE) |
cc5d7dcb GG |
102 | #define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" |
103 | #else | |
104 | /* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ | |
105 | #define FDTFILE | |
106 | #endif | |
107 | ||
108 | #define BOOT_TARGET_DEVICES(func) \ | |
109 | DISTRO_BOOT_DEV_MMC(func) \ | |
110 | DISTRO_BOOT_DEV_SATA(func) \ | |
111 | DISTRO_BOOT_DEV_USB(func) \ | |
112 | DISTRO_BOOT_DEV_PXE(func) \ | |
113 | DISTRO_BOOT_DEV_DHCP(func) | |
114 | ||
115 | #include <config_distro_bootcmd.h> | |
116 | ||
f8b1e86d | 117 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
f8b1e86d FE |
118 | "console=ttymxc1\0" \ |
119 | "fdt_high=0xffffffff\0" \ | |
120 | "initrd_high=0xffffffff\0" \ | |
cc5d7dcb GG |
121 | "fdt_addr_r=0x18000000\0" \ |
122 | FDTFILE \ | |
123 | "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ | |
124 | "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ | |
125 | "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ | |
126 | "ramdisk_addr_r=0x13000000\0" \ | |
127 | "ramdiskaddr=0x13000000\0" \ | |
f8b1e86d | 128 | "ip_dyn=yes\0" \ |
1c3e62d6 | 129 | "usb_pgood_delay=2000\0" \ |
cc5d7dcb | 130 | BOOTENV |
d67b0d97 EN |
131 | |
132 | /* Miscellaneous configurable options */ | |
d67b0d97 | 133 | |
d67b0d97 | 134 | /* Physical Memory Map */ |
d67b0d97 EN |
135 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
136 | ||
137 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
138 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
139 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
140 | ||
141 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
142 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
143 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
144 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
145 | ||
056845c2 | 146 | /* Environment organization */ |
d67b0d97 | 147 | |
d67b0d97 | 148 | #if defined(CONFIG_ENV_IS_IN_MMC) |
d67b0d97 | 149 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
d67b0d97 EN |
150 | #endif |
151 | ||
147f8fa3 MV |
152 | /* |
153 | * PCI express | |
154 | */ | |
147f8fa3 | 155 | #ifdef CONFIG_CMD_PCI |
147f8fa3 MV |
156 | #define CONFIG_PCI_SCAN_SHOW |
157 | #define CONFIG_PCIE_IMX | |
158 | #endif | |
159 | ||
d67b0d97 | 160 | #endif /* __CONFIG_H */ |