[J-u-boot.git] / drivers / i2c / lpc32xx_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * LPC32xx I2C interface driver
 *
 * (C) Copyright 2014-2015  DENX Software Engineering GmbH
 * Written-by: Albert ARIBAUD - 3ADEV <[email protected]>
 */

#include <config.h>
#include <log.h>
#include <asm/io.h>
#include <i2c.h>
#include <linux/errno.h>
#include <asm/arch/clk.h>
#include <asm/arch/i2c.h>
#include <dm.h>
#include <mapmem.h>

/*
 * Provide default speed and slave if target did not
 */

#if !defined(CFG_SYS_I2C_LPC32XX_SPEED)
#define CFG_SYS_I2C_LPC32XX_SPEED 350000
#endif

#if !defined(CFG_SYS_I2C_LPC32XX_SLAVE)
#define CFG_SYS_I2C_LPC32XX_SLAVE 0
#endif

/* TX register fields */
#define LPC32XX_I2C_TX_START		0x00000100
#define LPC32XX_I2C_TX_STOP		0x00000200

/* Control register values */
#define LPC32XX_I2C_SOFT_RESET		0x00000100

/* Status register values */
#define LPC32XX_I2C_STAT_TFF		0x00000400
#define LPC32XX_I2C_STAT_RFE		0x00000200
#define LPC32XX_I2C_STAT_NAI		0x00000004
#define LPC32XX_I2C_STAT_TDI		0x00000001

#if !CONFIG_IS_ENABLED(DM_I2C)
static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
	(struct lpc32xx_i2c_base *)I2C1_BASE,
	(struct lpc32xx_i2c_base *)I2C2_BASE,
	(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
#endif

/* Set I2C bus speed */
static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
					unsigned int speed, unsigned int chip)
{
	int half_period;

	if (speed == 0)
		return -EINVAL;

	/* OTG I2C clock source and CLK registers are different */
	if (chip == 2) {
		half_period = (get_periph_clk_rate() / speed) / 2;
		if (half_period > 0xFF)
			return -EINVAL;
	} else {
		half_period = (get_hclk_clk_rate() / speed) / 2;
		if (half_period > 0x3FF)
			return -EINVAL;
	}

	writel(half_period, &base->clk_hi);
	writel(half_period, &base->clk_lo);
	return 0;
}

/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void __i2c_init(struct lpc32xx_i2c_base *base,
		       int requested_speed, int slaveadd, unsigned int chip)
{
	/* soft reset (auto-clears) */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	/* set HI and LO periods for half of the default speed */
	__i2c_set_bus_speed(base, requested_speed, chip);
}

/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
{
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* Addre slave for write with start before and stop after */
	writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
	       &base->tx);
	/* wait for end of transation */
	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* was there no acknowledge? */
	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 */
static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
		      int alen, u8 *data, int length)
{
	int stat, wlen;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write an address at all? */
	if (alen) {
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
		/* write address bytes */
		while (alen--) {
			/* compute address byte + stop for the last one */
			int a = (addr >> (8 * alen)) & 0xff;
			if (!alen)
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &base->tx);
		}
		/* wait for end of transation */
		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &base->stat);
	}
	/* do we have to read data at all? */
	if (length) {
		/* Address slave in read mode */
		writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
		wlen = length;
		/* get data */
		while (length | wlen) {
			/* read status for TFF and RFE */
			stat = readl(&base->stat);
			/* must we, can we write a trigger byte? */
			if ((wlen > 0)
			   & (!(stat & LPC32XX_I2C_STAT_TFF))) {
				wlen--;
				/* write trigger byte + stop if last */
				writel(wlen ? 0 :
				LPC32XX_I2C_TX_STOP, &base->tx);
			}
			/* must we, can we read a data byte? */
			if ((length > 0)
			   & (!(stat & LPC32XX_I2C_STAT_RFE))) {
				length--;
				/* read byte */
				*(data++) = readl(&base->rx);
			}
		}
		/* wait for end of transation */
		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &base->stat);
	}
	/* success */
	return 0;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
		       int alen, u8 *data, int length)
{
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write anything at all? */
	if (alen | length)
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
	else
		return 0;
	/* write address bytes */
	while (alen) {
		/* wait for transmit fifo not full */
		stat = readl(&base->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			alen--;
			int a = (addr >> (8 * alen)) & 0xff;
			if (!(alen | length))
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &base->tx);
		}
	}
	while (length) {
		/* wait for transmit fifo not full */
		stat = readl(&base->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			/* compute data byte, add stop if length==0 */
			length--;
			int d = *(data++);
			if (!length)
				d |= LPC32XX_I2C_TX_STOP;
			/* Send data byte */
			writel(d, &base->tx);
		}
	}
	/* wait for end of transation */
	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* clear end-of-transaction flag */
	writel(1, &base->stat);
	return 0;
}

#if !CONFIG_IS_ENABLED(DM_I2C)
static void lpc32xx_i2c_init(struct i2c_adapter *adap,
			     int requested_speed, int slaveadd)
{
	__i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
		   adap->hwadapnr);
}

static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
{
	return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
}

static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
			    int alen, u8 *data, int length)
{
	return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
			 alen, data, length);
}

static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			     int alen, u8 *data, int length)
{
	return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
			  alen, data, length);
}

static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
					      unsigned int speed)
{
	return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
				  adap->hwadapnr);
}

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CFG_SYS_I2C_LPC32XX_SPEED,
			 CFG_SYS_I2C_LPC32XX_SLAVE,
			 0)

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CFG_SYS_I2C_LPC32XX_SPEED,
			 CFG_SYS_I2C_LPC32XX_SLAVE,
			 1)

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 100000,
			 0,
			 2)
#else /* CONFIG_DM_I2C */
static int lpc32xx_i2c_probe(struct udevice *bus)
{
	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);

	dev->base = dev_read_addr_ptr(bus);
	__i2c_init(dev->base, dev->speed, 0, dev->index);
	return 0;
}

static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
				  u32 chip_flags)
{
	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
	return __i2c_probe_chip(dev->base, chip_addr);
}

static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
		int nmsgs)
{
	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
	struct i2c_msg *dmsg, *omsg, dummy;
	uint i = 0, address = 0;

	memset(&dummy, 0, sizeof(struct i2c_msg));

	/* We expect either two messages (one with an offset and one with the
	 * actual data) or one message (just data)
	 */
	if (nmsgs > 2 || nmsgs == 0) {
		debug("%s: Only one or two messages are supported.", __func__);
		return -1;
	}

	omsg = nmsgs == 1 ? &dummy : msg;
	dmsg = nmsgs == 1 ? msg : msg + 1;

	/* the address is expected to be a uint, not a array. */
	address = omsg->buf[0];
	for (i = 1; i < omsg->len; i++)
		address = (address << 8) + omsg->buf[i];

	if (dmsg->flags & I2C_M_RD)
		return __i2c_read(dev->base, dmsg->addr, address,
				  omsg->len, dmsg->buf, dmsg->len);
	else
		return __i2c_write(dev->base, dmsg->addr, address,
				   omsg->len, dmsg->buf, dmsg->len);
}

static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
	return __i2c_set_bus_speed(dev->base, speed, dev->index);
}

static int lpc32xx_i2c_reset(struct udevice *bus)
{
	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);

	__i2c_init(dev->base, dev->speed, 0, dev->index);
	return 0;
}

static const struct dm_i2c_ops lpc32xx_i2c_ops = {
	.xfer          = lpc32xx_i2c_xfer,
	.probe_chip    = lpc32xx_i2c_probe_chip,
	.deblock       = lpc32xx_i2c_reset,
	.set_bus_speed = lpc32xx_i2c_set_bus_speed,
};

static const struct udevice_id lpc32xx_i2c_ids[] = {
	{ .compatible = "nxp,pnx-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_lpc32xx) = {
	.name                 = "i2c_lpc32xx",
	.id                   = UCLASS_I2C,
	.of_match             = lpc32xx_i2c_ids,
	.probe                = lpc32xx_i2c_probe,
	.ops                  = &lpc32xx_i2c_ops,
};
#endif /* CONFIG_DM_I2C */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5e862b95 AA	2	/*
	3	* LPC32xx I2C interface driver
	4	*
1933af15	5	* (C) Copyright 2014-2015 DENX Software Engineering GmbH
5e862b95	6	* Written-by: Albert ARIBAUD - 3ADEV <[email protected]>
5e862b95 AA	7	*/
5e862b95 AA	8
03de305e	9	#include <config.h>
f7ae49fc	10	#include <log.h>
5e862b95 AA	11	#include <asm/io.h>
5e862b95 AA	12	#include <i2c.h>
1221ce45	13	#include <linux/errno.h>
5e862b95	14	#include <asm/arch/clk.h>
fb057880	15	#include <asm/arch/i2c.h>
d61c7adb LB	16	#include <dm.h>
d61c7adb LB	17	#include <mapmem.h>
5e862b95 AA	18
	19	/*
	20	* Provide default speed and slave if target did not
	21	*/
	22
6e7df1d1 TR	23	#if !defined(CFG_SYS_I2C_LPC32XX_SPEED)
6e7df1d1 TR	24	#define CFG_SYS_I2C_LPC32XX_SPEED 350000
5e862b95 AA	25	#endif
5e862b95 AA	26
6e7df1d1 TR	27	#if !defined(CFG_SYS_I2C_LPC32XX_SLAVE)
6e7df1d1 TR	28	#define CFG_SYS_I2C_LPC32XX_SLAVE 0
5e862b95 AA	29	#endif
5e862b95 AA	30
5e862b95 AA	31	/* TX register fields */
	32	#define LPC32XX_I2C_TX_START 0x00000100
	33	#define LPC32XX_I2C_TX_STOP 0x00000200
	34
	35	/* Control register values */
	36	#define LPC32XX_I2C_SOFT_RESET 0x00000100
	37
	38	/* Status register values */
	39	#define LPC32XX_I2C_STAT_TFF 0x00000400
	40	#define LPC32XX_I2C_STAT_RFE 0x00000200
5e862b95 AA	41	#define LPC32XX_I2C_STAT_NAI 0x00000004
	42	#define LPC32XX_I2C_STAT_TDI 0x00000001
	43
2147a169	44	#if !CONFIG_IS_ENABLED(DM_I2C)
eddac8e9 LB	45	static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
	46	(struct lpc32xx_i2c_base *)I2C1_BASE,
	47	(struct lpc32xx_i2c_base *)I2C2_BASE,
	48	(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
5e862b95	49	};
d61c7adb	50	#endif
5e862b95 AA	51
5e862b95 AA	52	/* Set I2C bus speed */
eddac8e9 LB	53	static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
eddac8e9 LB	54	unsigned int speed, unsigned int chip)
5e862b95 AA	55	{
	56	int half_period;
	57
	58	if (speed == 0)
	59	return -EINVAL;
	60
ea16c6a1	61	/* OTG I2C clock source and CLK registers are different */
eddac8e9	62	if (chip == 2) {
ea16c6a1 VZ	63	half_period = (get_periph_clk_rate() / speed) / 2;
	64	if (half_period > 0xFF)
	65	return -EINVAL;
	66	} else {
	67	half_period = (get_hclk_clk_rate() / speed) / 2;
	68	if (half_period > 0x3FF)
	69	return -EINVAL;
	70	}
5e862b95	71
eddac8e9 LB	72	writel(half_period, &base->clk_hi);
eddac8e9 LB	73	writel(half_period, &base->clk_lo);
5e862b95 AA	74	return 0;
	75	}
	76
	77	/* I2C init called by cmd_i2c when doing 'i2c reset'. */
eddac8e9 LB	78	static void __i2c_init(struct lpc32xx_i2c_base *base,
eddac8e9 LB	79	int requested_speed, int slaveadd, unsigned int chip)
5e862b95	80	{
5e862b95	81	/* soft reset (auto-clears) */
eddac8e9	82	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
ea16c6a1	83	/* set HI and LO periods for half of the default speed */
eddac8e9	84	__i2c_set_bus_speed(base, requested_speed, chip);
5e862b95 AA	85	}
	86
	87	/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
eddac8e9	88	static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
5e862b95	89	{
5e862b95 AA	90	int stat;
	91
	92	/* Soft-reset the controller */
eddac8e9 LB	93	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	94	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	95	;
	96	/* Addre slave for write with start before and stop after */
	97	writel((dev<<1) \| LPC32XX_I2C_TX_START \| LPC32XX_I2C_TX_STOP,
eddac8e9	98	&base->tx);
5e862b95	99	/* wait for end of transation */
eddac8e9	100	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	101	;
	102	/* was there no acknowledge? */
	103	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
	104	}
	105
	106	/*
	107	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	108	* Begin write, send address byte(s), begin read, receive data bytes, end.
	109	*/
eddac8e9 LB	110	static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
eddac8e9 LB	111	int alen, u8 *data, int length)
5e862b95	112	{
5e862b95 AA	113	int stat, wlen;
	114
	115	/* Soft-reset the controller */
eddac8e9 LB	116	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	117	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	118	;
	119	/* do we need to write an address at all? */
	120	if (alen) {
	121	/* Address slave in write mode */
eddac8e9	122	writel((dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
5e862b95 AA	123	/* write address bytes */
	124	while (alen--) {
	125	/* compute address byte + stop for the last one */
	126	int a = (addr >> (8 * alen)) & 0xff;
	127	if (!alen)
	128	a \|= LPC32XX_I2C_TX_STOP;
	129	/* Send address byte */
eddac8e9	130	writel(a, &base->tx);
5e862b95 AA	131	}
5e862b95 AA	132	/* wait for end of transation */
eddac8e9	133	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	134	;
5e862b95 AA	135	/* clear end-of-transaction flag */
eddac8e9	136	writel(1, &base->stat);
5e862b95 AA	137	}
	138	/* do we have to read data at all? */
	139	if (length) {
	140	/* Address slave in read mode */
eddac8e9	141	writel(1 \| (dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
5e862b95 AA	142	wlen = length;
	143	/* get data */
	144	while (length \| wlen) {
	145	/* read status for TFF and RFE */
eddac8e9	146	stat = readl(&base->stat);
5e862b95 AA	147	/* must we, can we write a trigger byte? */
	148	if ((wlen > 0)
	149	& (!(stat & LPC32XX_I2C_STAT_TFF))) {
	150	wlen--;
	151	/* write trigger byte + stop if last */
	152	writel(wlen ? 0 :
eddac8e9	153	LPC32XX_I2C_TX_STOP, &base->tx);
5e862b95 AA	154	}
	155	/* must we, can we read a data byte? */
	156	if ((length > 0)
	157	& (!(stat & LPC32XX_I2C_STAT_RFE))) {
	158	length--;
	159	/* read byte */
eddac8e9	160	*(data++) = readl(&base->rx);
5e862b95 AA	161	}
5e862b95 AA	162	}
3d2b6a2e	163	/* wait for end of transation */
eddac8e9	164	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
3d2b6a2e SL	165	;
3d2b6a2e SL	166	/* clear end-of-transaction flag */
eddac8e9	167	writel(1, &base->stat);
5e862b95	168	}
5e862b95 AA	169	/* success */
	170	return 0;
	171	}
	172
	173	/*
	174	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	175	* Begin write, send address byte(s), send data bytes, end.
	176	*/
eddac8e9 LB	177	static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
eddac8e9 LB	178	int alen, u8 *data, int length)
5e862b95	179	{
5e862b95 AA	180	int stat;
	181
	182	/* Soft-reset the controller */
eddac8e9 LB	183	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	184	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	185	;
	186	/* do we need to write anything at all? */
	187	if (alen \| length)
	188	/* Address slave in write mode */
eddac8e9	189	writel((dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
58243001 SL	190	else
58243001 SL	191	return 0;
5e862b95 AA	192	/* write address bytes */
	193	while (alen) {
	194	/* wait for transmit fifo not full */
eddac8e9	195	stat = readl(&base->stat);
5e862b95 AA	196	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	197	alen--;
	198	int a = (addr >> (8 * alen)) & 0xff;
	199	if (!(alen \| length))
	200	a \|= LPC32XX_I2C_TX_STOP;
	201	/* Send address byte */
eddac8e9	202	writel(a, &base->tx);
5e862b95 AA	203	}
	204	}
	205	while (length) {
	206	/* wait for transmit fifo not full */
eddac8e9	207	stat = readl(&base->stat);
5e862b95 AA	208	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	209	/* compute data byte, add stop if length==0 */
	210	length--;
	211	int d = *(data++);
	212	if (!length)
	213	d \|= LPC32XX_I2C_TX_STOP;
	214	/* Send data byte */
eddac8e9	215	writel(d, &base->tx);
5e862b95 AA	216	}
	217	}
	218	/* wait for end of transation */
eddac8e9	219	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	220	;
5e862b95 AA	221	/* clear end-of-transaction flag */
eddac8e9	222	writel(1, &base->stat);
5e862b95 AA	223	return 0;
	224	}
	225
2147a169	226	#if !CONFIG_IS_ENABLED(DM_I2C)
552531e4 LB	227	static void lpc32xx_i2c_init(struct i2c_adapter *adap,
	228	int requested_speed, int slaveadd)
	229	{
eddac8e9 LB	230	__i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
eddac8e9 LB	231	adap->hwadapnr);
552531e4 LB	232	}
	233
	234	static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
	235	{
eddac8e9	236	return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
552531e4 LB	237	}
	238
	239	static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	240	int alen, u8 *data, int length)
	241	{
eddac8e9 LB	242	return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
eddac8e9 LB	243	alen, data, length);
552531e4 LB	244	}
	245
	246	static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	247	int alen, u8 *data, int length)
	248	{
eddac8e9 LB	249	return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
eddac8e9 LB	250	alen, data, length);
552531e4 LB	251	}
	252
	253	static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
	254	unsigned int speed)
	255	{
eddac8e9 LB	256	return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
eddac8e9 LB	257	adap->hwadapnr);
552531e4 LB	258	}
	259
	260	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
5e862b95 AA	261	lpc32xx_i2c_read, lpc32xx_i2c_write,
5e862b95 AA	262	lpc32xx_i2c_set_bus_speed,
6e7df1d1 TR	263	CFG_SYS_I2C_LPC32XX_SPEED,
6e7df1d1 TR	264	CFG_SYS_I2C_LPC32XX_SLAVE,
5e862b95 AA	265	0)
5e862b95 AA	266
552531e4	267	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
5e862b95 AA	268	lpc32xx_i2c_read, lpc32xx_i2c_write,
5e862b95 AA	269	lpc32xx_i2c_set_bus_speed,
6e7df1d1 TR	270	CFG_SYS_I2C_LPC32XX_SPEED,
6e7df1d1 TR	271	CFG_SYS_I2C_LPC32XX_SLAVE,
5e862b95	272	1)
1933af15	273
552531e4	274	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
1933af15 SL	275	lpc32xx_i2c_read, lpc32xx_i2c_write,
	276	lpc32xx_i2c_set_bus_speed,
	277	100000,
	278	0,
	279	2)
d61c7adb LB	280	#else /* CONFIG_DM_I2C */
	281	static int lpc32xx_i2c_probe(struct udevice *bus)
	282	{
c69cda25	283	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
8b85dfc6	284
3f70acdb	285	dev->base = dev_read_addr_ptr(bus);
d61c7adb LB	286	__i2c_init(dev->base, dev->speed, 0, dev->index);
	287	return 0;
	288	}
	289
	290	static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
	291	u32 chip_flags)
	292	{
c69cda25	293	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
d61c7adb LB	294	return __i2c_probe_chip(dev->base, chip_addr);
	295	}
	296
	297	static int lpc32xx_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	298	int nmsgs)
	299	{
c69cda25	300	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
d61c7adb LB	301	struct i2c_msg dmsg, omsg, dummy;
	302	uint i = 0, address = 0;
	303
	304	memset(&dummy, 0, sizeof(struct i2c_msg));
	305
	306	/* We expect either two messages (one with an offset and one with the
	307	* actual data) or one message (just data)
	308	*/
	309	if (nmsgs > 2 \|\| nmsgs == 0) {
	310	debug("%s: Only one or two messages are supported.", __func__);
	311	return -1;
	312	}
	313
	314	omsg = nmsgs == 1 ? &dummy : msg;
	315	dmsg = nmsgs == 1 ? msg : msg + 1;
	316
	317	/* the address is expected to be a uint, not a array. */
	318	address = omsg->buf[0];
	319	for (i = 1; i < omsg->len; i++)
	320	address = (address << 8) + omsg->buf[i];
	321
	322	if (dmsg->flags & I2C_M_RD)
	323	return __i2c_read(dev->base, dmsg->addr, address,
	324	omsg->len, dmsg->buf, dmsg->len);
	325	else
	326	return __i2c_write(dev->base, dmsg->addr, address,
	327	omsg->len, dmsg->buf, dmsg->len);
	328	}
	329
	330	static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	331	{
c69cda25	332	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
d61c7adb LB	333	return __i2c_set_bus_speed(dev->base, speed, dev->index);
	334	}
	335
	336	static int lpc32xx_i2c_reset(struct udevice *bus)
	337	{
c69cda25	338	struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
d61c7adb LB	339
	340	__i2c_init(dev->base, dev->speed, 0, dev->index);
	341	return 0;
	342	}
	343
	344	static const struct dm_i2c_ops lpc32xx_i2c_ops = {
	345	.xfer = lpc32xx_i2c_xfer,
	346	.probe_chip = lpc32xx_i2c_probe_chip,
	347	.deblock = lpc32xx_i2c_reset,
	348	.set_bus_speed = lpc32xx_i2c_set_bus_speed,
	349	};
	350
103f233e TW	351	static const struct udevice_id lpc32xx_i2c_ids[] = {
	352	{ .compatible = "nxp,pnx-i2c" },
	353	{ }
	354	};
	355
d61c7adb	356	U_BOOT_DRIVER(i2c_lpc32xx) = {
d61c7adb	357	.name = "i2c_lpc32xx",
103f233e TW	358	.id = UCLASS_I2C,
103f233e TW	359	.of_match = lpc32xx_i2c_ids,
d61c7adb LB	360	.probe = lpc32xx_i2c_probe,
	361	.ops = &lpc32xx_i2c_ops,
	362	};
	363	#endif /* CONFIG_DM_I2C */