[J-u-boot.git] / drivers / i2c / lpc32xx_i2c.c

/*
 * LPC32xx I2C interface driver
 *
 * (C) Copyright 2014  DENX Software Engineering GmbH
 * Written-by: Albert ARIBAUD - 3ADEV <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <asm/errno.h>
#include <asm/arch/clk.h>

/*
 * Provide default speed and slave if target did not
 */

#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
#endif

#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
#endif

/* i2c register set */
struct lpc32xx_i2c_registers {
	union {
		u32 rx;
		u32 tx;
	};
	u32 stat;
	u32 ctrl;
	u32 clk_hi;
	u32 clk_lo;
	u32 adr;
	u32 rxfl;
	u32 txfl;
	u32 rxb;
	u32 txb;
	u32 stx;
	u32 stxfl;
};

/* TX register fields */
#define LPC32XX_I2C_TX_START		0x00000100
#define LPC32XX_I2C_TX_STOP		0x00000200

/* Control register values */
#define LPC32XX_I2C_SOFT_RESET		0x00000100

/* Status register values */
#define LPC32XX_I2C_STAT_TFF		0x00000400
#define LPC32XX_I2C_STAT_RFE		0x00000200
#define LPC32XX_I2C_STAT_DRMI		0x00000008
#define LPC32XX_I2C_STAT_NAI		0x00000004
#define LPC32XX_I2C_STAT_TDI		0x00000001

static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
	(struct lpc32xx_i2c_registers *)I2C1_BASE,
	(struct lpc32xx_i2c_registers *)I2C2_BASE
};

/* Set I2C bus speed */
static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	int half_period;

	if (speed == 0)
		return -EINVAL;

	half_period = (get_hclk_clk_rate() / speed) / 2;

	if ((half_period > 255) || (half_period < 0))
		return -EINVAL;

	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
	return 0;
}

/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void _i2c_init(struct i2c_adapter *adap,
	int requested_speed, int slaveadd)
{
	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];

	/* soft reset (auto-clears) */
	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	/* set HI and LO periods for about 350 kHz */
	lpc32xx_i2c_set_bus_speed(adap, requested_speed);
}

/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* Addre slave for write with start before and stop after */
	writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
	       &i2c->tx);
	/* wait for end of transation */
	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* was there no acknowledge? */
	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 */
static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
			 int alen, u8 *data, int length)
{
	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	int stat, wlen;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write an address at all? */
	if (alen) {
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
		/* write address bytes */
		while (alen--) {
			/* compute address byte + stop for the last one */
			int a = (addr >> (8 * alen)) & 0xff;
			if (!alen)
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &i2c->tx);
		}
		/* wait for end of transation */
		while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &i2c->stat);
	}
	/* do we have to read data at all? */
	if (length) {
		/* Address slave in read mode */
		writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
		wlen = length;
		/* get data */
		while (length | wlen) {
			/* read status for TFF and RFE */
			stat = readl(&i2c->stat);
			/* must we, can we write a trigger byte? */
			if ((wlen > 0)
			   & (!(stat & LPC32XX_I2C_STAT_TFF))) {
				wlen--;
				/* write trigger byte + stop if last */
				writel(wlen ? 0 :
				LPC32XX_I2C_TX_STOP, &i2c->tx);
			}
			/* must we, can we read a data byte? */
			if ((length > 0)
			   & (!(stat & LPC32XX_I2C_STAT_RFE))) {
				length--;
				/* read byte */
				*(data++) = readl(&i2c->rx);
			}
		}
		/* wait for end of transation */
		while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &i2c->stat);
	}
	/* success */
	return 0;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			  int alen, u8 *data, int length)
{
	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write anything at all? */
	if (alen | length)
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
	else
		return 0;
	/* write address bytes */
	while (alen) {
		/* wait for transmit fifo not full */
		stat = readl(&i2c->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			alen--;
			int a = (addr >> (8 * alen)) & 0xff;
			if (!(alen | length))
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &i2c->tx);
		}
	}
	while (length) {
		/* wait for transmit fifo not full */
		stat = readl(&i2c->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			/* compute data byte, add stop if length==0 */
			length--;
			int d = *(data++);
			if (!length)
				d |= LPC32XX_I2C_TX_STOP;
			/* Send data byte */
			writel(d, &i2c->tx);
		}
	}
	/* wait for end of transation */
	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* clear end-of-transaction flag */
	writel(1, &i2c->stat);
	return 0;
}

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_LPC32XX_SPEED,
			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
			 0)

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_LPC32XX_SPEED,
			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
			 1)
Commit	Line	Data
5e862b95 AA	1	/*
	2	* LPC32xx I2C interface driver
	3	*
	4	* (C) Copyright 2014 DENX Software Engineering GmbH
	5	* Written-by: Albert ARIBAUD - 3ADEV <[email protected]>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <asm/io.h>
	12	#include <i2c.h>
	13	#include <asm/errno.h>
	14	#include <asm/arch/clk.h>
	15
	16	/*
	17	* Provide default speed and slave if target did not
	18	*/
	19
	20	#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
	21	#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
	22	#endif
	23
	24	#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
	25	#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
	26	#endif
	27
	28	/* i2c register set */
	29	struct lpc32xx_i2c_registers {
	30	union {
	31	u32 rx;
	32	u32 tx;
	33	};
	34	u32 stat;
	35	u32 ctrl;
	36	u32 clk_hi;
	37	u32 clk_lo;
	38	u32 adr;
	39	u32 rxfl;
	40	u32 txfl;
	41	u32 rxb;
	42	u32 txb;
	43	u32 stx;
	44	u32 stxfl;
	45	};
	46
	47	/* TX register fields */
	48	#define LPC32XX_I2C_TX_START 0x00000100
	49	#define LPC32XX_I2C_TX_STOP 0x00000200
	50
	51	/* Control register values */
	52	#define LPC32XX_I2C_SOFT_RESET 0x00000100
	53
	54	/* Status register values */
	55	#define LPC32XX_I2C_STAT_TFF 0x00000400
	56	#define LPC32XX_I2C_STAT_RFE 0x00000200
	57	#define LPC32XX_I2C_STAT_DRMI 0x00000008
	58	#define LPC32XX_I2C_STAT_NAI 0x00000004
	59	#define LPC32XX_I2C_STAT_TDI 0x00000001
	60
	61	static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
	62	(struct lpc32xx_i2c_registers *)I2C1_BASE,
	63	(struct lpc32xx_i2c_registers *)I2C2_BASE
	64	};
65
66	/* Set I2C bus speed */
67	static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
68	unsigned int speed)
69	{
70	int half_period;
71
72	if (speed == 0)
73	return -EINVAL;
74
b395a996	75	half_period = (get_hclk_clk_rate() / speed) / 2;
5e862b95 AA	76
	77	if ((half_period > 255) \|\| (half_period < 0))
	78	return -EINVAL;
	79
	80	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
	81	writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
	82	return 0;
	83	}
	84
	85	/* I2C init called by cmd_i2c when doing 'i2c reset'. */
	86	static void _i2c_init(struct i2c_adapter *adap,
	87	int requested_speed, int slaveadd)
	88	{
	89	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	90
	91	/* soft reset (auto-clears) */
	92	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	93	/* set HI and LO periods for about 350 kHz */
	94	lpc32xx_i2c_set_bus_speed(adap, requested_speed);
	95	}
	96
	97	/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
	98	static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
	99	{
	100	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	101	int stat;
	102
	103	/* Soft-reset the controller */
	104	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	105	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
	106	;
	107	/* Addre slave for write with start before and stop after */
	108	writel((dev<<1) \| LPC32XX_I2C_TX_START \| LPC32XX_I2C_TX_STOP,
	109	&i2c->tx);
	110	/* wait for end of transation */
	111	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
	112	;
	113	/* was there no acknowledge? */
	114	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
	115	}
	116
	117	/*
	118	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	119	* Begin write, send address byte(s), begin read, receive data bytes, end.
	120	*/
	121	static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	122	int alen, u8 *data, int length)
	123	{
	124	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	125	int stat, wlen;
	126
	127	/* Soft-reset the controller */
	128	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	129	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
	130	;
	131	/* do we need to write an address at all? */
	132	if (alen) {
	133	/* Address slave in write mode */
	134	writel((dev<<1) \| LPC32XX_I2C_TX_START, &i2c->tx);
	135	/* write address bytes */
	136	while (alen--) {
	137	/* compute address byte + stop for the last one */
	138	int a = (addr >> (8 * alen)) & 0xff;
	139	if (!alen)
140	a \|= LPC32XX_I2C_TX_STOP;
141	/* Send address byte */
142	writel(a, &i2c->tx);
143	}
144	/* wait for end of transation */
145	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
146	;
147	/* clear end-of-transaction flag */
148	writel(1, &i2c->stat);
149	}
150	/* do we have to read data at all? */
151	if (length) {
152	/* Address slave in read mode */
153	writel(1 \| (dev<<1) \| LPC32XX_I2C_TX_START, &i2c->tx);
154	wlen = length;
155	/* get data */
156	while (length \| wlen) {
157	/* read status for TFF and RFE */
158	stat = readl(&i2c->stat);
159	/* must we, can we write a trigger byte? */
160	if ((wlen > 0)
161	& (!(stat & LPC32XX_I2C_STAT_TFF))) {
162	wlen--;
163	/* write trigger byte + stop if last */
164	writel(wlen ? 0 :
165	LPC32XX_I2C_TX_STOP, &i2c->tx);
166	}
167	/* must we, can we read a data byte? */
168	if ((length > 0)
169	& (!(stat & LPC32XX_I2C_STAT_RFE))) {
170	length--;
171	/* read byte */
172	*(data++) = readl(&i2c->rx);
173	}
174	}
3d2b6a2e SL	175	/* wait for end of transation */
	176	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
	177	;
	178	/* clear end-of-transaction flag */
	179	writel(1, &i2c->stat);
5e862b95	180	}
5e862b95 AA	181	/* success */
	182	return 0;
	183	}
	184
	185	/*
	186	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	187	* Begin write, send address byte(s), send data bytes, end.
	188	*/
	189	static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	190	int alen, u8 *data, int length)
	191	{
	192	struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
	193	int stat;
	194
	195	/* Soft-reset the controller */
	196	writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
	197	while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
	198	;
	199	/* do we need to write anything at all? */
	200	if (alen \| length)
	201	/* Address slave in write mode */
	202	writel((dev<<1) \| LPC32XX_I2C_TX_START, &i2c->tx);
58243001 SL	203	else
58243001 SL	204	return 0;
5e862b95 AA	205	/* write address bytes */
	206	while (alen) {
	207	/* wait for transmit fifo not full */
	208	stat = readl(&i2c->stat);
	209	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	210	alen--;
	211	int a = (addr >> (8 * alen)) & 0xff;
	212	if (!(alen \| length))
	213	a \|= LPC32XX_I2C_TX_STOP;
	214	/* Send address byte */
	215	writel(a, &i2c->tx);
	216	}
	217	}
	218	while (length) {
	219	/* wait for transmit fifo not full */
	220	stat = readl(&i2c->stat);
	221	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	222	/* compute data byte, add stop if length==0 */
	223	length--;
	224	int d = *(data++);
	225	if (!length)
	226	d \|= LPC32XX_I2C_TX_STOP;
	227	/* Send data byte */
	228	writel(d, &i2c->tx);
	229	}
	230	}
	231	/* wait for end of transation */
	232	while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
	233	;
	234	/* clear end-of-transaction flag */
	235	writel(1, &i2c->stat);
	236	return 0;
	237	}
	238
	239	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
	240	lpc32xx_i2c_read, lpc32xx_i2c_write,
	241	lpc32xx_i2c_set_bus_speed,
	242	CONFIG_SYS_I2C_LPC32XX_SPEED,
	243	CONFIG_SYS_I2C_LPC32XX_SLAVE,
	244	0)
	245
	246	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
	247	lpc32xx_i2c_read, lpc32xx_i2c_write,
	248	lpc32xx_i2c_set_bus_speed,
	249	CONFIG_SYS_I2C_LPC32XX_SPEED,
	250	CONFIG_SYS_I2C_LPC32XX_SLAVE,
	251	1)