projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 53ab4af3 HG |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <[email protected]> | |
| 4 | * | |
| 5 | * This file is dual-licensed: you can use it either under the terms | |
| 6 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 7 | * licensing only applies to this file, and not this project as a | |
| 8 | * whole. | |
| 9 | * | |
| 10 | * a) This library is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of the | |
| 13 | * License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This library is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public | |
| 21 | * License along with this library; if not, write to the Free | |
| 22 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
| 23 | * MA 02110-1301 USA | |
| 24 | * | |
| 25 | * Or, alternatively, | |
| 26 | * | |
| 27 | * b) Permission is hereby granted, free of charge, to any person | |
| 28 | * obtaining a copy of this software and associated documentation | |
| 29 | * files (the "Software"), to deal in the Software without | |
| 30 | * restriction, including without limitation the rights to use, | |
| 31 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 32 | * sell copies of the Software, and to permit persons to whom the | |
| 33 | * Software is furnished to do so, subject to the following | |
| 34 | * conditions: | |
| 35 | * | |
| 36 | * The above copyright notice and this permission notice shall be | |
| 37 | * included in all copies or substantial portions of the Software. | |
| 38 | * | |
| 39 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 46 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 47 | */ | |
| 48 | ||
| 49 | #include "skeleton.dtsi" | |
| 50 | ||
| 51 | #include <dt-bindings/thermal/thermal.h> | |
| 52 | ||
| 53 | #include <dt-bindings/dma/sun4i-a10.h> | |
| 54 | #include <dt-bindings/pinctrl/sun4i-a10.h> | |
| 55 | ||
| 56 | / { | |
| 57 | interrupt-parent = <&intc>; | |
| 58 | ||
| 59 | aliases { | |
| 60 | ethernet0 = &emac; | |
| 61 | }; | |
| 62 | ||
| 63 | chosen { | |
| 64 | #address-cells = <1>; | |
| 65 | #size-cells = <1>; | |
| 66 | ranges; | |
| 67 | ||
| 68 | framebuffer@0 { | |
| 69 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
| 70 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
| 71 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
| 72 | <&ahb_gates 44>; | |
| 73 | status = "disabled"; | |
| 74 | }; | |
| 75 | ||
| 76 | framebuffer@1 { | |
| 77 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
| 78 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; | |
| 79 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
| 80 | <&ahb_gates 44>, <&ahb_gates 46>; | |
| 81 | status = "disabled"; | |
| 82 | }; | |
| 83 | ||
| 84 | framebuffer@2 { | |
| 85 | compatible = "allwinner,simple-framebuffer", | |
| 86 | "simple-framebuffer"; | |
| 87 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
| 88 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
| 89 | <&ahb_gates 46>; | |
| 90 | status = "disabled"; | |
| 91 | }; | |
| 92 | ||
| 93 | framebuffer@3 { | |
| 94 | compatible = "allwinner,simple-framebuffer", | |
| 95 | "simple-framebuffer"; | |
| 96 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
| 97 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
| 98 | <&ahb_gates 44>, <&ahb_gates 46>; | |
| 99 | status = "disabled"; | |
| 100 | }; | |
| 101 | }; | |
| 102 | ||
| 103 | cpus { | |
| 104 | #address-cells = <1>; | |
| 105 | #size-cells = <0>; | |
| 106 | cpu0: cpu@0 { | |
| 107 | device_type = "cpu"; | |
| 108 | compatible = "arm,cortex-a8"; | |
| 109 | reg = <0x0>; | |
| 110 | clocks = <&cpu>; | |
| 111 | clock-latency = <244144>; /* 8 32k periods */ | |
| 112 | operating-points = < | |
| 113 | /* kHz uV */ | |
| 114 | 1008000 1400000 | |
| 115 | 912000 1350000 | |
| 116 | 864000 1300000 | |
| 117 | 624000 1250000 | |
| 118 | >; | |
| 119 | #cooling-cells = <2>; | |
| 120 | cooling-min-level = <0>; | |
| 121 | cooling-max-level = <3>; | |
| 122 | }; | |
| 123 | }; | |
| 124 | ||
| 125 | thermal-zones { | |
| 126 | cpu_thermal { | |
| 127 | /* milliseconds */ | |
| 128 | polling-delay-passive = <250>; | |
| 129 | polling-delay = <1000>; | |
| 130 | thermal-sensors = <&rtp>; | |
| 131 | ||
| 132 | cooling-maps { | |
| 133 | map0 { | |
| 134 | trip = <&cpu_alert0>; | |
| 135 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 136 | }; | |
| 137 | }; | |
| 138 | ||
| 139 | trips { | |
| 140 | cpu_alert0: cpu_alert0 { | |
| 141 | /* milliCelsius */ | |
| 142 | temperature = <850000>; | |
| 143 | hysteresis = <2000>; | |
| 144 | type = "passive"; | |
| 145 | }; | |
| 146 | ||
| 147 | cpu_crit: cpu_crit { | |
| 148 | /* milliCelsius */ | |
| 149 | temperature = <100000>; | |
| 150 | hysteresis = <2000>; | |
| 151 | type = "critical"; | |
| 152 | }; | |
| 153 | }; | |
| 154 | }; | |
| 155 | }; | |
| 156 | ||
| 157 | memory { | |
| 158 | reg = <0x40000000 0x80000000>; | |
| 159 | }; | |
| 160 | ||
| 161 | clocks { | |
| 162 | #address-cells = <1>; | |
| 163 | #size-cells = <1>; | |
| 164 | ranges; | |
| 165 | ||
| 166 | /* | |
| 167 | * This is a dummy clock, to be used as placeholder on | |
| 168 | * other mux clocks when a specific parent clock is not | |
| 169 | * yet implemented. It should be dropped when the driver | |
| 170 | * is complete. | |
| 171 | */ | |
| 172 | dummy: dummy { | |
| 173 | #clock-cells = <0>; | |
| 174 | compatible = "fixed-clock"; | |
| 175 | clock-frequency = <0>; | |
| 176 | }; | |
| 177 | ||
| 178 | osc24M: clk@01c20050 { | |
| 179 | #clock-cells = <0>; | |
| 180 | compatible = "allwinner,sun4i-a10-osc-clk"; | |
| 181 | reg = <0x01c20050 0x4>; | |
| 182 | clock-frequency = <24000000>; | |
| 183 | clock-output-names = "osc24M"; | |
| 184 | }; | |
| 185 | ||
| 186 | osc32k: clk@0 { | |
| 187 | #clock-cells = <0>; | |
| 188 | compatible = "fixed-clock"; | |
| 189 | clock-frequency = <32768>; | |
| 190 | clock-output-names = "osc32k"; | |
| 191 | }; | |
| 192 | ||
| 193 | pll1: clk@01c20000 { | |
| 194 | #clock-cells = <0>; | |
| 195 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
| 196 | reg = <0x01c20000 0x4>; | |
| 197 | clocks = <&osc24M>; | |
| 198 | clock-output-names = "pll1"; | |
| 199 | }; | |
| 200 | ||
| 201 | pll4: clk@01c20018 { | |
| 202 | #clock-cells = <0>; | |
| 203 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
| 204 | reg = <0x01c20018 0x4>; | |
| 205 | clocks = <&osc24M>; | |
| 206 | clock-output-names = "pll4"; | |
| 207 | }; | |
| 208 | ||
| 209 | pll5: clk@01c20020 { | |
| 210 | #clock-cells = <1>; | |
| 211 | compatible = "allwinner,sun4i-a10-pll5-clk"; | |
| 212 | reg = <0x01c20020 0x4>; | |
| 213 | clocks = <&osc24M>; | |
| 214 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 215 | }; | |
| 216 | ||
| 217 | pll6: clk@01c20028 { | |
| 218 | #clock-cells = <1>; | |
| 219 | compatible = "allwinner,sun4i-a10-pll6-clk"; | |
| 220 | reg = <0x01c20028 0x4>; | |
| 221 | clocks = <&osc24M>; | |
| 222 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 223 | }; | |
| 224 | ||
| 225 | /* dummy is 200M */ | |
| 226 | cpu: cpu@01c20054 { | |
| 227 | #clock-cells = <0>; | |
| 228 | compatible = "allwinner,sun4i-a10-cpu-clk"; | |
| 229 | reg = <0x01c20054 0x4>; | |
| 230 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 231 | clock-output-names = "cpu"; | |
| 232 | }; | |
| 233 | ||
| 234 | axi: axi@01c20054 { | |
| 235 | #clock-cells = <0>; | |
| 236 | compatible = "allwinner,sun4i-a10-axi-clk"; | |
| 237 | reg = <0x01c20054 0x4>; | |
| 238 | clocks = <&cpu>; | |
| 239 | clock-output-names = "axi"; | |
| 240 | }; | |
| 241 | ||
| 242 | axi_gates: clk@01c2005c { | |
| 243 | #clock-cells = <1>; | |
| 244 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; | |
| 245 | reg = <0x01c2005c 0x4>; | |
| 246 | clocks = <&axi>; | |
| 247 | clock-output-names = "axi_dram"; | |
| 248 | }; | |
| 249 | ||
| 250 | ahb: ahb@01c20054 { | |
| 251 | #clock-cells = <0>; | |
| 252 | compatible = "allwinner,sun4i-a10-ahb-clk"; | |
| 253 | reg = <0x01c20054 0x4>; | |
| 254 | clocks = <&axi>; | |
| 255 | clock-output-names = "ahb"; | |
| 256 | }; | |
| 257 | ||
| 258 | ahb_gates: clk@01c20060 { | |
| 259 | #clock-cells = <1>; | |
| 260 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; | |
| 261 | reg = <0x01c20060 0x8>; | |
| 262 | clocks = <&ahb>; | |
| 263 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 264 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
| 265 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 266 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
| 267 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
| 268 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
| 269 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
| 270 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
| 271 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
| 272 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 273 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
| 274 | }; | |
| 275 | ||
| 276 | apb0: apb0@01c20054 { | |
| 277 | #clock-cells = <0>; | |
| 278 | compatible = "allwinner,sun4i-a10-apb0-clk"; | |
| 279 | reg = <0x01c20054 0x4>; | |
| 280 | clocks = <&ahb>; | |
| 281 | clock-output-names = "apb0"; | |
| 282 | }; | |
| 283 | ||
| 284 | apb0_gates: clk@01c20068 { | |
| 285 | #clock-cells = <1>; | |
| 286 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; | |
| 287 | reg = <0x01c20068 0x4>; | |
| 288 | clocks = <&apb0>; | |
| 289 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 290 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
| 291 | "apb0_ir1", "apb0_keypad"; | |
| 292 | }; | |
| 293 | ||
| 294 | apb1: clk@01c20058 { | |
| 295 | #clock-cells = <0>; | |
| 296 | compatible = "allwinner,sun4i-a10-apb1-clk"; | |
| 297 | reg = <0x01c20058 0x4>; | |
| 298 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | |
| 299 | clock-output-names = "apb1"; | |
| 300 | }; | |
| 301 | ||
| 302 | apb1_gates: clk@01c2006c { | |
| 303 | #clock-cells = <1>; | |
| 304 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; | |
| 305 | reg = <0x01c2006c 0x4>; | |
| 306 | clocks = <&apb1>; | |
| 307 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 308 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
| 309 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
| 310 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
| 311 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
| 312 | "apb1_uart7"; | |
| 313 | }; | |
| 314 | ||
| 315 | nand_clk: clk@01c20080 { | |
| 316 | #clock-cells = <0>; | |
| 317 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 318 | reg = <0x01c20080 0x4>; | |
| 319 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 320 | clock-output-names = "nand"; | |
| 321 | }; | |
| 322 | ||
| 323 | ms_clk: clk@01c20084 { | |
| 324 | #clock-cells = <0>; | |
| 325 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 326 | reg = <0x01c20084 0x4>; | |
| 327 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 328 | clock-output-names = "ms"; | |
| 329 | }; | |
| 330 | ||
| 331 | mmc0_clk: clk@01c20088 { | |
| 332 | #clock-cells = <1>; | |
| 333 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 334 | reg = <0x01c20088 0x4>; | |
| 335 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 336 | clock-output-names = "mmc0", | |
| 337 | "mmc0_output", | |
| 338 | "mmc0_sample"; | |
| 339 | }; | |
| 340 | ||
| 341 | mmc1_clk: clk@01c2008c { | |
| 342 | #clock-cells = <1>; | |
| 343 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 344 | reg = <0x01c2008c 0x4>; | |
| 345 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 346 | clock-output-names = "mmc1", | |
| 347 | "mmc1_output", | |
| 348 | "mmc1_sample"; | |
| 349 | }; | |
| 350 | ||
| 351 | mmc2_clk: clk@01c20090 { | |
| 352 | #clock-cells = <1>; | |
| 353 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 354 | reg = <0x01c20090 0x4>; | |
| 355 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 356 | clock-output-names = "mmc2", | |
| 357 | "mmc2_output", | |
| 358 | "mmc2_sample"; | |
| 359 | }; | |
| 360 | ||
| 361 | mmc3_clk: clk@01c20094 { | |
| 362 | #clock-cells = <1>; | |
| 363 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 364 | reg = <0x01c20094 0x4>; | |
| 365 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 366 | clock-output-names = "mmc3", | |
| 367 | "mmc3_output", | |
| 368 | "mmc3_sample"; | |
| 369 | }; | |
| 370 | ||
| 371 | ts_clk: clk@01c20098 { | |
| 372 | #clock-cells = <0>; | |
| 373 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 374 | reg = <0x01c20098 0x4>; | |
| 375 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 376 | clock-output-names = "ts"; | |
| 377 | }; | |
| 378 | ||
| 379 | ss_clk: clk@01c2009c { | |
| 380 | #clock-cells = <0>; | |
| 381 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 382 | reg = <0x01c2009c 0x4>; | |
| 383 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 384 | clock-output-names = "ss"; | |
| 385 | }; | |
| 386 | ||
| 387 | spi0_clk: clk@01c200a0 { | |
| 388 | #clock-cells = <0>; | |
| 389 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 390 | reg = <0x01c200a0 0x4>; | |
| 391 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 392 | clock-output-names = "spi0"; | |
| 393 | }; | |
| 394 | ||
| 395 | spi1_clk: clk@01c200a4 { | |
| 396 | #clock-cells = <0>; | |
| 397 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 398 | reg = <0x01c200a4 0x4>; | |
| 399 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 400 | clock-output-names = "spi1"; | |
| 401 | }; | |
| 402 | ||
| 403 | spi2_clk: clk@01c200a8 { | |
| 404 | #clock-cells = <0>; | |
| 405 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 406 | reg = <0x01c200a8 0x4>; | |
| 407 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 408 | clock-output-names = "spi2"; | |
| 409 | }; | |
| 410 | ||
| 411 | pata_clk: clk@01c200ac { | |
| 412 | #clock-cells = <0>; | |
| 413 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 414 | reg = <0x01c200ac 0x4>; | |
| 415 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 416 | clock-output-names = "pata"; | |
| 417 | }; | |
| 418 | ||
| 419 | ir0_clk: clk@01c200b0 { | |
| 420 | #clock-cells = <0>; | |
| 421 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 422 | reg = <0x01c200b0 0x4>; | |
| 423 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 424 | clock-output-names = "ir0"; | |
| 425 | }; | |
| 426 | ||
| 427 | ir1_clk: clk@01c200b4 { | |
| 428 | #clock-cells = <0>; | |
| 429 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 430 | reg = <0x01c200b4 0x4>; | |
| 431 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 432 | clock-output-names = "ir1"; | |
| 433 | }; | |
| 434 | ||
| 435 | usb_clk: clk@01c200cc { | |
| 436 | #clock-cells = <1>; | |
| 437 | #reset-cells = <1>; | |
| 438 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 439 | reg = <0x01c200cc 0x4>; | |
| 440 | clocks = <&pll6 1>; | |
| 441 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 442 | }; | |
| 443 | ||
| 444 | spi3_clk: clk@01c200d4 { | |
| 445 | #clock-cells = <0>; | |
| 446 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 447 | reg = <0x01c200d4 0x4>; | |
| 448 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 449 | clock-output-names = "spi3"; | |
| 450 | }; | |
| 451 | }; | |
| 452 | ||
| 453 | /* | |
| 454 | * Note we use the address where the mmio registers start, not where | |
| 455 | * the SRAM blocks start, this cannot be changed because that would be | |
| 456 | * a devicetree ABI change. | |
| 457 | */ | |
| 458 | soc@01c00000 { | |
| 459 | compatible = "simple-bus"; | |
| 460 | #address-cells = <1>; | |
| 461 | #size-cells = <1>; | |
| 462 | ranges; | |
| 463 | ||
| 464 | sram@00000000 { | |
| 465 | compatible = "allwinner,sun4i-a10-sram"; | |
| 466 | reg = <0x00000000 0x4000>; | |
| 467 | allwinner,sram-name = "A1"; | |
| 468 | }; | |
| 469 | ||
| 470 | sram@00004000 { | |
| 471 | compatible = "allwinner,sun4i-a10-sram"; | |
| 472 | reg = <0x00004000 0x4000>; | |
| 473 | allwinner,sram-name = "A2"; | |
| 474 | }; | |
| 475 | ||
| 476 | sram@00008000 { | |
| 477 | compatible = "allwinner,sun4i-a10-sram"; | |
| 478 | reg = <0x00008000 0x4000>; | |
| 479 | allwinner,sram-name = "A3-A4"; | |
| 480 | }; | |
| 481 | ||
| 482 | sram@00010000 { | |
| 483 | compatible = "allwinner,sun4i-a10-sram"; | |
| 484 | reg = <0x00010000 0x1000>; | |
| 485 | allwinner,sram-name = "D"; | |
| 486 | }; | |
| 487 | ||
| 488 | sram-controller@01c00000 { | |
| 489 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
| 490 | reg = <0x01c00000 0x30>; | |
| 491 | }; | |
| 492 | ||
| 493 | dma: dma-controller@01c02000 { | |
| 494 | compatible = "allwinner,sun4i-a10-dma"; | |
| 495 | reg = <0x01c02000 0x1000>; | |
| 496 | interrupts = <27>; | |
| 497 | clocks = <&ahb_gates 6>; | |
| 498 | #dma-cells = <2>; | |
| 499 | }; | |
| 500 | ||
| 501 | spi0: spi@01c05000 { | |
| 502 | compatible = "allwinner,sun4i-a10-spi"; | |
| 503 | reg = <0x01c05000 0x1000>; | |
| 504 | interrupts = <10>; | |
| 505 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 506 | clock-names = "ahb", "mod"; | |
| 507 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, | |
| 508 | <&dma SUN4I_DMA_DEDICATED 26>; | |
| 509 | dma-names = "rx", "tx"; | |
| 510 | status = "disabled"; | |
| 511 | #address-cells = <1>; | |
| 512 | #size-cells = <0>; | |
| 513 | }; | |
| 514 | ||
| 515 | spi1: spi@01c06000 { | |
| 516 | compatible = "allwinner,sun4i-a10-spi"; | |
| 517 | reg = <0x01c06000 0x1000>; | |
| 518 | interrupts = <11>; | |
| 519 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 520 | clock-names = "ahb", "mod"; | |
| 521 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, | |
| 522 | <&dma SUN4I_DMA_DEDICATED 8>; | |
| 523 | dma-names = "rx", "tx"; | |
| 524 | status = "disabled"; | |
| 525 | #address-cells = <1>; | |
| 526 | #size-cells = <0>; | |
| 527 | }; | |
| 528 | ||
| 529 | emac: ethernet@01c0b000 { | |
| 530 | compatible = "allwinner,sun4i-a10-emac"; | |
| 531 | reg = <0x01c0b000 0x1000>; | |
| 532 | interrupts = <55>; | |
| 533 | clocks = <&ahb_gates 17>; | |
| 534 | status = "disabled"; | |
| 535 | }; | |
| 536 | ||
| 537 | mdio: mdio@01c0b080 { | |
| 538 | compatible = "allwinner,sun4i-a10-mdio"; | |
| 539 | reg = <0x01c0b080 0x14>; | |
| 540 | status = "disabled"; | |
| 541 | #address-cells = <1>; | |
| 542 | #size-cells = <0>; | |
| 543 | }; | |
| 544 | ||
| 545 | mmc0: mmc@01c0f000 { | |
| 546 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 547 | reg = <0x01c0f000 0x1000>; | |
| 548 | clocks = <&ahb_gates 8>, | |
| 549 | <&mmc0_clk 0>, | |
| 550 | <&mmc0_clk 1>, | |
| 551 | <&mmc0_clk 2>; | |
| 552 | clock-names = "ahb", | |
| 553 | "mmc", | |
| 554 | "output", | |
| 555 | "sample"; | |
| 556 | interrupts = <32>; | |
| 557 | status = "disabled"; | |
| 558 | #address-cells = <1>; | |
| 559 | #size-cells = <0>; | |
| 560 | }; | |
| 561 | ||
| 562 | mmc1: mmc@01c10000 { | |
| 563 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 564 | reg = <0x01c10000 0x1000>; | |
| 565 | clocks = <&ahb_gates 9>, | |
| 566 | <&mmc1_clk 0>, | |
| 567 | <&mmc1_clk 1>, | |
| 568 | <&mmc1_clk 2>; | |
| 569 | clock-names = "ahb", | |
| 570 | "mmc", | |
| 571 | "output", | |
| 572 | "sample"; | |
| 573 | interrupts = <33>; | |
| 574 | status = "disabled"; | |
| 575 | #address-cells = <1>; | |
| 576 | #size-cells = <0>; | |
| 577 | }; | |
| 578 | ||
| 579 | mmc2: mmc@01c11000 { | |
| 580 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 581 | reg = <0x01c11000 0x1000>; | |
| 582 | clocks = <&ahb_gates 10>, | |
| 583 | <&mmc2_clk 0>, | |
| 584 | <&mmc2_clk 1>, | |
| 585 | <&mmc2_clk 2>; | |
| 586 | clock-names = "ahb", | |
| 587 | "mmc", | |
| 588 | "output", | |
| 589 | "sample"; | |
| 590 | interrupts = <34>; | |
| 591 | status = "disabled"; | |
| 592 | #address-cells = <1>; | |
| 593 | #size-cells = <0>; | |
| 594 | }; | |
| 595 | ||
| 596 | mmc3: mmc@01c12000 { | |
| 597 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 598 | reg = <0x01c12000 0x1000>; | |
| 599 | clocks = <&ahb_gates 11>, | |
| 600 | <&mmc3_clk 0>, | |
| 601 | <&mmc3_clk 1>, | |
| 602 | <&mmc3_clk 2>; | |
| 603 | clock-names = "ahb", | |
| 604 | "mmc", | |
| 605 | "output", | |
| 606 | "sample"; | |
| 607 | interrupts = <35>; | |
| 608 | status = "disabled"; | |
| 609 | #address-cells = <1>; | |
| 610 | #size-cells = <0>; | |
| 611 | }; | |
| 612 | ||
| 613 | usbphy: phy@01c13400 { | |
| 614 | #phy-cells = <1>; | |
| 615 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
| 616 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 617 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 618 | clocks = <&usb_clk 8>; | |
| 619 | clock-names = "usb_phy"; | |
| 620 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; | |
| 621 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
| 622 | status = "disabled"; | |
| 623 | }; | |
| 624 | ||
| 625 | ehci0: usb@01c14000 { | |
| 626 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 627 | reg = <0x01c14000 0x100>; | |
| 628 | interrupts = <39>; | |
| 629 | clocks = <&ahb_gates 1>; | |
| 630 | phys = <&usbphy 1>; | |
| 631 | phy-names = "usb"; | |
| 632 | status = "disabled"; | |
| 633 | }; | |
| 634 | ||
| 635 | ohci0: usb@01c14400 { | |
| 636 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 637 | reg = <0x01c14400 0x100>; | |
| 638 | interrupts = <64>; | |
| 639 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 640 | phys = <&usbphy 1>; | |
| 641 | phy-names = "usb"; | |
| 642 | status = "disabled"; | |
| 643 | }; | |
| 644 | ||
| 645 | spi2: spi@01c17000 { | |
| 646 | compatible = "allwinner,sun4i-a10-spi"; | |
| 647 | reg = <0x01c17000 0x1000>; | |
| 648 | interrupts = <12>; | |
| 649 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 650 | clock-names = "ahb", "mod"; | |
| 651 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, | |
| 652 | <&dma SUN4I_DMA_DEDICATED 28>; | |
| 653 | dma-names = "rx", "tx"; | |
| 654 | status = "disabled"; | |
| 655 | #address-cells = <1>; | |
| 656 | #size-cells = <0>; | |
| 657 | }; | |
| 658 | ||
| 659 | ahci: sata@01c18000 { | |
| 660 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 661 | reg = <0x01c18000 0x1000>; | |
| 662 | interrupts = <56>; | |
| 663 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 664 | status = "disabled"; | |
| 665 | }; | |
| 666 | ||
| 667 | ehci1: usb@01c1c000 { | |
| 668 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 669 | reg = <0x01c1c000 0x100>; | |
| 670 | interrupts = <40>; | |
| 671 | clocks = <&ahb_gates 3>; | |
| 672 | phys = <&usbphy 2>; | |
| 673 | phy-names = "usb"; | |
| 674 | status = "disabled"; | |
| 675 | }; | |
| 676 | ||
| 677 | ohci1: usb@01c1c400 { | |
| 678 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 679 | reg = <0x01c1c400 0x100>; | |
| 680 | interrupts = <65>; | |
| 681 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 682 | phys = <&usbphy 2>; | |
| 683 | phy-names = "usb"; | |
| 684 | status = "disabled"; | |
| 685 | }; | |
| 686 | ||
| 687 | spi3: spi@01c1f000 { | |
| 688 | compatible = "allwinner,sun4i-a10-spi"; | |
| 689 | reg = <0x01c1f000 0x1000>; | |
| 690 | interrupts = <50>; | |
| 691 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 692 | clock-names = "ahb", "mod"; | |
| 693 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, | |
| 694 | <&dma SUN4I_DMA_DEDICATED 30>; | |
| 695 | dma-names = "rx", "tx"; | |
| 696 | status = "disabled"; | |
| 697 | #address-cells = <1>; | |
| 698 | #size-cells = <0>; | |
| 699 | }; | |
| 700 | ||
| 701 | intc: interrupt-controller@01c20400 { | |
| 702 | compatible = "allwinner,sun4i-a10-ic"; | |
| 703 | reg = <0x01c20400 0x400>; | |
| 704 | interrupt-controller; | |
| 705 | #interrupt-cells = <1>; | |
| 706 | }; | |
| 707 | ||
| 708 | pio: pinctrl@01c20800 { | |
| 709 | compatible = "allwinner,sun4i-a10-pinctrl"; | |
| 710 | reg = <0x01c20800 0x400>; | |
| 711 | interrupts = <28>; | |
| 712 | clocks = <&apb0_gates 5>; | |
| 713 | gpio-controller; | |
| 714 | interrupt-controller; | |
| 715 | #interrupt-cells = <2>; | |
| 716 | #size-cells = <0>; | |
| 717 | #gpio-cells = <3>; | |
| 718 | ||
| 719 | pwm0_pins_a: pwm0@0 { | |
| 720 | allwinner,pins = "PB2"; | |
| 721 | allwinner,function = "pwm"; | |
| 722 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 723 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 724 | }; | |
| 725 | ||
| 726 | pwm1_pins_a: pwm1@0 { | |
| 727 | allwinner,pins = "PI3"; | |
| 728 | allwinner,function = "pwm"; | |
| 729 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 730 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 731 | }; | |
| 732 | ||
| 733 | uart0_pins_a: uart0@0 { | |
| 734 | allwinner,pins = "PB22", "PB23"; | |
| 735 | allwinner,function = "uart0"; | |
| 736 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 737 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 738 | }; | |
| 739 | ||
| 740 | uart0_pins_b: uart0@1 { | |
| 741 | allwinner,pins = "PF2", "PF4"; | |
| 742 | allwinner,function = "uart0"; | |
| 743 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 744 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 745 | }; | |
| 746 | ||
| 747 | uart1_pins_a: uart1@0 { | |
| 748 | allwinner,pins = "PA10", "PA11"; | |
| 749 | allwinner,function = "uart1"; | |
| 750 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 751 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 752 | }; | |
| 753 | ||
| 754 | i2c0_pins_a: i2c0@0 { | |
| 755 | allwinner,pins = "PB0", "PB1"; | |
| 756 | allwinner,function = "i2c0"; | |
| 757 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 758 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 759 | }; | |
| 760 | ||
| 761 | i2c1_pins_a: i2c1@0 { | |
| 762 | allwinner,pins = "PB18", "PB19"; | |
| 763 | allwinner,function = "i2c1"; | |
| 764 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 765 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 766 | }; | |
| 767 | ||
| 768 | i2c2_pins_a: i2c2@0 { | |
| 769 | allwinner,pins = "PB20", "PB21"; | |
| 770 | allwinner,function = "i2c2"; | |
| 771 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 772 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 773 | }; | |
| 774 | ||
| 775 | emac_pins_a: emac0@0 { | |
| 776 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 777 | "PA3", "PA4", "PA5", "PA6", | |
| 778 | "PA7", "PA8", "PA9", "PA10", | |
| 779 | "PA11", "PA12", "PA13", "PA14", | |
| 780 | "PA15", "PA16"; | |
| 781 | allwinner,function = "emac"; | |
| 782 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 783 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 784 | }; | |
| 785 | ||
| 786 | mmc0_pins_a: mmc0@0 { | |
| 787 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
| 788 | allwinner,function = "mmc0"; | |
| 789 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
| 790 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 791 | }; | |
| 792 | ||
| 793 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
| 794 | allwinner,pins = "PH1"; | |
| 795 | allwinner,function = "gpio_in"; | |
| 796 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 797 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| 798 | }; | |
| 799 | ||
| 800 | ir0_pins_a: ir0@0 { | |
| 801 | allwinner,pins = "PB3","PB4"; | |
| 802 | allwinner,function = "ir0"; | |
| 803 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 804 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 805 | }; | |
| 806 | ||
| 807 | ir1_pins_a: ir1@0 { | |
| 808 | allwinner,pins = "PB22","PB23"; | |
| 809 | allwinner,function = "ir1"; | |
| 810 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 811 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 812 | }; | |
| 813 | ||
| 814 | spi0_pins_a: spi0@0 { | |
| 815 | allwinner,pins = "PI10", "PI11", "PI12", "PI13"; | |
| 816 | allwinner,function = "spi0"; | |
| 817 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 818 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 819 | }; | |
| 820 | ||
| 821 | spi1_pins_a: spi1@0 { | |
| 822 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 823 | allwinner,function = "spi1"; | |
| 824 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 825 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 826 | }; | |
| 827 | ||
| 828 | spi2_pins_a: spi2@0 { | |
| 829 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; | |
| 830 | allwinner,function = "spi2"; | |
| 831 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 832 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 833 | }; | |
| 834 | ||
| 835 | spi2_pins_b: spi2@1 { | |
| 836 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
| 837 | allwinner,function = "spi2"; | |
| 838 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 839 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 840 | }; | |
| 841 | ||
| 842 | ps20_pins_a: ps20@0 { | |
| 843 | allwinner,pins = "PI20", "PI21"; | |
| 844 | allwinner,function = "ps2"; | |
| 845 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 846 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 847 | }; | |
| 848 | ||
| 849 | ps21_pins_a: ps21@0 { | |
| 850 | allwinner,pins = "PH12", "PH13"; | |
| 851 | allwinner,function = "ps2"; | |
| 852 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 853 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 854 | }; | |
| 855 | }; | |
| 856 | ||
| 857 | timer@01c20c00 { | |
| 858 | compatible = "allwinner,sun4i-a10-timer"; | |
| 859 | reg = <0x01c20c00 0x90>; | |
| 860 | interrupts = <22>; | |
| 861 | clocks = <&osc24M>; | |
| 862 | }; | |
| 863 | ||
| 864 | wdt: watchdog@01c20c90 { | |
| 865 | compatible = "allwinner,sun4i-a10-wdt"; | |
| 866 | reg = <0x01c20c90 0x10>; | |
| 867 | }; | |
| 868 | ||
| 869 | rtc: rtc@01c20d00 { | |
| 870 | compatible = "allwinner,sun4i-a10-rtc"; | |
| 871 | reg = <0x01c20d00 0x20>; | |
| 872 | interrupts = <24>; | |
| 873 | }; | |
| 874 | ||
| 875 | pwm: pwm@01c20e00 { | |
| 876 | compatible = "allwinner,sun4i-a10-pwm"; | |
| 877 | reg = <0x01c20e00 0xc>; | |
| 878 | clocks = <&osc24M>; | |
| 879 | #pwm-cells = <3>; | |
| 880 | status = "disabled"; | |
| 881 | }; | |
| 882 | ||
| 883 | ir0: ir@01c21800 { | |
| 884 | compatible = "allwinner,sun4i-a10-ir"; | |
| 885 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
| 886 | clock-names = "apb", "ir"; | |
| 887 | interrupts = <5>; | |
| 888 | reg = <0x01c21800 0x40>; | |
| 889 | status = "disabled"; | |
| 890 | }; | |
| 891 | ||
| 892 | ir1: ir@01c21c00 { | |
| 893 | compatible = "allwinner,sun4i-a10-ir"; | |
| 894 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
| 895 | clock-names = "apb", "ir"; | |
| 896 | interrupts = <6>; | |
| 897 | reg = <0x01c21c00 0x40>; | |
| 898 | status = "disabled"; | |
| 899 | }; | |
| 900 | ||
| 901 | lradc: lradc@01c22800 { | |
| 902 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
| 903 | reg = <0x01c22800 0x100>; | |
| 904 | interrupts = <31>; | |
| 905 | status = "disabled"; | |
| 906 | }; | |
| 907 | ||
| 908 | sid: eeprom@01c23800 { | |
| 909 | compatible = "allwinner,sun4i-a10-sid"; | |
| 910 | reg = <0x01c23800 0x10>; | |
| 911 | }; | |
| 912 | ||
| 913 | rtp: rtp@01c25000 { | |
| 914 | compatible = "allwinner,sun4i-a10-ts"; | |
| 915 | reg = <0x01c25000 0x100>; | |
| 916 | interrupts = <29>; | |
| 917 | #thermal-sensor-cells = <0>; | |
| 918 | }; | |
| 919 | ||
| 920 | uart0: serial@01c28000 { | |
| 921 | compatible = "snps,dw-apb-uart"; | |
| 922 | reg = <0x01c28000 0x400>; | |
| 923 | interrupts = <1>; | |
| 924 | reg-shift = <2>; | |
| 925 | reg-io-width = <4>; | |
| 926 | clocks = <&apb1_gates 16>; | |
| 927 | status = "disabled"; | |
| 928 | }; | |
| 929 | ||
| 930 | uart1: serial@01c28400 { | |
| 931 | compatible = "snps,dw-apb-uart"; | |
| 932 | reg = <0x01c28400 0x400>; | |
| 933 | interrupts = <2>; | |
| 934 | reg-shift = <2>; | |
| 935 | reg-io-width = <4>; | |
| 936 | clocks = <&apb1_gates 17>; | |
| 937 | status = "disabled"; | |
| 938 | }; | |
| 939 | ||
| 940 | uart2: serial@01c28800 { | |
| 941 | compatible = "snps,dw-apb-uart"; | |
| 942 | reg = <0x01c28800 0x400>; | |
| 943 | interrupts = <3>; | |
| 944 | reg-shift = <2>; | |
| 945 | reg-io-width = <4>; | |
| 946 | clocks = <&apb1_gates 18>; | |
| 947 | status = "disabled"; | |
| 948 | }; | |
| 949 | ||
| 950 | uart3: serial@01c28c00 { | |
| 951 | compatible = "snps,dw-apb-uart"; | |
| 952 | reg = <0x01c28c00 0x400>; | |
| 953 | interrupts = <4>; | |
| 954 | reg-shift = <2>; | |
| 955 | reg-io-width = <4>; | |
| 956 | clocks = <&apb1_gates 19>; | |
| 957 | status = "disabled"; | |
| 958 | }; | |
| 959 | ||
| 960 | uart4: serial@01c29000 { | |
| 961 | compatible = "snps,dw-apb-uart"; | |
| 962 | reg = <0x01c29000 0x400>; | |
| 963 | interrupts = <17>; | |
| 964 | reg-shift = <2>; | |
| 965 | reg-io-width = <4>; | |
| 966 | clocks = <&apb1_gates 20>; | |
| 967 | status = "disabled"; | |
| 968 | }; | |
| 969 | ||
| 970 | uart5: serial@01c29400 { | |
| 971 | compatible = "snps,dw-apb-uart"; | |
| 972 | reg = <0x01c29400 0x400>; | |
| 973 | interrupts = <18>; | |
| 974 | reg-shift = <2>; | |
| 975 | reg-io-width = <4>; | |
| 976 | clocks = <&apb1_gates 21>; | |
| 977 | status = "disabled"; | |
| 978 | }; | |
| 979 | ||
| 980 | uart6: serial@01c29800 { | |
| 981 | compatible = "snps,dw-apb-uart"; | |
| 982 | reg = <0x01c29800 0x400>; | |
| 983 | interrupts = <19>; | |
| 984 | reg-shift = <2>; | |
| 985 | reg-io-width = <4>; | |
| 986 | clocks = <&apb1_gates 22>; | |
| 987 | status = "disabled"; | |
| 988 | }; | |
| 989 | ||
| 990 | uart7: serial@01c29c00 { | |
| 991 | compatible = "snps,dw-apb-uart"; | |
| 992 | reg = <0x01c29c00 0x400>; | |
| 993 | interrupts = <20>; | |
| 994 | reg-shift = <2>; | |
| 995 | reg-io-width = <4>; | |
| 996 | clocks = <&apb1_gates 23>; | |
| 997 | status = "disabled"; | |
| 998 | }; | |
| 999 | ||
| 1000 | i2c0: i2c@01c2ac00 { | |
| 1001 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1002 | reg = <0x01c2ac00 0x400>; | |
| 1003 | interrupts = <7>; | |
| 1004 | clocks = <&apb1_gates 0>; | |
| 1005 | status = "disabled"; | |
| 1006 | #address-cells = <1>; | |
| 1007 | #size-cells = <0>; | |
| 1008 | }; | |
| 1009 | ||
| 1010 | i2c1: i2c@01c2b000 { | |
| 1011 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1012 | reg = <0x01c2b000 0x400>; | |
| 1013 | interrupts = <8>; | |
| 1014 | clocks = <&apb1_gates 1>; | |
| 1015 | status = "disabled"; | |
| 1016 | #address-cells = <1>; | |
| 1017 | #size-cells = <0>; | |
| 1018 | }; | |
| 1019 | ||
| 1020 | i2c2: i2c@01c2b400 { | |
| 1021 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1022 | reg = <0x01c2b400 0x400>; | |
| 1023 | interrupts = <9>; | |
| 1024 | clocks = <&apb1_gates 2>; | |
| 1025 | status = "disabled"; | |
| 1026 | #address-cells = <1>; | |
| 1027 | #size-cells = <0>; | |
| 1028 | }; | |
| 1029 | ||
| 1030 | ps20: ps2@01c2a000 { | |
| 1031 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1032 | reg = <0x01c2a000 0x400>; | |
| 1033 | interrupts = <62>; | |
| 1034 | clocks = <&apb1_gates 6>; | |
| 1035 | status = "disabled"; | |
| 1036 | }; | |
| 1037 | ||
| 1038 | ps21: ps2@01c2a400 { | |
| 1039 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1040 | reg = <0x01c2a400 0x400>; | |
| 1041 | interrupts = <63>; | |
| 1042 | clocks = <&apb1_gates 7>; | |
| 1043 | status = "disabled"; | |
| 1044 | }; | |
| 1045 | }; | |
| 1046 | }; |