[J-u-boot.git] / drivers / mmc / atmel_sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Atmel Corporation
 *		      Wenyou.Yang <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/clk.h>
#include <asm/global_data.h>

#define ATMEL_SDHC_MIN_FREQ	400000
#define ATMEL_SDHC_GCK_RATE	240000000

#ifndef CONFIG_DM_MMC
int atmel_sdhci_init(void *regbase, u32 id)
{
	struct sdhci_host *host;
	u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;

	host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
	if (!host) {
		printf("%s: sdhci_host calloc failed\n", __func__);
		return -ENOMEM;
	}

	host->name = "atmel_sdhci";
	host->ioaddr = regbase;
	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
	max_clk = at91_get_periph_generated_clk(id);
	if (!max_clk) {
		printf("%s: Failed to get the proper clock\n", __func__);
		free(host);
		return -ENODEV;
	}
	host->max_clk = max_clk;

	add_sdhci(host, 0, min_clk);

	return 0;
}

#else

DECLARE_GLOBAL_DATA_PTR;

struct atmel_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

static int atmel_sdhci_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct atmel_sdhci_plat *plat = dev_get_plat(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	u32 max_clk;
	struct clk clk;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return ret;

	ret = clk_enable(&clk);
	if (ret)
		return ret;

	host->name = dev->name;
	host->ioaddr = dev_read_addr_ptr(dev);

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
	host->bus_width	= fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
					 "bus-width", 4);

	ret = clk_get_by_index(dev, 1, &clk);
	if (ret)
		return ret;

	clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);

	max_clk = clk_get_rate(&clk);
	if (!max_clk)
		return -EINVAL;

	ret = clk_enable(&clk);
	/* return error only if the clock really has a clock enable func */
	if (ret && ret != -ENOSYS)
		return ret;

	ret = mmc_of_parse(dev, &plat->cfg);
	if (ret)
		return ret;

	host->max_clk = max_clk;
	host->mmc = &plat->mmc;
	host->mmc->dev = dev;

	ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
	if (ret)
		return ret;

	host->mmc->priv = host;
	upriv->mmc = host->mmc;

	clk_free(&clk);

	return sdhci_probe(dev);
}

static int atmel_sdhci_bind(struct udevice *dev)
{
	struct atmel_sdhci_plat *plat = dev_get_plat(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id atmel_sdhci_ids[] = {
	{ .compatible = "atmel,sama5d2-sdhci" },
	{ .compatible = "microchip,sam9x60-sdhci" },
	{ .compatible = "microchip,sama7g5-sdhci" },
	{ }
};

U_BOOT_DRIVER(atmel_sdhci_drv) = {
	.name		= "atmel_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= atmel_sdhci_ids,
	.ops		= &sdhci_ops,
	.bind		= atmel_sdhci_bind,
	.probe		= atmel_sdhci_probe,
	.priv_auto	= sizeof(struct sdhci_host),
	.plat_auto	= sizeof(struct atmel_sdhci_plat),
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a3b59b15 WY	2	/*
	3	* Copyright (C) 2015 Atmel Corporation
	4	* Wenyou.Yang <[email protected]>
a3b59b15 WY	5	*/
	6
	7	#include <common.h>
a0d0d86f WY	8	#include <clk.h>
a0d0d86f WY	9	#include <dm.h>
a3b59b15 WY	10	#include <malloc.h>
	11	#include <sdhci.h>
	12	#include <asm/arch/clk.h>
401d1c4f	13	#include <asm/global_data.h>
a3b59b15 WY	14
a3b59b15 WY	15	#define ATMEL_SDHC_MIN_FREQ 400000
327713a6	16	#define ATMEL_SDHC_GCK_RATE 240000000
a3b59b15	17
a0d0d86f	18	#ifndef CONFIG_DM_MMC
a3b59b15 WY	19	int atmel_sdhci_init(void *regbase, u32 id)
	20	{
	21	struct sdhci_host *host;
	22	u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
	23
	24	host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
	25	if (!host) {
	26	printf("%s: sdhci_host calloc failed\n", __func__);
	27	return -ENOMEM;
	28	}
	29
	30	host->name = "atmel_sdhci";
	31	host->ioaddr = regbase;
b3125088	32	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
a3b59b15 WY	33	max_clk = at91_get_periph_generated_clk(id);
	34	if (!max_clk) {
	35	printf("%s: Failed to get the proper clock\n", __func__);
	36	free(host);
	37	return -ENODEV;
	38	}
6d0e34bf	39	host->max_clk = max_clk;
a3b59b15	40
6d0e34bf	41	add_sdhci(host, 0, min_clk);
a3b59b15 WY	42
	43	return 0;
	44	}
a0d0d86f WY	45
	46	#else
	47
	48	DECLARE_GLOBAL_DATA_PTR;
	49
	50	struct atmel_sdhci_plat {
	51	struct mmc_config cfg;
	52	struct mmc mmc;
	53	};
	54
a0d0d86f WY	55	static int atmel_sdhci_probe(struct udevice *dev)
	56	{
	57	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
c69cda25	58	struct atmel_sdhci_plat *plat = dev_get_plat(dev);
a0d0d86f WY	59	struct sdhci_host *host = dev_get_priv(dev);
a0d0d86f WY	60	u32 max_clk;
a0d0d86f WY	61	struct clk clk;
	62	int ret;
	63
339cb073	64	ret = clk_get_by_index(dev, 0, &clk);
a0d0d86f WY	65	if (ret)
	66	return ret;
	67
	68	ret = clk_enable(&clk);
	69	if (ret)
	70	return ret;
	71
	72	host->name = dev->name;
8613c8d8	73	host->ioaddr = dev_read_addr_ptr(dev);
a0d0d86f	74
b3125088	75	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
e160f7d4	76	host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
a0d0d86f WY	77	"bus-width", 4);
a0d0d86f WY	78
339cb073	79	ret = clk_get_by_index(dev, 1, &clk);
a0d0d86f WY	80	if (ret)
	81	return ret;
	82
2e00608c	83	clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
a0d0d86f WY	84
	85	max_clk = clk_get_rate(&clk);
	86	if (!max_clk)
	87	return -EINVAL;
	88
81f16438	89	ret = clk_enable(&clk);
7eace38d EH	90	/* return error only if the clock really has a clock enable func */
7eace38d EH	91	if (ret && ret != -ENOSYS)
81f16438 EH	92	return ret;
81f16438 EH	93
3710b464 EH	94	ret = mmc_of_parse(dev, &plat->cfg);
	95	if (ret)
	96	return ret;
	97
6d0e34bf	98	host->max_clk = max_clk;
7835e873 PF	99	host->mmc = &plat->mmc;
7835e873 PF	100	host->mmc->dev = dev;
6d0e34bf SH	101
6d0e34bf SH	102	ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
a0d0d86f WY	103	if (ret)
	104	return ret;
	105
a0d0d86f WY	106	host->mmc->priv = host;
	107	upriv->mmc = host->mmc;
	108
	109	clk_free(&clk);
	110
	111	return sdhci_probe(dev);
	112	}
	113
	114	static int atmel_sdhci_bind(struct udevice *dev)
	115	{
c69cda25	116	struct atmel_sdhci_plat *plat = dev_get_plat(dev);
a0d0d86f	117
24f5aec3	118	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
a0d0d86f WY	119	}
	120
	121	static const struct udevice_id atmel_sdhci_ids[] = {
	122	{ .compatible = "atmel,sama5d2-sdhci" },
f5663740	123	{ .compatible = "microchip,sam9x60-sdhci" },
4cc08258	124	{ .compatible = "microchip,sama7g5-sdhci" },
a0d0d86f WY	125	{ }
	126	};
	127
	128	U_BOOT_DRIVER(atmel_sdhci_drv) = {
	129	.name = "atmel_sdhci",
	130	.id = UCLASS_MMC,
	131	.of_match = atmel_sdhci_ids,
	132	.ops = &sdhci_ops,
	133	.bind = atmel_sdhci_bind,
	134	.probe = atmel_sdhci_probe,
41575d8e	135	.priv_auto = sizeof(struct sdhci_host),
caa4daa2	136	.plat_auto = sizeof(struct atmel_sdhci_plat),
a0d0d86f WY	137	};
a0d0d86f WY	138	#endif