[J-u-boot.git] / drivers / mmc / atmel_sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Atmel Corporation
 *		      Wenyou.Yang <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/clk.h>

#define ATMEL_SDHC_MIN_FREQ	400000
#define ATMEL_SDHC_GCK_RATE	240000000

#ifndef CONFIG_DM_MMC
int atmel_sdhci_init(void *regbase, u32 id)
{
	struct sdhci_host *host;
	u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;

	host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
	if (!host) {
		printf("%s: sdhci_host calloc failed\n", __func__);
		return -ENOMEM;
	}

	host->name = "atmel_sdhci";
	host->ioaddr = regbase;
	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
	max_clk = at91_get_periph_generated_clk(id);
	if (!max_clk) {
		printf("%s: Failed to get the proper clock\n", __func__);
		free(host);
		return -ENODEV;
	}
	host->max_clk = max_clk;

	add_sdhci(host, 0, min_clk);

	return 0;
}

#else

DECLARE_GLOBAL_DATA_PTR;

struct atmel_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

static int atmel_sdhci_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	u32 max_clk;
	struct clk clk;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return ret;

	ret = clk_enable(&clk);
	if (ret)
		return ret;

	host->name = dev->name;
	host->ioaddr = dev_read_addr_ptr(dev);

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
	host->bus_width	= fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
					 "bus-width", 4);

	ret = clk_get_by_index(dev, 1, &clk);
	if (ret)
		return ret;

	clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);

	max_clk = clk_get_rate(&clk);
	if (!max_clk)
		return -EINVAL;

	ret = clk_enable(&clk);
	if (ret)
		return ret;

	ret = mmc_of_parse(dev, &plat->cfg);
	if (ret)
		return ret;

	host->max_clk = max_clk;
	host->mmc = &plat->mmc;
	host->mmc->dev = dev;

	ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
	if (ret)
		return ret;

	host->mmc->priv = host;
	upriv->mmc = host->mmc;

	clk_free(&clk);

	return sdhci_probe(dev);
}

static int atmel_sdhci_bind(struct udevice *dev)
{
	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id atmel_sdhci_ids[] = {
	{ .compatible = "atmel,sama5d2-sdhci" },
	{ .compatible = "microchip,sam9x60-sdhci" },
	{ .compatible = "microchip,sama7g5-sdhci" },
	{ }
};

U_BOOT_DRIVER(atmel_sdhci_drv) = {
	.name		= "atmel_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= atmel_sdhci_ids,
	.ops		= &sdhci_ops,
	.bind		= atmel_sdhci_bind,
	.probe		= atmel_sdhci_probe,
	.priv_auto	= sizeof(struct sdhci_host),
	.platdata_auto	= sizeof(struct atmel_sdhci_plat),
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a3b59b15 WY	2	/*
	3	* Copyright (C) 2015 Atmel Corporation
	4	* Wenyou.Yang <[email protected]>
a3b59b15 WY	5	*/
	6
	7	#include <common.h>
a0d0d86f WY	8	#include <clk.h>
a0d0d86f WY	9	#include <dm.h>
a3b59b15 WY	10	#include <malloc.h>
	11	#include <sdhci.h>
	12	#include <asm/arch/clk.h>
	13
	14	#define ATMEL_SDHC_MIN_FREQ 400000
327713a6	15	#define ATMEL_SDHC_GCK_RATE 240000000
a3b59b15	16
a0d0d86f	17	#ifndef CONFIG_DM_MMC
a3b59b15 WY	18	int atmel_sdhci_init(void *regbase, u32 id)
	19	{
	20	struct sdhci_host *host;
	21	u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
	22
	23	host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
	24	if (!host) {
	25	printf("%s: sdhci_host calloc failed\n", __func__);
	26	return -ENOMEM;
	27	}
	28
	29	host->name = "atmel_sdhci";
	30	host->ioaddr = regbase;
b3125088	31	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
a3b59b15 WY	32	max_clk = at91_get_periph_generated_clk(id);
	33	if (!max_clk) {
	34	printf("%s: Failed to get the proper clock\n", __func__);
	35	free(host);
	36	return -ENODEV;
	37	}
6d0e34bf	38	host->max_clk = max_clk;
a3b59b15	39
6d0e34bf	40	add_sdhci(host, 0, min_clk);
a3b59b15 WY	41
	42	return 0;
	43	}
a0d0d86f WY	44
	45	#else
	46
	47	DECLARE_GLOBAL_DATA_PTR;
	48
	49	struct atmel_sdhci_plat {
	50	struct mmc_config cfg;
	51	struct mmc mmc;
	52	};
	53
a0d0d86f WY	54	static int atmel_sdhci_probe(struct udevice *dev)
	55	{
	56	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	57	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
	58	struct sdhci_host *host = dev_get_priv(dev);
	59	u32 max_clk;
a0d0d86f WY	60	struct clk clk;
	61	int ret;
	62
339cb073	63	ret = clk_get_by_index(dev, 0, &clk);
a0d0d86f WY	64	if (ret)
	65	return ret;
	66
	67	ret = clk_enable(&clk);
	68	if (ret)
	69	return ret;
	70
	71	host->name = dev->name;
8613c8d8	72	host->ioaddr = dev_read_addr_ptr(dev);
a0d0d86f	73
b3125088	74	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
e160f7d4	75	host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
a0d0d86f WY	76	"bus-width", 4);
a0d0d86f WY	77
339cb073	78	ret = clk_get_by_index(dev, 1, &clk);
a0d0d86f WY	79	if (ret)
	80	return ret;
	81
2e00608c	82	clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
a0d0d86f WY	83
	84	max_clk = clk_get_rate(&clk);
	85	if (!max_clk)
	86	return -EINVAL;
	87
81f16438 EH	88	ret = clk_enable(&clk);
	89	if (ret)
	90	return ret;
	91
3710b464 EH	92	ret = mmc_of_parse(dev, &plat->cfg);
	93	if (ret)
	94	return ret;
	95
6d0e34bf	96	host->max_clk = max_clk;
7835e873 PF	97	host->mmc = &plat->mmc;
7835e873 PF	98	host->mmc->dev = dev;
6d0e34bf SH	99
6d0e34bf SH	100	ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
a0d0d86f WY	101	if (ret)
	102	return ret;
	103
a0d0d86f WY	104	host->mmc->priv = host;
	105	upriv->mmc = host->mmc;
	106
	107	clk_free(&clk);
	108
	109	return sdhci_probe(dev);
	110	}
	111
	112	static int atmel_sdhci_bind(struct udevice *dev)
	113	{
	114	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
a0d0d86f	115
24f5aec3	116	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
a0d0d86f WY	117	}
	118
	119	static const struct udevice_id atmel_sdhci_ids[] = {
	120	{ .compatible = "atmel,sama5d2-sdhci" },
f5663740	121	{ .compatible = "microchip,sam9x60-sdhci" },
4cc08258	122	{ .compatible = "microchip,sama7g5-sdhci" },
a0d0d86f WY	123	{ }
	124	};
	125
	126	U_BOOT_DRIVER(atmel_sdhci_drv) = {
	127	.name = "atmel_sdhci",
	128	.id = UCLASS_MMC,
	129	.of_match = atmel_sdhci_ids,
	130	.ops = &sdhci_ops,
	131	.bind = atmel_sdhci_bind,
	132	.probe = atmel_sdhci_probe,
41575d8e SG	133	.priv_auto = sizeof(struct sdhci_host),
41575d8e SG	134	.platdata_auto = sizeof(struct atmel_sdhci_plat),
a0d0d86f WY	135	};
a0d0d86f WY	136	#endif