[J-u-boot.git] / arch / arm / mach-imx / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 */

#include <bootm.h>
#include <common.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/boot_mode.h>
#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>

#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#endif

static u32 reset_cause = -1;

u32 get_imx_reset_cause(void)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;

	if (reset_cause == -1) {
		reset_cause = readl(&src_regs->srsr);
/* preserve the value for U-Boot proper */
#if !defined(CONFIG_SPL_BUILD)
		writel(reset_cause, &src_regs->srsr);
#endif
	}

	return reset_cause;
}

#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
static char *get_reset_cause(void)
{
	switch (get_imx_reset_cause()) {
	case 0x00001:
	case 0x00011:
		return "POR";
	case 0x00004:
		return "CSU";
	case 0x00008:
		return "IPP USER";
	case 0x00010:
#ifdef	CONFIG_MX7
		return "WDOG1";
#else
		return "WDOG";
#endif
	case 0x00020:
		return "JTAG HIGH-Z";
	case 0x00040:
		return "JTAG SW";
	case 0x00080:
		return "WDOG3";
#ifdef CONFIG_MX7
	case 0x00100:
		return "WDOG4";
	case 0x00200:
		return "TEMPSENSE";
#elif defined(CONFIG_IMX8M)
	case 0x00100:
		return "WDOG2";
	case 0x00200:
		return "TEMPSENSE";
#else
	case 0x00100:
		return "TEMPSENSE";
	case 0x10000:
		return "WARM BOOT";
#endif
	default:
		return "unknown reset";
	}
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)

const char *get_imx_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_IMX8MP:
		return "8MP[8]";	/* Quad-core version of the imx8mp */
	case MXC_CPU_IMX8MPD:
		return "8MP Dual[3]";	/* Dual-core version of the imx8mp */
	case MXC_CPU_IMX8MPL:
		return "8MP Lite[4]";	/* Quad-core Lite version of the imx8mp */
	case MXC_CPU_IMX8MP6:
		return "8MP[6]";	/* Quad-core version of the imx8mp, NPU fused */
	case MXC_CPU_IMX8MN:
		return "8MNano Quad"; /* Quad-core version */
	case MXC_CPU_IMX8MND:
		return "8MNano Dual"; /* Dual-core version */
	case MXC_CPU_IMX8MNS:
		return "8MNano Solo"; /* Single-core version */
	case MXC_CPU_IMX8MNL:
		return "8MNano QuadLite"; /* Quad-core Lite version */
	case MXC_CPU_IMX8MNDL:
		return "8MNano DualLite"; /* Dual-core Lite version */
	case MXC_CPU_IMX8MNSL:
		return "8MNano SoloLite"; /* Single-core Lite version */
	case MXC_CPU_IMX8MM:
		return "8MMQ";	/* Quad-core version of the imx8mm */
	case MXC_CPU_IMX8MML:
		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MMD:
		return "8MMD";	/* Dual-core version of the imx8mm */
	case MXC_CPU_IMX8MMDL:
		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MMS:
		return "8MMS";	/* Single-core version of the imx8mm */
	case MXC_CPU_IMX8MMSL:
		return "8MMSL";	/* Single-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MQ:
		return "8MQ";	/* Quad-core version of the imx8mq */
	case MXC_CPU_IMX8MQL:
		return "8MQLite";	/* Quad-core Lite version of the imx8mq */
	case MXC_CPU_IMX8MD:
		return "8MD";	/* Dual-core version of the imx8mq */
	case MXC_CPU_MX7S:
		return "7S";	/* Single-core version of the mx7 */
	case MXC_CPU_MX7D:
		return "7D";	/* Dual-core version of the mx7 */
	case MXC_CPU_MX6QP:
		return "6QP";	/* Quad-Plus version of the mx6 */
	case MXC_CPU_MX6DP:
		return "6DP";	/* Dual-Plus version of the mx6 */
	case MXC_CPU_MX6Q:
		return "6Q";	/* Quad-core version of the mx6 */
	case MXC_CPU_MX6D:
		return "6D";	/* Dual-core version of the mx6 */
	case MXC_CPU_MX6DL:
		return "6DL";	/* Dual Lite version of the mx6 */
	case MXC_CPU_MX6SOLO:
		return "6SOLO";	/* Solo version of the mx6 */
	case MXC_CPU_MX6SL:
		return "6SL";	/* Solo-Lite version of the mx6 */
	case MXC_CPU_MX6SLL:
		return "6SLL";	/* SLL version of the mx6 */
	case MXC_CPU_MX6SX:
		return "6SX";   /* SoloX version of the mx6 */
	case MXC_CPU_MX6UL:
		return "6UL";   /* Ultra-Lite version of the mx6 */
	case MXC_CPU_MX6ULL:
		return "6ULL";	/* ULL version of the mx6 */
	case MXC_CPU_MX6ULZ:
		return "6ULZ";	/* ULZ version of the mx6 */
	case MXC_CPU_MX51:
		return "51";
	case MXC_CPU_MX53:
		return "53";
	default:
		return "??";
	}
}

int print_cpuinfo(void)
{
	u32 cpurev;
	__maybe_unused u32 max_freq;

	cpurev = get_cpu_rev();

#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
	struct udevice *thermal_dev;
	int cpu_tmp, minc, maxc, ret;

	printf("CPU:   Freescale i.MX%s rev%d.%d",
	       get_imx_type((cpurev & 0x1FF000) >> 12),
	       (cpurev & 0x000F0) >> 4,
	       (cpurev & 0x0000F) >> 0);
	max_freq = get_cpu_speed_grade_hz();
	if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
		printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	} else {
		printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
	}
#else
	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
		get_imx_type((cpurev & 0x1FF000) >> 12),
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif

#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
	puts("CPU:   ");
	switch (get_cpu_temp_grade(&minc, &maxc)) {
	case TEMP_AUTOMOTIVE:
		puts("Automotive temperature grade ");
		break;
	case TEMP_INDUSTRIAL:
		puts("Industrial temperature grade ");
		break;
	case TEMP_EXTCOMMERCIAL:
		puts("Extended Commercial temperature grade ");
		break;
	default:
		puts("Commercial temperature grade ");
		break;
	}
	printf("(%dC to %dC)", minc, maxc);
	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	if (!ret) {
		ret = thermal_get_temp(thermal_dev, &cpu_tmp);

		if (!ret)
			printf(" at %dC", cpu_tmp);
		else
			debug(" - invalid sensor data\n");
	} else {
		debug(" - invalid sensor device\n");
	}
	puts("\n");
#endif

	printf("Reset cause: %s\n", get_reset_cause());
	return 0;
}
#endif

int cpu_eth_init(struct bd_info *bis)
{
	int rc = -ENODEV;

#if defined(CONFIG_FEC_MXC)
	rc = fecmxc_initialize(bis);
#endif

	return rc;
}

#ifdef CONFIG_FSL_ESDHC_IMX
/*
 * Initializes on-chip MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(struct bd_info *bis)
{
	return fsl_esdhc_mmc_init(bis);
}
#endif

#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
u32 get_ahb_clk(void)
{
	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, ahb_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;

	return get_periph_clk() / (ahb_podf + 1);
}
#endif

void arch_preboot_os(void)
{
#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
	imx_pcie_remove();
#endif

#if defined(CONFIG_IMX_AHCI)
	struct udevice *dev;
	int rc;

	rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
	if (!rc && dev) {
		rc = device_remove(dev, DM_REMOVE_NORMAL);
		if (rc)
			printf("Cannot remove SATA device '%s' (err=%d)\n",
				dev->name, rc);
	}
#endif

#if defined(CONFIG_SATA)
	if (!is_mx6sdl()) {
		sata_remove(0);
#if defined(CONFIG_MX6)
		disable_sata_clock();
#endif
	}
#endif
#if defined(CONFIG_VIDEO_IPUV3)
	/* disable video before launching O/S */
	ipuv3_fb_shutdown();
#endif
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
	lcdif_power_down();
#endif
}

#ifndef CONFIG_IMX8M
void set_chipselect_size(int const cs_size)
{
	unsigned int reg;
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	reg = readl(&iomuxc_regs->gpr[1]);

	switch (cs_size) {
	case CS0_128:
		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
		reg |= 0x5;
		break;
	case CS0_64M_CS1_64M:
		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
		reg |= 0x1B;
		break;
	case CS0_64M_CS1_32M_CS2_32M:
		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
		reg |= 0x4B;
		break;
	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
		reg |= 0x249;
		break;
	default:
		printf("Unknown chip select size: %d\n", cs_size);
		break;
	}

	writel(reg, &iomuxc_regs->gpr[1]);
}
#endif

#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
/*
 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_SPEED_SHIFT	8
enum cpu_speed {
	OCOTP_TESTER3_SPEED_GRADE0,
	OCOTP_TESTER3_SPEED_GRADE1,
	OCOTP_TESTER3_SPEED_GRADE2,
	OCOTP_TESTER3_SPEED_GRADE3,
	OCOTP_TESTER3_SPEED_GRADE4,
};

u32 get_cpu_speed_grade_hz(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	val >>= OCOTP_TESTER3_SPEED_SHIFT;

	if (is_imx8mn() || is_imx8mp()) {
		val &= 0xf;
		return 2300000000 - val * 100000000;
	}

	if (is_imx8mm())
		val &= 0x7;
	else
		val &= 0x3;

	switch(val) {
	case OCOTP_TESTER3_SPEED_GRADE0:
		return 800000000;
	case OCOTP_TESTER3_SPEED_GRADE1:
		return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
	case OCOTP_TESTER3_SPEED_GRADE2:
		return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
	case OCOTP_TESTER3_SPEED_GRADE3:
		return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
	case OCOTP_TESTER3_SPEED_GRADE4:
		return 2000000000;
	}

	return 0;
}

/*
 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_TEMP_SHIFT	6

/* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
#define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT	5

u32 get_cpu_temp_grade(int *minc, int *maxc)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	if (is_imx8mp())
		val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
	else
		val >>= OCOTP_TESTER3_TEMP_SHIFT;
	val &= 0x3;

	if (minc && maxc) {
		if (val == TEMP_AUTOMOTIVE) {
			*minc = -40;
			*maxc = 125;
		} else if (val == TEMP_INDUSTRIAL) {
			*minc = -40;
			*maxc = 105;
		} else if (val == TEMP_EXTCOMMERCIAL) {
			*minc = -20;
			*maxc = 105;
		} else {
			*minc = 0;
			*maxc = 95;
		}
	}
	return val;
}
#endif

#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
enum boot_device get_boot_device(void)
{
	struct bootrom_sw_info **p =
		(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;

	enum boot_device boot_dev = SD1_BOOT;
	u8 boot_type = (*p)->boot_dev_type;
	u8 boot_instance = (*p)->boot_dev_instance;

	switch (boot_type) {
	case BOOT_TYPE_SD:
		boot_dev = boot_instance + SD1_BOOT;
		break;
	case BOOT_TYPE_MMC:
		boot_dev = boot_instance + MMC1_BOOT;
		break;
	case BOOT_TYPE_NAND:
		boot_dev = NAND_BOOT;
		break;
	case BOOT_TYPE_QSPI:
		boot_dev = QSPI_BOOT;
		break;
	case BOOT_TYPE_WEIM:
		boot_dev = WEIM_NOR_BOOT;
		break;
	case BOOT_TYPE_SPINOR:
		boot_dev = SPI_NOR_BOOT;
		break;
	case BOOT_TYPE_USB:
		boot_dev = USB_BOOT;
		break;
	default:
#ifdef CONFIG_IMX8M
		if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
			boot_dev = QSPI_BOOT;
#endif
		break;
	}

	return boot_dev;
}
#endif

#ifdef CONFIG_NXP_BOARD_REVISION
int nxp_board_rev(void)
{
	/*
	 * Get Board ID information from OCOTP_GP1[15:8]
	 * RevA: 0x1
	 * RevB: 0x2
	 * RevC: 0x3
	 */
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	return (readl(&fuse->gp1) >> 8 & 0x0F);
}

char nxp_board_rev_string(void)
{
	const char *rev = "A";

	return (*rev + nxp_board_rev() - 1);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
18936ee2 JL	2	/*
	3	* (C) Copyright 2007
	4	* Sascha Hauer, Pengutronix
	5	*
	6	* (C) Copyright 2009 Freescale Semiconductor, Inc.
18936ee2 JL	7	*/
18936ee2 JL	8
5624c6bd	9	#include <bootm.h>
18936ee2	10	#include <common.h>
055efe56	11	#include <dm.h>
691d719d	12	#include <init.h>
f7ae49fc	13	#include <log.h>
90526e9f	14	#include <net.h>
5624c6bd	15	#include <netdev.h>
1221ce45	16	#include <linux/errno.h>
18936ee2 JL	17	#include <asm/io.h>
	18	#include <asm/arch/imx-regs.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/sys_proto.h>
6a376046	21	#include <asm/arch/crm_regs.h>
770611f2	22	#include <asm/mach-imx/boot_mode.h>
70caa8e2	23	#include <imx_thermal.h>
e1eb75b5	24	#include <ipu_pixfmt.h>
7a264168	25	#include <thermal.h>
44b9841d	26	#include <sata.h>
acc403cb YL	27	#include <dm/device-internal.h>
acc403cb YL	28	#include <dm/uclass-internal.h>
18936ee2	29
e37ac717 YL	30	#ifdef CONFIG_FSL_ESDHC_IMX
e37ac717 YL	31	#include <fsl_esdhc_imx.h>
18936ee2 JL	32	#endif
18936ee2 JL	33
11c2e505 EN	34	static u32 reset_cause = -1;
11c2e505 EN	35
6ed4d26c	36	u32 get_imx_reset_cause(void)
18936ee2	37	{
18936ee2 JL	38	struct src src_regs = (struct src )SRC_BASE_ADDR;
18936ee2 JL	39
6ed4d26c MK	40	if (reset_cause == -1) {
	41	reset_cause = readl(&src_regs->srsr);
	42	/* preserve the value for U-Boot proper */
	43	#if !defined(CONFIG_SPL_BUILD)
	44	writel(reset_cause, &src_regs->srsr);
	45	#endif
	46	}
	47
	48	return reset_cause;
	49	}
18936ee2	50
6ed4d26c MK	51	#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
	52	static char *get_reset_cause(void)
	53	{
	54	switch (get_imx_reset_cause()) {
18936ee2	55	case 0x00001:
cece2622	56	case 0x00011:
18936ee2 JL	57	return "POR";
	58	case 0x00004:
	59	return "CSU";
	60	case 0x00008:
	61	return "IPP USER";
	62	case 0x00010:
cd562c8d AA	63	#ifdef CONFIG_MX7
	64	return "WDOG1";
	65	#else
18936ee2	66	return "WDOG";
cd562c8d	67	#endif
18936ee2 JL	68	case 0x00020:
	69	return "JTAG HIGH-Z";
	70	case 0x00040:
	71	return "JTAG SW";
cd562c8d AA	72	case 0x00080:
	73	return "WDOG3";
	74	#ifdef CONFIG_MX7
	75	case 0x00100:
	76	return "WDOG4";
	77	case 0x00200:
	78	return "TEMPSENSE";
cd357ad1	79	#elif defined(CONFIG_IMX8M)
7537e932 PF	80	case 0x00100:
	81	return "WDOG2";
	82	case 0x00200:
	83	return "TEMPSENSE";
cd562c8d AA	84	#else
	85	case 0x00100:
	86	return "TEMPSENSE";
18936ee2 JL	87	case 0x10000:
18936ee2 JL	88	return "WARM BOOT";
cd562c8d	89	#endif
18936ee2 JL	90	default:
	91	return "unknown reset";
	92	}
	93	}
28420e78	94	#endif
11c2e505	95
38df3701	96	#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
a7683867	97
20332a06	98	const char *get_imx_type(u32 imxtype)
a7683867 FE	99	{
a7683867 FE	100	switch (imxtype) {
625b03d8	101	case MXC_CPU_IMX8MP:
d1eee7ee YL	102	return "8MP[8]"; /* Quad-core version of the imx8mp */
	103	case MXC_CPU_IMX8MPD:
	104	return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
	105	case MXC_CPU_IMX8MPL:
	106	return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
d1eee7ee YL	107	case MXC_CPU_IMX8MP6:
d1eee7ee YL	108	return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
2434131a	109	case MXC_CPU_IMX8MN:
c9154032 PF	110	return "8MNano Quad"; /* Quad-core version */
	111	case MXC_CPU_IMX8MND:
	112	return "8MNano Dual"; /* Dual-core version */
	113	case MXC_CPU_IMX8MNS:
	114	return "8MNano Solo"; /* Single-core version */
	115	case MXC_CPU_IMX8MNL:
	116	return "8MNano QuadLite"; /* Quad-core Lite version */
	117	case MXC_CPU_IMX8MNDL:
	118	return "8MNano DualLite"; /* Dual-core Lite version */
	119	case MXC_CPU_IMX8MNSL:
	120	return "8MNano SoloLite"; /* Single-core Lite version */
65a6c500 PF	121	case MXC_CPU_IMX8MM:
	122	return "8MMQ"; /* Quad-core version of the imx8mm */
	123	case MXC_CPU_IMX8MML:
	124	return "8MMQL"; /* Quad-core Lite version of the imx8mm */
	125	case MXC_CPU_IMX8MMD:
	126	return "8MMD"; /* Dual-core version of the imx8mm */
	127	case MXC_CPU_IMX8MMDL:
	128	return "8MMDL"; /* Dual-core Lite version of the imx8mm */
	129	case MXC_CPU_IMX8MMS:
	130	return "8MMS"; /* Single-core version of the imx8mm */
	131	case MXC_CPU_IMX8MMSL:
	132	return "8MMSL"; /* Single-core Lite version of the imx8mm */
cd357ad1	133	case MXC_CPU_IMX8MQ:
cb1a1de6 PF	134	return "8MQ"; /* Quad-core version of the imx8mq */
	135	case MXC_CPU_IMX8MQL:
	136	return "8MQLite"; /* Quad-core Lite version of the imx8mq */
	137	case MXC_CPU_IMX8MD:
	138	return "8MD"; /* Dual-core version of the imx8mq */
e25a0656	139	case MXC_CPU_MX7S:
249092fa	140	return "7S"; /* Single-core version of the mx7 */
cd562c8d AA	141	case MXC_CPU_MX7D:
cd562c8d AA	142	return "7D"; /* Dual-core version of the mx7 */
d0acd993 PF	143	case MXC_CPU_MX6QP:
	144	return "6QP"; /* Quad-Plus version of the mx6 */
	145	case MXC_CPU_MX6DP:
	146	return "6DP"; /* Dual-Plus version of the mx6 */
20332a06	147	case MXC_CPU_MX6Q:
a7683867	148	return "6Q"; /* Quad-core version of the mx6 */
94db6655 FE	149	case MXC_CPU_MX6D:
94db6655 FE	150	return "6D"; /* Dual-core version of the mx6 */
20332a06 TK	151	case MXC_CPU_MX6DL:
	152	return "6DL"; /* Dual Lite version of the mx6 */
	153	case MXC_CPU_MX6SOLO:
	154	return "6SOLO"; /* Solo version of the mx6 */
	155	case MXC_CPU_MX6SL:
a7683867	156	return "6SL"; /* Solo-Lite version of the mx6 */
7ce6d3c8 PF	157	case MXC_CPU_MX6SLL:
7ce6d3c8 PF	158	return "6SLL"; /* SLL version of the mx6 */
05d54b82 FE	159	case MXC_CPU_MX6SX:
05d54b82 FE	160	return "6SX"; /* SoloX version of the mx6 */
8631c06e PF	161	case MXC_CPU_MX6UL:
8631c06e PF	162	return "6UL"; /* Ultra-Lite version of the mx6 */
65ce54be PF	163	case MXC_CPU_MX6ULL:
65ce54be PF	164	return "6ULL"; /* ULL version of the mx6 */
81ae46c2 PF	165	case MXC_CPU_MX6ULZ:
81ae46c2 PF	166	return "6ULZ"; /* ULZ version of the mx6 */
20332a06	167	case MXC_CPU_MX51:
a7683867	168	return "51";
20332a06	169	case MXC_CPU_MX53:
a7683867 FE	170	return "53";
a7683867 FE	171	default:
e972d72b	172	return "??";
a7683867 FE	173	}
	174	}
	175
18936ee2 JL	176	int print_cpuinfo(void)
18936ee2 JL	177	{
943a3f2c SB	178	u32 cpurev;
943a3f2c SB	179	__maybe_unused u32 max_freq;
18936ee2	180
1368f993 AA	181	cpurev = get_cpu_rev();
1368f993 AA	182
dc597d1d	183	#if defined(CONFIG_IMX_THERMAL) \|\| defined(CONFIG_IMX_TMU)
7a264168	184	struct udevice *thermal_dev;
70caa8e2	185	int cpu_tmp, minc, maxc, ret;
a7683867	186
b83ddac8	187	printf("CPU: Freescale i.MX%s rev%d.%d",
13868eaf	188	get_imx_type((cpurev & 0x1FF000) >> 12),
b83ddac8 TH	189	(cpurev & 0x000F0) >> 4,
	190	(cpurev & 0x0000F) >> 0);
	191	max_freq = get_cpu_speed_grade_hz();
	192	if (!max_freq \|\| max_freq == mxc_get_clock(MXC_ARM_CLK)) {
	193	printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	194	} else {
	195	printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
	196	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	197	}
	198	#else
a7683867	199	printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
13868eaf	200	get_imx_type((cpurev & 0x1FF000) >> 12),
18936ee2 JL	201	(cpurev & 0x000F0) >> 4,
	202	(cpurev & 0x0000F) >> 0,
	203	mxc_get_clock(MXC_ARM_CLK) / 1000000);
b83ddac8	204	#endif
7a264168	205
dc597d1d	206	#if defined(CONFIG_IMX_THERMAL) \|\| defined(CONFIG_IMX_TMU)
70caa8e2 TH	207	puts("CPU: ");
	208	switch (get_cpu_temp_grade(&minc, &maxc)) {
	209	case TEMP_AUTOMOTIVE:
	210	puts("Automotive temperature grade ");
	211	break;
	212	case TEMP_INDUSTRIAL:
	213	puts("Industrial temperature grade ");
	214	break;
	215	case TEMP_EXTCOMMERCIAL:
	216	puts("Extended Commercial temperature grade ");
	217	break;
	218	default:
	219	puts("Commercial temperature grade ");
	220	break;
	221	}
	222	printf("(%dC to %dC)", minc, maxc);
7a264168 YL	223	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	224	if (!ret) {
	225	ret = thermal_get_temp(thermal_dev, &cpu_tmp);
	226
	227	if (!ret)
9d416288	228	printf(" at %dC", cpu_tmp);
7a264168	229	else
3a384b49	230	debug(" - invalid sensor data\n");
7a264168	231	} else {
3a384b49	232	debug(" - invalid sensor device\n");
7a264168	233	}
9d416288	234	puts("\n");
7a264168 YL	235	#endif
7a264168 YL	236
18936ee2 JL	237	printf("Reset cause: %s\n", get_reset_cause());
	238	return 0;
	239	}
	240	#endif
	241
b75d8dc5	242	int cpu_eth_init(struct bd_info *bis)
18936ee2 JL	243	{
	244	int rc = -ENODEV;
	245
	246	#if defined(CONFIG_FEC_MXC)
	247	rc = fecmxc_initialize(bis);
	248	#endif
	249
	250	return rc;
	251	}
	252
e37ac717	253	#ifdef CONFIG_FSL_ESDHC_IMX
18936ee2 JL	254	/*
	255	* Initializes on-chip MMC controllers.
	256	* to override, implement board_mmc_init()
	257	*/
b75d8dc5	258	int cpu_mmc_init(struct bd_info *bis)
18936ee2	259	{
18936ee2	260	return fsl_esdhc_mmc_init(bis);
18936ee2	261	}
ecb0f317	262	#endif
18936ee2	263
cd357ad1	264	#if !(defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8M))
6a376046 FE	265	u32 get_ahb_clk(void)
	266	{
	267	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	268	u32 reg, ahb_podf;
	269
	270	reg = __raw_readl(&imx_ccm->cbcdr);
	271	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	272	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
	273
	274	return get_periph_clk() / (ahb_podf + 1);
	275	}
cd562c8d	276	#endif
e1eb75b5	277
e1eb75b5 EN	278	void arch_preboot_os(void)
e1eb75b5 EN	279	{
42dc1230	280	#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
6ecbe137 TH	281	imx_pcie_remove();
6ecbe137 TH	282	#endif
acc403cb YL	283
	284	#if defined(CONFIG_IMX_AHCI)
	285	struct udevice *dev;
	286	int rc;
	287
	288	rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
	289	if (!rc && dev) {
	290	rc = device_remove(dev, DM_REMOVE_NORMAL);
	291	if (rc)
	292	printf("Cannot remove SATA device '%s' (err=%d)\n",
	293	dev->name, rc);
	294	}
	295	#endif
	296
10e40d54	297	#if defined(CONFIG_SATA)
86e59530 LZ	298	if (!is_mx6sdl()) {
86e59530 LZ	299	sata_remove(0);
dd1c8f1b	300	#if defined(CONFIG_MX6)
86e59530	301	disable_sata_clock();
dd1c8f1b	302	#endif
86e59530	303	}
44b9841d NK	304	#endif
44b9841d NK	305	#if defined(CONFIG_VIDEO_IPUV3)
e1eb75b5 EN	306	/* disable video before launching O/S */
e1eb75b5 EN	307	ipuv3_fb_shutdown();
e1eb75b5	308	#endif
8c1df09f	309	#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
623787fd PF	310	lcdif_power_down();
623787fd PF	311	#endif
44b9841d	312	}
32c81ea6	313
cd357ad1	314	#ifndef CONFIG_IMX8M
32c81ea6 FE	315	void set_chipselect_size(int const cs_size)
	316	{
	317	unsigned int reg;
	318	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	319	reg = readl(&iomuxc_regs->gpr[1]);
	320
	321	switch (cs_size) {
	322	case CS0_128:
	323	reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
	324	reg \|= 0x5;
	325	break;
	326	case CS0_64M_CS1_64M:
	327	reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
	328	reg \|= 0x1B;
	329	break;
	330	case CS0_64M_CS1_32M_CS2_32M:
	331	reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
	332	reg \|= 0x4B;
	333	break;
	334	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
	335	reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
	336	reg \|= 0x249;
	337	break;
	338	default:
	339	printf("Unknown chip select size: %d\n", cs_size);
	340	break;
	341	}
	342
	343	writel(reg, &iomuxc_regs->gpr[1]);
	344	}
7537e932	345	#endif
4555c261	346
cd357ad1	347	#if defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8M)
423e84bc PF	348	/*
	349	* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
	350	* defines a 2-bit SPEED_GRADING
	351	*/
	352	#define OCOTP_TESTER3_SPEED_SHIFT 8
e56d9d79 PF	353	enum cpu_speed {
	354	OCOTP_TESTER3_SPEED_GRADE0,
	355	OCOTP_TESTER3_SPEED_GRADE1,
	356	OCOTP_TESTER3_SPEED_GRADE2,
	357	OCOTP_TESTER3_SPEED_GRADE3,
47586a4a	358	OCOTP_TESTER3_SPEED_GRADE4,
e56d9d79	359	};
423e84bc PF	360
	361	u32 get_cpu_speed_grade_hz(void)
	362	{
	363	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	364	struct fuse_bank *bank = &ocotp->bank[1];
	365	struct fuse_bank1_regs *fuse =
	366	(struct fuse_bank1_regs *)bank->fuse_regs;
	367	uint32_t val;
	368
	369	val = readl(&fuse->tester3);
	370	val >>= OCOTP_TESTER3_SPEED_SHIFT;
47586a4a	371
354dcce6	372	if (is_imx8mn() \|\| is_imx8mp()) {
47586a4a PF	373	val &= 0xf;
	374	return 2300000000 - val * 100000000;
	375	}
	376
	377	if (is_imx8mm())
	378	val &= 0x7;
	379	else
	380	val &= 0x3;
423e84bc PF	381
423e84bc PF	382	switch(val) {
e56d9d79	383	case OCOTP_TESTER3_SPEED_GRADE0:
423e84bc	384	return 800000000;
e56d9d79	385	case OCOTP_TESTER3_SPEED_GRADE1:
c9a1a24b	386	return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
e56d9d79	387	case OCOTP_TESTER3_SPEED_GRADE2:
c9a1a24b	388	return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
e56d9d79	389	case OCOTP_TESTER3_SPEED_GRADE3:
c9a1a24b	390	return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
47586a4a PF	391	case OCOTP_TESTER3_SPEED_GRADE4:
47586a4a PF	392	return 2000000000;
423e84bc	393	}
e56d9d79	394
423e84bc PF	395	return 0;
	396	}
	397
	398	/*
	399	* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
	400	* defines a 2-bit SPEED_GRADING
	401	*/
	402	#define OCOTP_TESTER3_TEMP_SHIFT 6
	403
79e0217a YL	404	/* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
	405	#define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
	406
423e84bc PF	407	u32 get_cpu_temp_grade(int minc, int maxc)
	408	{
	409	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	410	struct fuse_bank *bank = &ocotp->bank[1];
	411	struct fuse_bank1_regs *fuse =
	412	(struct fuse_bank1_regs *)bank->fuse_regs;
	413	uint32_t val;
	414
	415	val = readl(&fuse->tester3);
79e0217a YL	416	if (is_imx8mp())
	417	val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
	418	else
	419	val >>= OCOTP_TESTER3_TEMP_SHIFT;
423e84bc PF	420	val &= 0x3;
	421
	422	if (minc && maxc) {
	423	if (val == TEMP_AUTOMOTIVE) {
	424	*minc = -40;
	425	*maxc = 125;
	426	} else if (val == TEMP_INDUSTRIAL) {
	427	*minc = -40;
	428	*maxc = 105;
	429	} else if (val == TEMP_EXTCOMMERCIAL) {
	430	*minc = -20;
	431	*maxc = 105;
	432	} else {
	433	*minc = 0;
	434	*maxc = 95;
	435	}
	436	}
	437	return val;
	438	}
	439	#endif
	440
b890c4ae	441	#if defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8MQ) \|\| defined(CONFIG_IMX8MM)
770611f2 PF	442	enum boot_device get_boot_device(void)
	443	{
	444	struct bootrom_sw_info **p =
	445	(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
	446
	447	enum boot_device boot_dev = SD1_BOOT;
	448	u8 boot_type = (*p)->boot_dev_type;
	449	u8 boot_instance = (*p)->boot_dev_instance;
	450
	451	switch (boot_type) {
	452	case BOOT_TYPE_SD:
	453	boot_dev = boot_instance + SD1_BOOT;
	454	break;
	455	case BOOT_TYPE_MMC:
	456	boot_dev = boot_instance + MMC1_BOOT;
	457	break;
	458	case BOOT_TYPE_NAND:
	459	boot_dev = NAND_BOOT;
	460	break;
	461	case BOOT_TYPE_QSPI:
	462	boot_dev = QSPI_BOOT;
	463	break;
	464	case BOOT_TYPE_WEIM:
	465	boot_dev = WEIM_NOR_BOOT;
	466	break;
	467	case BOOT_TYPE_SPINOR:
	468	boot_dev = SPI_NOR_BOOT;
	469	break;
80ebf86d PF	470	case BOOT_TYPE_USB:
	471	boot_dev = USB_BOOT;
	472	break;
770611f2	473	default:
d4e84f24 PF	474	#ifdef CONFIG_IMX8M
	475	if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
	476	boot_dev = QSPI_BOOT;
	477	#endif
770611f2 PF	478	break;
	479	}
	480
	481	return boot_dev;
	482	}
	483	#endif
	484
4555c261 FE	485	#ifdef CONFIG_NXP_BOARD_REVISION
	486	int nxp_board_rev(void)
	487	{
	488	/*
	489	* Get Board ID information from OCOTP_GP1[15:8]
	490	* RevA: 0x1
	491	* RevB: 0x2
	492	* RevC: 0x3
	493	*/
	494	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	495	struct fuse_bank *bank = &ocotp->bank[4];
	496	struct fuse_bank4_regs *fuse =
	497	(struct fuse_bank4_regs *)bank->fuse_regs;
	498
	499	return (readl(&fuse->gp1) >> 8 & 0x0F);
	500	}
	501
	502	char nxp_board_rev_string(void)
	503	{
	504	const char *rev = "A";
	505
	506	return (*rev + nxp_board_rev() - 1);
	507	}
	508	#endif