[J-u-boot.git] / arch / arm / imx-common / cpu.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bootm.h>
#include <common.h>
#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>

#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
static u32 reset_cause = -1;

static char *get_reset_cause(void)
{
	u32 cause;
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;

	cause = readl(&src_regs->srsr);
	writel(cause, &src_regs->srsr);
	reset_cause = cause;

	switch (cause) {
	case 0x00001:
	case 0x00011:
		return "POR";
	case 0x00004:
		return "CSU";
	case 0x00008:
		return "IPP USER";
	case 0x00010:
		return "WDOG";
	case 0x00020:
		return "JTAG HIGH-Z";
	case 0x00040:
		return "JTAG SW";
	case 0x10000:
		return "WARM BOOT";
	default:
		return "unknown reset";
	}
}

u32 get_imx_reset_cause(void)
{
	return reset_cause;
}
#endif

#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE	ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE	MMDC_P0_BASE_ADDR
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};

/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
	uint32_t	ctl;
	uint32_t	pdc;
	uint32_t	otc;
	uint32_t	cfg0;
	uint32_t	cfg1;
	uint32_t	cfg2;
	uint32_t	misc;
};

#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)

/*
 * imx_ddr_size - return size in bytes of DRAM according MMDC config
 * The MMDC MDCTL register holds the number of bits for row, col, and data
 * width and the MMDC MDMISC register holds the number of banks. Combine
 * all these bits to determine the meme size the MMDC has been configured for
 */
unsigned imx_ddr_size(void)
{
	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
	unsigned ctl = readl(&mem->ctl);
	unsigned misc = readl(&mem->misc);
	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */

	bits += ESD_MMDC_CTL_GET_ROW(ctl);
	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
	bits += ESD_MMDC_CTL_GET_CS1(ctl);

	/* The MX6 can do only 3840 MiB of DRAM */
	if (bits == 32)
		return 0xf0000000;

	return 1 << bits;
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)

const char *get_imx_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_MX6QP:
		return "6QP";	/* Quad-Plus version of the mx6 */
	case MXC_CPU_MX6DP:
		return "6DP";	/* Dual-Plus version of the mx6 */
	case MXC_CPU_MX6Q:
		return "6Q";	/* Quad-core version of the mx6 */
	case MXC_CPU_MX6D:
		return "6D";	/* Dual-core version of the mx6 */
	case MXC_CPU_MX6DL:
		return "6DL";	/* Dual Lite version of the mx6 */
	case MXC_CPU_MX6SOLO:
		return "6SOLO";	/* Solo version of the mx6 */
	case MXC_CPU_MX6SL:
		return "6SL";	/* Solo-Lite version of the mx6 */
	case MXC_CPU_MX6SX:
		return "6SX";   /* SoloX version of the mx6 */
	case MXC_CPU_MX51:
		return "51";
	case MXC_CPU_MX53:
		return "53";
	default:
		return "??";
	}
}

int print_cpuinfo(void)
{
	u32 cpurev;
	__maybe_unused u32 max_freq;

#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
	struct udevice *thermal_dev;
	int cpu_tmp, minc, maxc, ret;
#endif

	cpurev = get_cpu_rev();

#if defined(CONFIG_MX6)
	printf("CPU:   Freescale i.MX%s rev%d.%d",
	       get_imx_type((cpurev & 0xFF000) >> 12),
	       (cpurev & 0x000F0) >> 4,
	       (cpurev & 0x0000F) >> 0);
	max_freq = get_cpu_speed_grade_hz();
	if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
		printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	} else {
		printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
	}
#else
	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
		get_imx_type((cpurev & 0xFF000) >> 12),
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif

#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
	puts("CPU:   ");
	switch (get_cpu_temp_grade(&minc, &maxc)) {
	case TEMP_AUTOMOTIVE:
		puts("Automotive temperature grade ");
		break;
	case TEMP_INDUSTRIAL:
		puts("Industrial temperature grade ");
		break;
	case TEMP_EXTCOMMERCIAL:
		puts("Extended Commercial temperature grade ");
		break;
	default:
		puts("Commercial temperature grade ");
		break;
	}
	printf("(%dC to %dC)", minc, maxc);
	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	if (!ret) {
		ret = thermal_get_temp(thermal_dev, &cpu_tmp);

		if (!ret)
			printf(" at %dC\n", cpu_tmp);
		else
			puts(" - invalid sensor data\n");
	} else {
		puts(" - invalid sensor device\n");
	}
#endif

	printf("Reset cause: %s\n", get_reset_cause());
	return 0;
}
#endif

int cpu_eth_init(bd_t *bis)
{
	int rc = -ENODEV;

#if defined(CONFIG_FEC_MXC)
	rc = fecmxc_initialize(bis);
#endif

	return rc;
}

#ifdef CONFIG_FSL_ESDHC
/*
 * Initializes on-chip MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(bd_t *bis)
{
	return fsl_esdhc_mmc_init(bis);
}
#endif

u32 get_ahb_clk(void)
{
	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, ahb_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;

	return get_periph_clk() / (ahb_podf + 1);
}

void arch_preboot_os(void)
{
#if defined(CONFIG_CMD_SATA)
	sata_stop();
#if defined(CONFIG_MX6)
	disable_sata_clock();
#endif
#endif
#if defined(CONFIG_VIDEO_IPUV3)
	/* disable video before launching O/S */
	ipuv3_fb_shutdown();
#endif
}

void set_chipselect_size(int const cs_size)
{
	unsigned int reg;
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	reg = readl(&iomuxc_regs->gpr[1]);

	switch (cs_size) {
	case CS0_128:
		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
		reg |= 0x5;
		break;
	case CS0_64M_CS1_64M:
		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
		reg |= 0x1B;
		break;
	case CS0_64M_CS1_32M_CS2_32M:
		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
		reg |= 0x4B;
		break;
	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
		reg |= 0x249;
		break;
	default:
		printf("Unknown chip select size: %d\n", cs_size);
		break;
	}

	writel(reg, &iomuxc_regs->gpr[1]);
}
Commit	Line	Data
18936ee2 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
18936ee2 JL	8	*/
18936ee2 JL	9
5624c6bd	10	#include <bootm.h>
18936ee2	11	#include <common.h>
5624c6bd	12	#include <netdev.h>
18936ee2 JL	13	#include <asm/errno.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/sys_proto.h>
6a376046	18	#include <asm/arch/crm_regs.h>
70caa8e2	19	#include <imx_thermal.h>
e1eb75b5	20	#include <ipu_pixfmt.h>
7a264168	21	#include <thermal.h>
44b9841d	22	#include <sata.h>
18936ee2 JL	23
	24	#ifdef CONFIG_FSL_ESDHC
	25	#include <fsl_esdhc.h>
	26	#endif
	27
28420e78	28	#if defined(CONFIG_DISPLAY_CPUINFO)
11c2e505 EN	29	static u32 reset_cause = -1;
	30
	31	static char *get_reset_cause(void)
18936ee2 JL	32	{
	33	u32 cause;
	34	struct src src_regs = (struct src )SRC_BASE_ADDR;
	35
	36	cause = readl(&src_regs->srsr);
	37	writel(cause, &src_regs->srsr);
11c2e505	38	reset_cause = cause;
18936ee2 JL	39
	40	switch (cause) {
	41	case 0x00001:
cece2622	42	case 0x00011:
18936ee2 JL	43	return "POR";
	44	case 0x00004:
	45	return "CSU";
	46	case 0x00008:
	47	return "IPP USER";
	48	case 0x00010:
	49	return "WDOG";
	50	case 0x00020:
	51	return "JTAG HIGH-Z";
	52	case 0x00040:
	53	return "JTAG SW";
	54	case 0x10000:
	55	return "WARM BOOT";
	56	default:
	57	return "unknown reset";
	58	}
	59	}
	60
11c2e505 EN	61	u32 get_imx_reset_cause(void)
	62	{
	63	return reset_cause;
	64	}
28420e78	65	#endif
11c2e505	66
eb0344d9 TK	67	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
eb0344d9 TK	68	#if defined(CONFIG_MX53)
3e9cbbbb	69	#define MEMCTL_BASE ESDCTL_BASE_ADDR
eb0344d9	70	#else
3e9cbbbb	71	#define MEMCTL_BASE MMDC_P0_BASE_ADDR
eb0344d9 TK	72	#endif
	73	static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
	74	static const unsigned char bank_lookup[] = {3, 2};
	75
b07161c3	76	/* these MMDC registers are common to the IMX53 and IMX6 */
eb0344d9 TK	77	struct esd_mmdc_regs {
	78	uint32_t ctl;
	79	uint32_t pdc;
	80	uint32_t otc;
	81	uint32_t cfg0;
	82	uint32_t cfg1;
	83	uint32_t cfg2;
	84	uint32_t misc;
eb0344d9 TK	85	};
	86
	87	#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
	88	#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
	89	#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
	90	#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
	91	#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
	92
b07161c3 TH	93	/*
	94	* imx_ddr_size - return size in bytes of DRAM according MMDC config
	95	* The MMDC MDCTL register holds the number of bits for row, col, and data
	96	* width and the MMDC MDMISC register holds the number of banks. Combine
	97	* all these bits to determine the meme size the MMDC has been configured for
	98	*/
eb0344d9 TK	99	unsigned imx_ddr_size(void)
	100	{
	101	struct esd_mmdc_regs mem = (struct esd_mmdc_regs )MEMCTL_BASE;
	102	unsigned ctl = readl(&mem->ctl);
	103	unsigned misc = readl(&mem->misc);
	104	int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
	105
	106	bits += ESD_MMDC_CTL_GET_ROW(ctl);
	107	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
	108	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
	109	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
	110	bits += ESD_MMDC_CTL_GET_CS1(ctl);
fcfdfdd5 MV	111
	112	/* The MX6 can do only 3840 MiB of DRAM */
	113	if (bits == 32)
	114	return 0xf0000000;
	115
eb0344d9 TK	116	return 1 << bits;
	117	}
	118	#endif
	119
18936ee2	120	#if defined(CONFIG_DISPLAY_CPUINFO)
a7683867	121
20332a06	122	const char *get_imx_type(u32 imxtype)
a7683867 FE	123	{
a7683867 FE	124	switch (imxtype) {
d0acd993 PF	125	case MXC_CPU_MX6QP:
	126	return "6QP"; /* Quad-Plus version of the mx6 */
	127	case MXC_CPU_MX6DP:
	128	return "6DP"; /* Dual-Plus version of the mx6 */
20332a06	129	case MXC_CPU_MX6Q:
a7683867	130	return "6Q"; /* Quad-core version of the mx6 */
94db6655 FE	131	case MXC_CPU_MX6D:
94db6655 FE	132	return "6D"; /* Dual-core version of the mx6 */
20332a06 TK	133	case MXC_CPU_MX6DL:
	134	return "6DL"; /* Dual Lite version of the mx6 */
	135	case MXC_CPU_MX6SOLO:
	136	return "6SOLO"; /* Solo version of the mx6 */
	137	case MXC_CPU_MX6SL:
a7683867	138	return "6SL"; /* Solo-Lite version of the mx6 */
05d54b82 FE	139	case MXC_CPU_MX6SX:
05d54b82 FE	140	return "6SX"; /* SoloX version of the mx6 */
20332a06	141	case MXC_CPU_MX51:
a7683867	142	return "51";
20332a06	143	case MXC_CPU_MX53:
a7683867 FE	144	return "53";
a7683867 FE	145	default:
e972d72b	146	return "??";
a7683867 FE	147	}
	148	}
	149
18936ee2 JL	150	int print_cpuinfo(void)
18936ee2 JL	151	{
943a3f2c SB	152	u32 cpurev;
943a3f2c SB	153	__maybe_unused u32 max_freq;
18936ee2	154
7a264168 YL	155	#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
7a264168 YL	156	struct udevice *thermal_dev;
70caa8e2	157	int cpu_tmp, minc, maxc, ret;
7a264168 YL	158	#endif
7a264168 YL	159
18936ee2	160	cpurev = get_cpu_rev();
a7683867	161
b83ddac8 TH	162	#if defined(CONFIG_MX6)
	163	printf("CPU: Freescale i.MX%s rev%d.%d",
	164	get_imx_type((cpurev & 0xFF000) >> 12),
	165	(cpurev & 0x000F0) >> 4,
	166	(cpurev & 0x0000F) >> 0);
	167	max_freq = get_cpu_speed_grade_hz();
	168	if (!max_freq \|\| max_freq == mxc_get_clock(MXC_ARM_CLK)) {
	169	printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	170	} else {
	171	printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
	172	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	173	}
	174	#else
a7683867 FE	175	printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
a7683867 FE	176	get_imx_type((cpurev & 0xFF000) >> 12),
18936ee2 JL	177	(cpurev & 0x000F0) >> 4,
	178	(cpurev & 0x0000F) >> 0,
	179	mxc_get_clock(MXC_ARM_CLK) / 1000000);
b83ddac8	180	#endif
7a264168 YL	181
7a264168 YL	182	#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
70caa8e2 TH	183	puts("CPU: ");
	184	switch (get_cpu_temp_grade(&minc, &maxc)) {
	185	case TEMP_AUTOMOTIVE:
	186	puts("Automotive temperature grade ");
	187	break;
	188	case TEMP_INDUSTRIAL:
	189	puts("Industrial temperature grade ");
	190	break;
	191	case TEMP_EXTCOMMERCIAL:
	192	puts("Extended Commercial temperature grade ");
	193	break;
	194	default:
	195	puts("Commercial temperature grade ");
	196	break;
	197	}
	198	printf("(%dC to %dC)", minc, maxc);
7a264168 YL	199	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	200	if (!ret) {
	201	ret = thermal_get_temp(thermal_dev, &cpu_tmp);
	202
	203	if (!ret)
70caa8e2	204	printf(" at %dC\n", cpu_tmp);
7a264168	205	else
70caa8e2	206	puts(" - invalid sensor data\n");
7a264168	207	} else {
70caa8e2	208	puts(" - invalid sensor device\n");
7a264168 YL	209	}
	210	#endif
	211
18936ee2 JL	212	printf("Reset cause: %s\n", get_reset_cause());
	213	return 0;
	214	}
	215	#endif
	216
	217	int cpu_eth_init(bd_t *bis)
	218	{
	219	int rc = -ENODEV;
	220
	221	#if defined(CONFIG_FEC_MXC)
	222	rc = fecmxc_initialize(bis);
	223	#endif
	224
	225	return rc;
	226	}
	227
ecb0f317	228	#ifdef CONFIG_FSL_ESDHC
18936ee2 JL	229	/*
	230	* Initializes on-chip MMC controllers.
	231	* to override, implement board_mmc_init()
	232	*/
	233	int cpu_mmc_init(bd_t *bis)
	234	{
18936ee2	235	return fsl_esdhc_mmc_init(bis);
18936ee2	236	}
ecb0f317	237	#endif
18936ee2	238
6a376046 FE	239	u32 get_ahb_clk(void)
	240	{
	241	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	242	u32 reg, ahb_podf;
	243
	244	reg = __raw_readl(&imx_ccm->cbcdr);
	245	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	246	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
	247
	248	return get_periph_clk() / (ahb_podf + 1);
	249	}
e1eb75b5	250
e1eb75b5 EN	251	void arch_preboot_os(void)
e1eb75b5 EN	252	{
44b9841d NK	253	#if defined(CONFIG_CMD_SATA)
44b9841d NK	254	sata_stop();
dd1c8f1b SM	255	#if defined(CONFIG_MX6)
	256	disable_sata_clock();
	257	#endif
44b9841d NK	258	#endif
44b9841d NK	259	#if defined(CONFIG_VIDEO_IPUV3)
e1eb75b5 EN	260	/* disable video before launching O/S */
e1eb75b5 EN	261	ipuv3_fb_shutdown();
e1eb75b5	262	#endif
44b9841d	263	}
32c81ea6 FE	264
	265	void set_chipselect_size(int const cs_size)
	266	{
	267	unsigned int reg;
	268	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	269	reg = readl(&iomuxc_regs->gpr[1]);
	270
	271	switch (cs_size) {
	272	case CS0_128:
	273	reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
	274	reg \|= 0x5;
	275	break;
	276	case CS0_64M_CS1_64M:
	277	reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
	278	reg \|= 0x1B;
	279	break;
	280	case CS0_64M_CS1_32M_CS2_32M:
	281	reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
	282	reg \|= 0x4B;
	283	break;
	284	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
	285	reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
	286	reg \|= 0x249;
	287	break;
	288	default:
	289	printf("Unknown chip select size: %d\n", cs_size);
	290	break;
	291	}
	292
	293	writel(reg, &iomuxc_regs->gpr[1]);
	294	}