[J-u-boot.git] / include / phy.h

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>

#define PHY_FIXED_ID		0xa5a55a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


typedef enum {
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_SGMII_2500,
	PHY_INTERFACE_MODE_QSGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_RGMII,
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_XAUI,
	PHY_INTERFACE_MODE_RXAUI,
	PHY_INTERFACE_MODE_SFI,
	PHY_INTERFACE_MODE_NONE,	/* Must be last */

	PHY_INTERFACE_MODE_COUNT,
} phy_interface_t;

static const char *phy_interface_strings[] = {
	[PHY_INTERFACE_MODE_MII]		= "mii",
	[PHY_INTERFACE_MODE_GMII]		= "gmii",
	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
	[PHY_INTERFACE_MODE_SGMII_2500]		= "sgmii-2500",
	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
	[PHY_INTERFACE_MODE_TBI]		= "tbi",
	[PHY_INTERFACE_MODE_RMII]		= "rmii",
	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
	[PHY_INTERFACE_MODE_SFI]		= "sfi",
	[PHY_INTERFACE_MODE_NONE]		= "",
};

static inline const char *phy_string_for_interface(phy_interface_t i)
{
	/* Default to unknown */
	if (i > PHY_INTERFACE_MODE_NONE)
		i = PHY_INTERFACE_MODE_NONE;

	return phy_interface_strings[i];
}


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);
	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  0x13e51002
#define PHY_UID_TN2020	0x00a19410

#endif
Commit	Line	Data
5f184715 AF	1	/*
5f184715 AF	2	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	3	* Andy Fleming <[email protected]>
5f184715	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5f184715 AF	6	*
	7	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	8	*/
	9
	10	#ifndef _PHY_H
	11	#define _PHY_H
	12
	13	#include <linux/list.h>
	14	#include <linux/mii.h>
	15	#include <linux/ethtool.h>
	16	#include <linux/mdio.h>
	17
db40c1aa HS	18	#define PHY_FIXED_ID 0xa5a55a5a
db40c1aa HS	19
5f184715 AF	20	#define PHY_MAX_ADDR 32
5f184715 AF	21
ddcd1f30 SX	22	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	23
4dae610b	24	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	25	SUPPORTED_TP \| \
	26	SUPPORTED_MII)
	27
4dae610b FF	28	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	29	SUPPORTED_10baseT_Full)
	30
	31	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	32	SUPPORTED_100baseT_Full)
	33
	34	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	35	SUPPORTED_1000baseT_Full)
5f184715 AF	36
4dae610b FF	37	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	38	PHY_100BT_FEATURES \| \
	39	PHY_DEFAULT_FEATURES)
	40
	41	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	42	PHY_1000BT_FEATURES)
	43
5f184715 AF	44	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	45	SUPPORTED_10000baseT_Full)
	46
4fb3f0c8	47	#ifndef PHY_ANEG_TIMEOUT
5f184715	48	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	49	#endif
5f184715 AF	50
	51
	52	typedef enum {
	53	PHY_INTERFACE_MODE_MII,
	54	PHY_INTERFACE_MODE_GMII,
	55	PHY_INTERFACE_MODE_SGMII,
c35f8693	56	PHY_INTERFACE_MODE_SGMII_2500,
7794b1a7	57	PHY_INTERFACE_MODE_QSGMII,
5f184715 AF	58	PHY_INTERFACE_MODE_TBI,
	59	PHY_INTERFACE_MODE_RMII,
	60	PHY_INTERFACE_MODE_RGMII,
	61	PHY_INTERFACE_MODE_RGMII_ID,
	62	PHY_INTERFACE_MODE_RGMII_RXID,
	63	PHY_INTERFACE_MODE_RGMII_TXID,
	64	PHY_INTERFACE_MODE_RTBI,
	65	PHY_INTERFACE_MODE_XGMII,
d11e9347 SR	66	PHY_INTERFACE_MODE_XAUI,
	67	PHY_INTERFACE_MODE_RXAUI,
	68	PHY_INTERFACE_MODE_SFI,
c74c8e66 SG	69	PHY_INTERFACE_MODE_NONE, /* Must be last */
	70
	71	PHY_INTERFACE_MODE_COUNT,
5f184715 AF	72	} phy_interface_t;
	73
	74	static const char *phy_interface_strings[] = {
	75	[PHY_INTERFACE_MODE_MII] = "mii",
	76	[PHY_INTERFACE_MODE_GMII] = "gmii",
	77	[PHY_INTERFACE_MODE_SGMII] = "sgmii",
c35f8693	78	[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
7794b1a7	79	[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
5f184715 AF	80	[PHY_INTERFACE_MODE_TBI] = "tbi",
	81	[PHY_INTERFACE_MODE_RMII] = "rmii",
	82	[PHY_INTERFACE_MODE_RGMII] = "rgmii",
	83	[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
	84	[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
	85	[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
	86	[PHY_INTERFACE_MODE_RTBI] = "rtbi",
	87	[PHY_INTERFACE_MODE_XGMII] = "xgmii",
d11e9347 SR	88	[PHY_INTERFACE_MODE_XAUI] = "xaui",
	89	[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
	90	[PHY_INTERFACE_MODE_SFI] = "sfi",
5f184715 AF	91	[PHY_INTERFACE_MODE_NONE] = "",
	92	};
	93
	94	static inline const char *phy_string_for_interface(phy_interface_t i)
	95	{
	96	/* Default to unknown */
	97	if (i > PHY_INTERFACE_MODE_NONE)
	98	i = PHY_INTERFACE_MODE_NONE;
	99
	100	return phy_interface_strings[i];
	101	}
	102
	103
	104	struct phy_device;
	105
	106	#define MDIO_NAME_LEN 32
	107
	108	struct mii_dev {
	109	struct list_head link;
	110	char name[MDIO_NAME_LEN];
	111	void *priv;
	112	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	113	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	114	u16 val);
	115	int (reset)(struct mii_dev bus);
	116	struct phy_device *phymap[PHY_MAX_ADDR];
	117	u32 phy_mask;
	118	};
	119
	120	/* struct phy_driver: a structure which defines PHY behavior
	121	*
	122	* uid will contain a number which represents the PHY. During
	123	* startup, the driver will poll the PHY to find out what its
	124	* UID--as defined by registers 2 and 3--is. The 32-bit result
	125	* gotten from the PHY will be masked to
	126	* discard any bits which may change based on revision numbers
	127	* unimportant to functionality
	128	*
	129	*/
	130	struct phy_driver {
	131	char *name;
	132	unsigned int uid;
	133	unsigned int mask;
	134	unsigned int mmds;
	135
	136	u32 features;
	137
	138	/* Called to do any driver startup necessities */
	139	/* Will be called during phy_connect */
	140	int (probe)(struct phy_device phydev);
	141
	142	/* Called to configure the PHY, and modify the controller
	143	* based on the results. Should be called after phy_connect */
	144	int (config)(struct phy_device phydev);
	145
	146	/* Called when starting up the controller */
	147	int (startup)(struct phy_device phydev);
	148
	149	/* Called when bringing down the controller */
	150	int (shutdown)(struct phy_device phydev);
	151
b71841b9 SB	152	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	153	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	154	u16 val);
5f184715 AF	155	struct list_head list;
	156	};
	157
	158	struct phy_device {
	159	/* Information about the PHY type */
	160	/* And management functions */
	161	struct mii_dev *bus;
	162	struct phy_driver *drv;
	163	void *priv;
	164
c74c8e66 SG	165	#ifdef CONFIG_DM_ETH
	166	struct udevice *dev;
	167	#else
5f184715	168	struct eth_device *dev;
c74c8e66	169	#endif
5f184715 AF	170
	171	/* forced speed & duplex (no autoneg)
	172	* partner speed & duplex & pause (autoneg)
	173	*/
	174	int speed;
	175	int duplex;
	176
	177	/* The most recently read link state */
	178	int link;
	179	int port;
	180	phy_interface_t interface;
	181
	182	u32 advertising;
	183	u32 supported;
	184	u32 mmds;
	185
	186	int autoneg;
	187	int addr;
	188	int pause;
	189	int asym_pause;
	190	u32 phy_id;
	191	u32 flags;
	192	};
	193
f55a776c SX	194	struct fixed_link {
	195	int phy_id;
	196	int duplex;
	197	int link_speed;
	198	int pause;
	199	int asym_pause;
	200	};
	201
5f184715 AF	202	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	203	{
	204	struct mii_dev *bus = phydev->bus;
	205
	206	return bus->read(bus, phydev->addr, devad, regnum);
	207	}
	208
	209	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	210	u16 val)
	211	{
	212	struct mii_dev *bus = phydev->bus;
	213
	214	return bus->write(bus, phydev->addr, devad, regnum, val);
	215	}
	216
	217	#ifdef CONFIG_PHYLIB_10G
	218	extern struct phy_driver gen10g_driver;
	219
	220	/* For now, XGMII is the only 10G interface */
	221	static inline int is_10g_interface(phy_interface_t interface)
	222	{
	223	return interface == PHY_INTERFACE_MODE_XGMII;
	224	}
	225
	226	#endif
	227
	228	int phy_init(void);
	229	int phy_reset(struct phy_device *phydev);
1adb406b TK	230	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	231	phy_interface_t interface);
c74c8e66 SG	232	#ifdef CONFIG_DM_ETH
	233	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
	234	struct phy_device phy_connect(struct mii_dev bus, int addr,
	235	struct udevice *dev,
	236	phy_interface_t interface);
	237	#else
1adb406b	238	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
5f184715 AF	239	struct phy_device phy_connect(struct mii_dev bus, int addr,
	240	struct eth_device *dev,
	241	phy_interface_t interface);
c74c8e66	242	#endif
5f184715 AF	243	int phy_startup(struct phy_device *phydev);
	244	int phy_config(struct phy_device *phydev);
	245	int phy_shutdown(struct phy_device *phydev);
	246	int phy_register(struct phy_driver *drv);
b18acb0a	247	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	248	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	249	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	250	int genphy_update_link(struct phy_device *phydev);
e2043f5c	251	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	252	int genphy_config(struct phy_device *phydev);
	253	int genphy_startup(struct phy_device *phydev);
	254	int genphy_shutdown(struct phy_device *phydev);
	255	int gen10g_config(struct phy_device *phydev);
	256	int gen10g_startup(struct phy_device *phydev);
	257	int gen10g_shutdown(struct phy_device *phydev);
	258	int gen10g_discover_mmds(struct phy_device *phydev);
	259
24ae3961	260	int phy_mv88e61xx_init(void);
f7c38cf8	261	int phy_aquantia_init(void);
9082eeac AF	262	int phy_atheros_init(void);
9082eeac AF	263	int phy_broadcom_init(void);
9b18e519	264	int phy_cortina_init(void);
9082eeac	265	int phy_davicom_init(void);
f485c8a3	266	int phy_et1011c_init(void);
9082eeac AF	267	int phy_lxt_init(void);
9082eeac AF	268	int phy_marvell_init(void);
d397f7c4 AG	269	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	270	int phy_micrel_ksz90x1_init(void);
9082eeac AF	271	int phy_natsemi_init(void);
9082eeac AF	272	int phy_realtek_init(void);
b6abf555	273	int phy_smsc_init(void);
9082eeac	274	int phy_teranetics_init(void);
721aed79	275	int phy_ti_init(void);
9082eeac	276	int phy_vitesse_init(void);
ed6fad3e	277	int phy_xilinx_init(void);
a5fd13ad	278	int phy_mscc_init(void);
db40c1aa	279	int phy_fixed_init(void);
a836626c	280
2fb63964	281	int board_phy_config(struct phy_device *phydev);
5707d5ff	282	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	283
c74c8e66 SG	284	/**
	285	* phy_get_interface_by_name() - Look up a PHY interface name
	286	*
	287	* @str: PHY interface name, e.g. "mii"
	288	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	289	*/
	290	int phy_get_interface_by_name(const char *str);
	291
3ab72fe8 DM	292	/**
	293	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	294	* is RGMII (all variants)
	295	* @phydev: the phy_device struct
	296	*/
	297	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	298	{
	299	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	300	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	301	}
	302
3c221af3 DM	303	/**
	304	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	305	* is SGMII (all variants)
	306	* @phydev: the phy_device struct
	307	*/
	308	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	309	{
	310	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	311	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	312	}
	313
a836626c	314	/* PHY UIDs for various PHYs that are referenced in external code */
9b18e519	315	#define PHY_UID_CS4340 0x13e51002
a836626c TT	316	#define PHY_UID_TN2020 0x00a19410
a836626c TT	317
5f184715	318	#endif