[J-u-boot.git] / include / configs / CPC45.h

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the CPC45 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_CPC45		1


#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#define CONFIG_BOOTDELAY	5

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_BEDBUG  | \
				CFG_CMD_DHCP	| \
				CFG_CMD_PCI	| \
				0 /* CFG_CMD_DATE */	)

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 */
#include <cmd_confdefs.h>


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

/* Print Buffer Size
 */
#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)

#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */

#define CFG_SDRAM_BASE	    0x00000000

#if defined(CONFIG_BOOT_ROM)
#define CFG_FLASH_BASE	    0xFF000000
#else
#define CFG_FLASH_BASE	    0xFF800000
#endif

#define CFG_RESET_ADDRESS   0xFFF00100

#define CFG_EUMB_ADDR	    0xFCE00000

#define CFG_MONITOR_BASE    TEXT_BASE

#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CFG_MAX_RAM_SIZE    0x10000000


#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

	/* Size in bytes reserved for initial data
	 */
#define CFG_GBL_DATA_SIZE    128

#define CFG_INIT_RAM_ADDR     0x40000000
#define CFG_INIT_RAM_END      0x1000
#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CFG_NS16550		
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
#define	DUART_DCR		(CFG_EUMB_ADDR + 0x4511)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CFG_HZ		     1000
/*
 * SDRAM Configuration Settings
 * Please note: currently only 64 and 128 MB SDRAM size supported
 * set CFG_SDRAM_SIZE to 64 or 128
 * Memory configuration using SPD information stored on the SODIMMs
 * not yet supported.
 */
 
#define	CFG_SDRAM_SIZE    64		/* SDRAM size -- 64 or 128 MB supported */

	/* Bit-field values for MCCR1.
	 */
#define CFG_ROMNAL	    0
#define CFG_ROMFAL	    7

#if (CFG_SDRAM_SIZE == 64)			/* 64 MB */
#define CFG_BANK0_ROW	0			/* SDRAM bank 7-0 row address */
#elif (CFG_SDRAM_SIZE == 128)			/* 128 MB */
#define CFG_BANK0_ROW	2			/* SDRAM bank 7-0 row address */
#else
#  error "SDRAM size not supported"
#endif
#define CFG_BANK1_ROW	0	
#define CFG_BANK2_ROW	0
#define CFG_BANK3_ROW	0
#define CFG_BANK4_ROW	0
#define CFG_BANK5_ROW	0
#define CFG_BANK6_ROW	0
#define CFG_BANK7_ROW	0

	/* Bit-field values for MCCR2.
	 */
#define CFG_REFINT	    430	    /* Refresh interval			*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CFG_BSTOPRE	    192

	/* Bit-field values for MCCR3.
	 */
#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
#define CFG_RDLAT	    3	    /* Data latancy from read command	*/

	/* Bit-field values for MCCR4.
	 */
#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
#define CFG_ACTORW	    2
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM	    1
#define CFG_REGDIMM	    0

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START	    0x00000000
#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE    1
#define CFG_BANK1_START	    0x3ff00000
#define CFG_BANK1_END	    0x3fffffff
#define CFG_BANK1_ENABLE    0
#define CFG_BANK2_START	    0x3ff00000
#define CFG_BANK2_END	    0x3fffffff
#define CFG_BANK2_ENABLE    0
#define CFG_BANK3_START	    0x3ff00000
#define CFG_BANK3_END	    0x3fffffff
#define CFG_BANK3_ENABLE    0
#define CFG_BANK4_START	    0x3ff00000
#define CFG_BANK4_END	    0x3fffffff
#define CFG_BANK4_ENABLE    0
#define CFG_BANK5_START	    0x3ff00000
#define CFG_BANK5_END	    0x3fffffff
#define CFG_BANK5_ENABLE    0
#define CFG_BANK6_START	    0x3ff00000
#define CFG_BANK6_END	    0x3fffffff
#define CFG_BANK6_ENABLE    0
#define CFG_BANK7_START	    0x3ff00000
#define CFG_BANK7_END	    0x3fffffff
#define CFG_BANK7_ENABLE    0

#define CFG_ODCR	    0xff

#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CFG_DBAT0L  CFG_IBAT0L
#define CFG_DBAT0U  CFG_IBAT0U
#define CFG_DBAT1L  CFG_IBAT1L
#define CFG_DBAT1U  CFG_IBAT1U
#define CFG_DBAT2L  CFG_IBAT2L
#define CFG_DBAT2U  CFG_IBAT2U
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

	/* Warining: environment is not EMBEDDED in the ppcboot code.
	 * It's stored in flash separately.
	 */
#define CFG_ENV_IS_IN_FLASH	    1

#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7C0000)
#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/


#define	SRAM_BASE		0x80000000	/* SRAM base address 	*/
#define	SRAM_END		0x801FFFFF

/*---------------------------------------------------------------------*/
/* CPC45 Memory Map                                                    */
/*---------------------------------------------------------------------*/
#define	SRAM_BASE	0x80000000	/* SRAM base address            */
#define	ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
#define	ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
#define	BCSR_BASE	0x80600000	/* board control / status registers */
#define	DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
#define	PCMCIA_MEM_BASE	0x81000000	/* PCMCIA memory window base        */
#define	PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base            */


/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers                                      */
/*---------------------------------------------------------------------*/
#define	IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
#define	IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
#define	IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
#define	IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
#define	BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
#define	BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
#define	WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
#define	WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define	WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define	BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))

/* IRQ_ENA_1 bit definitions */
#define	I_ENA_1_IERA	0x80		/* INTA enable 			*/
#define	I_ENA_1_IERB	0x40		/* INTB enable			*/
#define	I_ENA_1_IERC	0x20		/* INTC enable			*/
#define	I_ENA_1_IERD	0x10		/* INTD enable			*/

/* IRQ_STAT_1 bit definitions */
#define	I_STAT_1_INTA	0x80		/* INTA status			*/
#define	I_STAT_1_INTB	0x40		/* INTB status			*/
#define	I_STAT_1_INTC	0x20		/* INTC status			*/
#define	I_STAT_1_INTD	0x10		/* INTD status			*/

/* IRQ_ENA_2 bit definitions */
#define	I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
#define	I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
#define	I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/ 
#define	I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
#define	I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
#define	I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
#define	I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
#define	I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/

/* IRQ_STAT_2 bit definitions */
#define	I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
#define	I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
#define	I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/ 
#define	I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
#define	I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/ 
#define	I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
#define	I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
#define	I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/

/* BOARD_CTRL bit definitions */
#define	USER_LEDS		2			/* 2 user LEDs	*/

#if (USER_LEDS == 4)
#define	B_CTRL_WRSE		0x80
#define	B_CTRL_KRSE		0x40
#define	B_CTRL_FWRE		0x20		/* Flash write enable		*/
#define	B_CTRL_FWPT		0x10		/* Flash write protect		*/
#define	B_CTRL_LED3		0x08		/* LED 3 control		*/
#define	B_CTRL_LED2		0x04		/* LED 2 control		*/
#define	B_CTRL_LED1		0x02		/* LED 1 control		*/
#define	B_CTRL_LED0		0x01		/* LED 0 control		*/
#else
#define	B_CTRL_WRSE		0x80
#define	B_CTRL_KRSE		0x40
#define	B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
#define	B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
#define	B_CTRL_LED1		0x08		/* LED 1 control		*/
#define	B_CTRL_LED0		0x04		/* LED 0 control		*/
#define	B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
#define	B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
#endif

/* BOARD_STAT bit definitions */
#define	B_STAT_WDGE		0x80
#define	B_STAT_WDGS		0x40
#define	B_STAT_WRST		0x20
#define	B_STAT_KRST		0x10
#define	B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
#define	B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
#define	B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
#define	B_STAT_CSW0		0x01		/* sitch bit 0 status		*/

/*---------------------------------------------------------------------*/
/* Display addresses                                                   */
/*---------------------------------------------------------------------*/
#define	DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
#define	DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
#define	DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram           */

#define	DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
#define	DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */

#define	DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */      
#define	DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */      
#define	DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
#define	DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */      
#define	DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */      
#define	DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
#define	DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */      
#define	DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */      


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#undef CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/

#define CONFIG_EEPRO100

#define PCI_ENET0_IOADDR	0x00104000
#define PCI_ENET0_MEMADDR	0x82000000
#define	PCI_PLX9030_MEMADDR	0x82100000
#endif	/* __CONFIG_H */
Commit	Line	Data
3bac3513 WD	1	/*
	2	* (C) Copyright 2001-2003
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the CPC45 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8245 1
	46	#define CONFIG_CPC45 1
	47
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
	51	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	52
	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	54
	55	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	56
	57	#define CONFIG_BOOTDELAY 5
	58
	59	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	60
	61	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	62	CFG_CMD_BEDBUG \| \
	63	CFG_CMD_DHCP \| \
	64	CFG_CMD_PCI \| \
65	0 /* CFG_CMD_DATE */ )
66
67	/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
68	*/
69	#include <cmd_confdefs.h>
70
71
72	/*
73	* Miscellaneous configurable options
74	*/
75	#define CFG_LONGHELP /* undef to save memory */
76	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
77	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
78
79	#if 1
80	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
81	#endif
82	#ifdef CFG_HUSH_PARSER
83	#define CFG_PROMPT_HUSH_PS2 "> "
84	#endif
85
86	/* Print Buffer Size
87	*/
88	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
89
90	#define CFG_MAXARGS 16 /* max number of command args */
91	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
92	#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
93
94	/*-----------------------------------------------------------------------
95	* Start addresses for the final memory configuration
96	* (Set up by the startup code)
97	* Please note that CFG_SDRAM_BASE _must_ start at 0
98	*/
99
100	#define CFG_SDRAM_BASE 0x00000000
101
102	#if defined(CONFIG_BOOT_ROM)
103	#define CFG_FLASH_BASE 0xFF000000
104	#else
105	#define CFG_FLASH_BASE 0xFF800000
106	#endif
107
108	#define CFG_RESET_ADDRESS 0xFFF00100
109
110	#define CFG_EUMB_ADDR 0xFCE00000
111
112	#define CFG_MONITOR_BASE TEXT_BASE
113
114	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
115	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
116
117	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
118	#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
119
120	/* Maximum amount of RAM.
121	*/
122	#define CFG_MAX_RAM_SIZE 0x10000000
123
124
125	#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
126	#undef CFG_RAMBOOT
127	#else
128	#define CFG_RAMBOOT
129	#endif
130
131
132	/*-----------------------------------------------------------------------
133	* Definitions for initial stack pointer and data area
134	*/
135
136	/* Size in bytes reserved for initial data
137	*/
138	#define CFG_GBL_DATA_SIZE 128
139
140	#define CFG_INIT_RAM_ADDR 0x40000000
141	#define CFG_INIT_RAM_END 0x1000
142	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
143
144	/*
145	* NS16550 Configuration
146	*/
147	#define CFG_NS16550
148	#define CFG_NS16550_SERIAL
149
150	#define CFG_NS16550_REG_SIZE 1
151
152	#define CFG_NS16550_CLK get_bus_freq(0)
153
154	#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
155	#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
156	#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
157
158	/*
159	* Low Level Configuration Settings
160	* (address mappings, register initial values, etc.)
161	* You should know what you are doing if you make changes here.
162	* For the detail description refer to the MPC8240 user's manual.
163	*/
164
165	#define CONFIG_SYS_CLK_FREQ 33000000
166	#define CFG_HZ 1000
167	/*
168	* SDRAM Configuration Settings
169	* Please note: currently only 64 and 128 MB SDRAM size supported
170	* set CFG_SDRAM_SIZE to 64 or 128
171	* Memory configuration using SPD information stored on the SODIMMs
172	* not yet supported.
173	*/
174
175	#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
176
177	/* Bit-field values for MCCR1.
178	*/
179	#define CFG_ROMNAL 0
180	#define CFG_ROMFAL 7
181
182	#if (CFG_SDRAM_SIZE == 64) /* 64 MB */
183	#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
184	#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */
185	#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
186	#else
187	# error "SDRAM size not supported"
188	#endif
189	#define CFG_BANK1_ROW 0
190	#define CFG_BANK2_ROW 0
191	#define CFG_BANK3_ROW 0
192	#define CFG_BANK4_ROW 0
193	#define CFG_BANK5_ROW 0
194	#define CFG_BANK6_ROW 0
195	#define CFG_BANK7_ROW 0
196
197	/* Bit-field values for MCCR2.
198	*/
199	#define CFG_REFINT 430 /* Refresh interval */
200
201	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
202	*/
203	#define CFG_BSTOPRE 192
204
205	/* Bit-field values for MCCR3.
206	*/
207	#define CFG_REFREC 2 /* Refresh to activate interval */
208	#define CFG_RDLAT 3 /* Data latancy from read command */
209
210	/* Bit-field values for MCCR4.
211	*/
212	#define CFG_PRETOACT 2 /* Precharge to activate interval */
213	#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
214	#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
215	#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
216	#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
217	#define CFG_ACTORW 2
218	#define CFG_REGISTERD_TYPE_BUFFER 1
219	#define CFG_EXTROM 1
220	#define CFG_REGDIMM 0
221
222	/* Memory bank settings.
223	* Only bits 20-29 are actually used from these vales to set the
224	* start/end addresses. The upper two bits will always be 0, and the lower
225	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
226	* address. Refer to the MPC8240 book.
227	*/
228
229	#define CFG_BANK0_START 0x00000000
230	#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
231	#define CFG_BANK0_ENABLE 1
232	#define CFG_BANK1_START 0x3ff00000
233	#define CFG_BANK1_END 0x3fffffff
234	#define CFG_BANK1_ENABLE 0
235	#define CFG_BANK2_START 0x3ff00000
236	#define CFG_BANK2_END 0x3fffffff
237	#define CFG_BANK2_ENABLE 0
238	#define CFG_BANK3_START 0x3ff00000
239	#define CFG_BANK3_END 0x3fffffff
240	#define CFG_BANK3_ENABLE 0
241	#define CFG_BANK4_START 0x3ff00000
242	#define CFG_BANK4_END 0x3fffffff
243	#define CFG_BANK4_ENABLE 0
244	#define CFG_BANK5_START 0x3ff00000
245	#define CFG_BANK5_END 0x3fffffff
246	#define CFG_BANK5_ENABLE 0
247	#define CFG_BANK6_START 0x3ff00000
248	#define CFG_BANK6_END 0x3fffffff
249	#define CFG_BANK6_ENABLE 0
250	#define CFG_BANK7_START 0x3ff00000
251	#define CFG_BANK7_END 0x3fffffff
252	#define CFG_BANK7_ENABLE 0
253
254	#define CFG_ODCR 0xff
255
256	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
257	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
258
259	#define CFG_IBAT1L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
260	#define CFG_IBAT1U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
261
262	#define CFG_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
263	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
264
265	#define CFG_IBAT3L (0xFC000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
266	#define CFG_IBAT3U (0xFC000000 \| BATU_BL_64M \| BATU_VS \| BATU_VP)
267
268	#define CFG_DBAT0L CFG_IBAT0L
269	#define CFG_DBAT0U CFG_IBAT0U
270	#define CFG_DBAT1L CFG_IBAT1L
271	#define CFG_DBAT1U CFG_IBAT1U
272	#define CFG_DBAT2L CFG_IBAT2L
273	#define CFG_DBAT2U CFG_IBAT2U
274	#define CFG_DBAT3L CFG_IBAT3L
275	#define CFG_DBAT3U CFG_IBAT3U
276
277	/*
278	* For booting Linux, the board info and command line data
279	* have to be in the first 8 MB of memory, since this is
280	* the maximum mapped by the Linux kernel during initialization.
281	*/
282	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
283
284	/*-----------------------------------------------------------------------
285	* FLASH organization
286	*/
287	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
288	#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
289	#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
290	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
291	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
292
293	/* Warining: environment is not EMBEDDED in the ppcboot code.
294	* It's stored in flash separately.
295	*/
296	#define CFG_ENV_IS_IN_FLASH 1
297
298	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000)
299	#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
300	#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
301	#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
302
303	/*-----------------------------------------------------------------------
304	* Cache Configuration
305	*/
306	#define CFG_CACHELINE_SIZE 32
307	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
308	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
309	#endif
310
311	/*
312	* Internal Definitions
313	*
314	* Boot Flags
315	*/
316	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
317	#define BOOTFLAG_WARM 0x02 /* Software reboot */
318
319
320	#define SRAM_BASE 0x80000000 /* SRAM base address */
321	#define SRAM_END 0x801FFFFF
322
323	/---------------------------------------------------------------------/
324	/* CPC45 Memory Map */
325	/---------------------------------------------------------------------/
326	#define SRAM_BASE 0x80000000 /* SRAM base address */
327	#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
328	#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
329	#define BCSR_BASE 0x80600000 /* board control / status registers */
330	#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
331	#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
332	#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
333
334
335	/---------------------------------------------------------------------/
336	/* CPC45 Control/Status Registers */
337	/---------------------------------------------------------------------/
338	#define IRQ_ENA_1 ((volatile uchar)(BCSR_BASE + 0x00))
339	#define IRQ_STAT_1 ((volatile uchar)(BCSR_BASE + 0x01))
340	#define IRQ_ENA_2 ((volatile uchar)(BCSR_BASE + 0x02))
341	#define IRQ_STAT_2 ((volatile uchar)(BCSR_BASE + 0x03))
342	#define BOARD_CTRL ((volatile uchar)(BCSR_BASE + 0x04))
343	#define BOARD_STAT ((volatile uchar)(BCSR_BASE + 0x05))
344	#define WDG_START ((volatile uchar)(BCSR_BASE + 0x06))
345	#define WDG_PRESTOP ((volatile uchar)(BCSR_BASE + 0x06))
346	#define WDG_STOP ((volatile uchar)(BCSR_BASE + 0x06))
347	#define BOARD_REV ((volatile uchar)(BCSR_BASE + 0x07))
348
349	/* IRQ_ENA_1 bit definitions */
350	#define I_ENA_1_IERA 0x80 /* INTA enable */
351	#define I_ENA_1_IERB 0x40 /* INTB enable */
352	#define I_ENA_1_IERC 0x20 /* INTC enable */
353	#define I_ENA_1_IERD 0x10 /* INTD enable */
354
355	/* IRQ_STAT_1 bit definitions */
356	#define I_STAT_1_INTA 0x80 /* INTA status */
357	#define I_STAT_1_INTB 0x40 /* INTB status */
358	#define I_STAT_1_INTC 0x20 /* INTC status */
359	#define I_STAT_1_INTD 0x10 /* INTD status */
360
361	/* IRQ_ENA_2 bit definitions */
362	#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
363	#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
364	#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
365	#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
366	#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
367	#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
368	#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
369	#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
370
371	/* IRQ_STAT_2 bit definitions */
372	#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
373	#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
374	#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
375	#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
376	#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
377	#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
378	#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
379	#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
380
381	/* BOARD_CTRL bit definitions */
382	#define USER_LEDS 2 /* 2 user LEDs */
383
384	#if (USER_LEDS == 4)
385	#define B_CTRL_WRSE 0x80
386	#define B_CTRL_KRSE 0x40
387	#define B_CTRL_FWRE 0x20 /* Flash write enable */
388	#define B_CTRL_FWPT 0x10 /* Flash write protect */
389	#define B_CTRL_LED3 0x08 /* LED 3 control */
390	#define B_CTRL_LED2 0x04 /* LED 2 control */
391	#define B_CTRL_LED1 0x02 /* LED 1 control */
392	#define B_CTRL_LED0 0x01 /* LED 0 control */
393	#else
394	#define B_CTRL_WRSE 0x80
395	#define B_CTRL_KRSE 0x40
396	#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
397	#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
398	#define B_CTRL_LED1 0x08 /* LED 1 control */
399	#define B_CTRL_LED0 0x04 /* LED 0 control */
400	#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
401	#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
402	#endif
403
404	/* BOARD_STAT bit definitions */
405	#define B_STAT_WDGE 0x80
406	#define B_STAT_WDGS 0x40
407	#define B_STAT_WRST 0x20
408	#define B_STAT_KRST 0x10
409	#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
410	#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
411	#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
412	#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
413
414	/---------------------------------------------------------------------/
415	/* Display addresses */
416	/---------------------------------------------------------------------/
417	#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
418	#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
419	#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
420
421	#define DISP_UDC_ADR ((volatile uchar)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
422	#define DISP_CWORD ((volatile uchar)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
423
424	#define DISP_DIG0 ((volatile uchar)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
425	#define DISP_DIG1 ((volatile uchar)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
426	#define DISP_DIG2 ((volatile uchar)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
427	#define DISP_DIG3 ((volatile uchar)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
428	#define DISP_DIG4 ((volatile uchar)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
429	#define DISP_DIG5 ((volatile uchar)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
430	#define DISP_DIG6 ((volatile uchar)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
431	#define DISP_DIG7 ((volatile uchar)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
432
433
434	/*-----------------------------------------------------------------------
435	* PCI stuff
436	*-----------------------------------------------------------------------
437	*/
438	#define CONFIG_PCI /* include pci support */
439	#undef CONFIG_PCI_PNP
440
441	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
442
443	#define CONFIG_EEPRO100
444
445	#define PCI_ENET0_IOADDR 0x00104000
446	#define PCI_ENET0_MEMADDR 0x82000000
447	#define PCI_PLX9030_MEMADDR 0x82100000
448	#endif /* __CONFIG_H */