[J-u-boot.git] / include / configs / socfpga_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

#include <linux/stringify.h>

/*
 * Memory configurations
 */
#define PHYS_SDRAM_1			0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	SOCFPGA_PHYS_OCRAM_SIZE
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
#define CONFIG_SYS_INIT_RAM_SIZE	(SOCFPGA_PHYS_OCRAM_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE)
#endif

/*
 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
 * SRAM as bootcounter storage. Make sure to not put the stack directly
 * at this address to not overwrite the bootcounter by checking, if the
 * bootcounter address is located in the internal SRAM.
 */
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&	\
     (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +	\
				   CONFIG_SYS_INIT_RAM_SIZE)))
#endif

/*
 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
 * in U-Boot pre-reloc is higher than in SPL.
 */

#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/*
 * U-Boot general configurations
 */
						/* Print buffer size */

/*
 * Cache
 */
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * L4 OSC1 Timer 0
 */
#ifndef CONFIG_TIMER
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#ifndef CONFIG_SYS_TIMER_RATE
#define CONFIG_SYS_TIMER_RATE		25000000
#endif
#endif

/*
 * L4 Watchdog
 */
#define CONFIG_DW_WDT_CLOCK_KHZ		25000

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CFG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CFG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#endif

/*
 * USB
 */

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */

/* Environment for SDMMC boot */

/* Environment for QSPI boot */

/*
 * SPL
 *
 * SRAM Memory layout for gen 5:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Global Data
 * 0xFFFF_zzzz ...... Malloc area
 * 0xFFFF_FFFF ...... End of SRAM
 *
 * SRAM Memory layout for Arria 10:
 * 0xFFE0_0000 ...... Start of SRAM (bottom)
 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 * 0xFFEy_yyyy ...... Global Data
 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 * 0xFFE3_FFFF ...... End of SRAM (top)
 */

/* SPL QSPI boot support */

/* SPL NAND boot support */

/* Extra Environment */
#ifndef CONFIG_SPL_BUILD

#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif

#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif

#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif

#define BOOT_TARGET_DEVICES(func) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_PXE(func) \
	BOOT_TARGET_DEVICES_DHCP(func)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	"fdt_addr_r=0x02000000\0" \
	"scriptaddr=0x02100000\0" \
	"pxefile_addr_r=0x02200000\0" \
	"ramdisk_addr_r=0x02300000\0" \
	"socfpga_legacy_reset_compat=1\0" \
	BOOTENV

#endif
#endif

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5095ee08 PM	2	/*
5095ee08 PM	3	* Copyright (C) 2012 Altera Corporation <www.altera.com>
5095ee08	4	*/
48275c96 DN	5	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	6	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	7
1af3c7f4 SG	8	#include <linux/stringify.h>
1af3c7f4 SG	9
5095ee08 PM	10	/*
	11	* Memory configurations
	12	*/
5095ee08	13	#define PHYS_SDRAM_1 0x0
1b259403	14	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
5095ee08	15	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
4f17f296	16	#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
1b259403 LFT	17	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
1b259403 LFT	18	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
4399e48d	19	/* SPL memory allocation configuration, this is for FAT implementation */
4f17f296 LFT	20	#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
4f17f296 LFT	21	CONFIG_SYS_SPL_MALLOC_SIZE)
1b259403	22	#endif
f457c52e SR	23
	24	/*
	25	* Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
	26	* SRAM as bootcounter storage. Make sure to not put the stack directly
	27	* at this address to not overwrite the bootcounter by checking, if the
	28	* bootcounter address is located in the internal SRAM.
	29	*/
	30	#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
	31	(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
	32	CONFIG_SYS_INIT_RAM_SIZE)))
f457c52e	33	#endif
5095ee08	34
4399e48d SG	35	/*
	36	* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
	37	* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
	38	* in U-Boot pre-reloc is higher than in SPL.
	39	*/
4399e48d	40
aa6e94de	41	#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
5095ee08 PM	42
	43	/*
	44	* U-Boot general configurations
	45	*/
5095ee08	46	/* Print buffer size */
5095ee08 PM	47
	48	/*
	49	* Cache
	50	*/
5095ee08 PM	51	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
5095ee08 PM	52
5095ee08 PM	53	/*
	54	* L4 OSC1 Timer 0
	55	*/
331c3722	56	#ifndef CONFIG_TIMER
5095ee08	57	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
5095ee08	58	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
c808ab47	59	#ifndef CONFIG_SYS_TIMER_RATE
5095ee08	60	#define CONFIG_SYS_TIMER_RATE 25000000
331c3722	61	#endif
c808ab47	62	#endif
5095ee08 PM	63
	64	/*
	65	* L4 Watchdog
	66	*/
5095ee08	67	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
5095ee08	68
c339ea5b MV	69	/*
	70	* NAND Support
	71	*/
	72	#ifdef CONFIG_NAND_DENALI
4e590945 TR	73	#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
4e590945 TR	74	#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
c339ea5b MV	75	#endif
c339ea5b MV	76
20cadbbe MV	77	/*
	78	* USB
	79	*/
20cadbbe	80
0223a95c MV	81	/*
	82	* USB Gadget (DFU, UMS)
	83	*/
	84	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
0223a95c MV	85	#define DFU_DEFAULT_POLL_TIMEOUT 300
	86
	87	/* USB IDs */
e6c0bc06 SP	88	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	89	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	90	#endif
0223a95c MV	91
5095ee08 PM	92	/*
	93	* U-Boot environment
	94	*/
5095ee08	95
79cc48e7	96	/* Environment for SDMMC boot */
79cc48e7	97
ec8b7528	98	/* Environment for QSPI boot */
ec8b7528	99
5095ee08 PM	100	/*
5095ee08 PM	101	* SPL
34584d19	102	*
421a21c5	103	* SRAM Memory layout for gen 5:
34584d19 MV	104	*
	105	* 0xFFFF_0000 ...... Start of SRAM
	106	* 0xFFFF_xxxx ...... Top of stack (grows down)
798baf7c SG	107	* 0xFFFF_yyyy ...... Global Data
	108	* 0xFFFF_zzzz ...... Malloc area
	109	* 0xFFFF_FFFF ...... End of SRAM
421a21c5 TFC	110	*
	111	* SRAM Memory layout for Arria 10:
	112	* 0xFFE0_0000 ...... Start of SRAM (bottom)
	113	* 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
	114	* 0xFFEy_yyyy ...... Global Data
	115	* 0xFFEz_zzzz ...... Malloc area (grows up to top)
	116	* 0xFFE3_FFFF ...... End of SRAM (top)
5095ee08	117	*/
5095ee08	118
346d6f56	119	/* SPL QSPI boot support */
346d6f56	120
c339ea5b	121	/* SPL NAND boot support */
c339ea5b	122
451e8241 DW	123	/* Extra Environment */
451e8241 DW	124	#ifndef CONFIG_SPL_BUILD
451e8241	125
1c7fa793 SG	126	#ifdef CONFIG_CMD_DHCP
	127	#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
	128	#else
	129	#define BOOT_TARGET_DEVICES_DHCP(func)
	130	#endif
	131
86271b3f	132	#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
451e8241 DW	133	#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
	134	#else
	135	#define BOOT_TARGET_DEVICES_PXE(func)
	136	#endif
	137
	138	#ifdef CONFIG_CMD_MMC
	139	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
	140	#else
	141	#define BOOT_TARGET_DEVICES_MMC(func)
	142	#endif
	143
	144	#define BOOT_TARGET_DEVICES(func) \
	145	BOOT_TARGET_DEVICES_MMC(func) \
	146	BOOT_TARGET_DEVICES_PXE(func) \
1c7fa793	147	BOOT_TARGET_DEVICES_DHCP(func)
451e8241 DW	148
	149	#include <config_distro_bootcmd.h>
	150
	151	#ifndef CONFIG_EXTRA_ENV_SETTINGS
	152	#define CONFIG_EXTRA_ENV_SETTINGS \
	153	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	154	"bootm_size=0xa000000\0" \
	155	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	156	"fdt_addr_r=0x02000000\0" \
	157	"scriptaddr=0x02100000\0" \
	158	"pxefile_addr_r=0x02200000\0" \
	159	"ramdisk_addr_r=0x02300000\0" \
4b2e32ef	160	"socfpga_legacy_reset_compat=1\0" \
451e8241 DW	161	BOOTENV
	162
	163	#endif
	164	#endif
	165
48275c96	166	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */