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1/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <[email protected]>
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*------------------------------------------------------------------------
12 * BOARD/CPU
13 *----------------------------------------------------------------------*/
14#define CONFIG_PK1C20 1 /* PK1C20 board */
15#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
16
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17#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
18#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
19#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
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20#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
21
22/*------------------------------------------------------------------------
23 * CACHE -- the following will support II/s and II/f. The II/s does not
24 * have dcache, so the cache instructions will behave as NOPs.
25 *----------------------------------------------------------------------*/
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26#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
27#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
28#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
29#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
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30
31/*------------------------------------------------------------------------
32 * MEMORY BASE ADDRESSES
33 *----------------------------------------------------------------------*/
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34#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
35#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
36#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
37#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
38#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
39#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
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40
41/*------------------------------------------------------------------------
42 * MEMORY ORGANIZATION
43 * -Monitor at top.
44 * -The heap is placed below the monitor.
45 * -Global data is placed below the heap.
46 * -The stack is placed below global data (&grows down).
47 *----------------------------------------------------------------------*/
6d0f6bcf 48#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
6d0f6bcf 49#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
5c952cf0 50
14d0a02a 51#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 52#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
25ddd1fb 53#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 54#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
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55
56/*------------------------------------------------------------------------
57 * FLASH (AM29LV065D)
58 *----------------------------------------------------------------------*/
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59#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
60#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
61#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
62#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
63#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
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64
65/*------------------------------------------------------------------------
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66 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
67 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
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68 * reset address, no? This will keep the environment in user region
69 * of flash. NOTE: the monitor length must be multiple of sector size
70 * (which is common practice).
71 *----------------------------------------------------------------------*/
5a1aceb0 72#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
0e8d1586 73#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
5c952cf0 74#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
6d0f6bcf 75#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
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76
77/*------------------------------------------------------------------------
78 * CONSOLE
79 *----------------------------------------------------------------------*/
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80#define CONFIG_ALTERA_UART 1 /* Use altera uart */
81#if defined(CONFIG_ALTERA_JTAG_UART)
6d0f6bcf 82#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
5c952cf0 83#else
6d0f6bcf 84#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
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85#endif
86
6d0f6bcf 87#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
5c952cf0 88#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
6d0f6bcf 89#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
5c952cf0 90
6d0f6bcf 91#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
5c952cf0 92
0c1c117c 93/*------------------------------------------------------------------------
6d0f6bcf 94 * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
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95 * epcs device access is enabled. The base address is the epcs
96 * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
3d22d0b8 97 * The register base is currently at offset 0x600 from the memory base.
0c1c117c 98 *----------------------------------------------------------------------*/
6d0f6bcf 99#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
0c1c117c 100
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101/*------------------------------------------------------------------------
102 * DEBUG
103 *----------------------------------------------------------------------*/
104#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
105
106/*------------------------------------------------------------------------
107 * TIMEBASE --
108 *
109 * The high res timer defaults to 1 msec. Since it includes the period
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110 * registers, the interrupt frequency can be reduced using TMRCNT.
111 * If the default period is acceptable, TMRCNT can be left undefined.
112 * TMRMS represents the desired mecs per tick (msecs per interrupt).
5c952cf0 113 *----------------------------------------------------------------------*/
3a89a91a 114#define CONFIG_SYS_HZ 1000 /* Always 1000 */
e110c4fe 115#define CONFIG_SYS_LOW_RES_TIMER
6d0f6bcf 116#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
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117#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
118#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
119#define CONFIG_SYS_NIOS_TMRCNT \
120 (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
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121
122/*------------------------------------------------------------------------
123 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
124 * must implement its own led routines -- leds are, after all,
125 * board-specific, no?
126 *----------------------------------------------------------------------*/
6d0f6bcf 127#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
5c952cf0 128#define CONFIG_STATUS_LED /* Enable status driver */
db719642 129#define CONFIG_BOARD_SPECIFIC_LED
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130
131#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
132#define STATUS_LED_STATE 1 /* Blinking */
6d0f6bcf 133#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
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134
135/*------------------------------------------------------------------------
136 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
137 * and really doesn't need any additional clutter. So I choose the lazy
138 * way out to avoid changes there -- define the base address to ensure
139 * cache bypass so there's no need to monkey with inx/outx macros.
140 *----------------------------------------------------------------------*/
3d22d0b8 141#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
7194ab80 142#define CONFIG_SMC91111 /* Using SMC91c111 */
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143#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
144#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
145
146#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
147#define CONFIG_NETMASK 255.255.255.0
148#define CONFIG_IPADDR 192.168.2.21
149#define CONFIG_SERVERIP 192.168.2.16
150
acf02697 151
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152/*
153 * BOOTP options
154 */
155#define CONFIG_BOOTP_BOOTFILESIZE
156#define CONFIG_BOOTP_BOOTPATH
157#define CONFIG_BOOTP_GATEWAY
158#define CONFIG_BOOTP_HOSTNAME
159
160
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161/*
162 * Command line configuration.
163 */
164
165#define CONFIG_CMD_BDI
166#define CONFIG_CMD_DHCP
167#define CONFIG_CMD_ECHO
bdab39d3 168#define CONFIG_CMD_SAVEENV
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169#define CONFIG_CMD_FLASH
170#define CONFIG_CMD_IMI
171#define CONFIG_CMD_IRQ
172#define CONFIG_CMD_LOADS
173#define CONFIG_CMD_LOADB
174#define CONFIG_CMD_MEMORY
175#define CONFIG_CMD_MISC
176#define CONFIG_CMD_NET
177#define CONFIG_CMD_PING
178#define CONFIG_CMD_RUN
179#define CONFIG_CMD_SAVES
180
5c952cf0 181
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182/*------------------------------------------------------------------------
183 * COMPACT FLASH
184 *----------------------------------------------------------------------*/
acf02697 185#if defined(CONFIG_CMD_IDE)
0c1c117c 186#define CONFIG_IDE_PREINIT /* Implement id_preinit */
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187#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
188#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
189
190#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
191#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
192#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
193#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */
194#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
195#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */
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196#define CONFIG_DOS_PARTITION
197
198/* Board-specific cf regs */
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199#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */
200#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/
201#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
0c1c117c 202
acf02697 203#endif
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204
205/*------------------------------------------------------------------------
206 * JFFS2
207 *----------------------------------------------------------------------*/
acf02697 208#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf 209#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */
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210#endif
211
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212/*------------------------------------------------------------------------
213 * MISC
214 *----------------------------------------------------------------------*/
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215#define CONFIG_SYS_LONGHELP /* Provide extended help*/
216#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
217#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
218#define CONFIG_SYS_MAXARGS 16 /* Max command args */
219#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
220#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
221#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
222#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
223#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
224
225#define CONFIG_SYS_HUSH_PARSER
0c1c117c 226
5c952cf0 227#endif /* __CONFIG_H */
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