[J-u-boot.git] / include / configs / PK1C20.h

/*
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*------------------------------------------------------------------------
 * BOARD/CPU
 *----------------------------------------------------------------------*/
#define CONFIG_PK1C20		1		/* PK1C20 board		*/
#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/

#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * CACHE -- the following will support II/s and II/f. The II/s does not
 * have dcache, so the cache instructions will behave as NOPs.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/

/*------------------------------------------------------------------------
 * MEMORY BASE ADDRESSES
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION
 *	-Monitor at top.
 *	-The heap is placed below the monitor.
 *	-Global data is placed below the heap.
 *	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/

/*------------------------------------------------------------------------
 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
 * reset address, no? This will keep the environment in user region
 * of flash. NOTE: the monitor length must be multiple of sector size
 * (which is common practice).
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#define CONFIG_ALTERA_UART		1	/* Use altera uart */
#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
#else
#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
#endif

#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/

/*------------------------------------------------------------------------
 * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
 * epcs device access is enabled. The base address is the epcs
 * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
 * The register base is currently at offset 0x600 from the memory base.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/

/*------------------------------------------------------------------------
 * DEBUG
 *----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/

/*------------------------------------------------------------------------
 * TIMEBASE --
 *
 * The high res timer defaults to 1 msec. Since it includes the period
 * registers, we can slow it down to 10 msec using TMRCNT. If the default
 * period is acceptable, TMRCNT can be left undefined.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))

/*------------------------------------------------------------------------
 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
 * must implement its own led routines -- leds are, after all,
 * board-specific, no?
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
#define CONFIG_STATUS_LED			/* Enable status driver */

#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
#define STATUS_LED_STATE	1		/* Blinking		*/
#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/

/*------------------------------------------------------------------------
 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
 * and really doesn't need any additional clutter. So I choose the lazy
 * way out to avoid changes there -- define the base address to ensure
 * cache bypass so there's no need to monkey with inx/outx macros.
 *----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
#define CONFIG_NET_MULTI
#define CONFIG_SMC91111			/* Using SMC91c111	*/
#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/

#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.2.21
#define CONFIG_SERVERIP		192.168.2.16


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES


/*------------------------------------------------------------------------
 * COMPACT FLASH
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
#define CONFIG_SYS_IDE_MAXBUS		1		/* 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0040		/* Register offset	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
#define CONFIG_SYS_ATA_STRIDE          4		/* Width betwix addrs	*/
#define CONFIG_DOS_PARTITION

/* Board-specific cf regs */
#define CONFIG_SYS_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
#define CONFIG_SYS_CF_POWER		0x00900890	/* CF Power FET PIO base*/
#define CONFIG_SYS_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/

#endif

/*------------------------------------------------------------------------
 * JFFS2
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS_CUSTOM_PART			/* board defined part	*/
#endif

/*------------------------------------------------------------------------
 * MISC
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000

#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

#endif	/* __CONFIG_H */
Commit	Line	Data
5c952cf0 WD	1	/*
	2	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	3	* Scott McNutt <[email protected]>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*------------------------------------------------------------------------
	28	* BOARD/CPU
	29	----------------------------------------------------------------------/
	30	#define CONFIG_PK1C20 1 /* PK1C20 board */
	31	#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
	32
6d0f6bcf JCPV	33	#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
	34	#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
	35	#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
5c952cf0 WD	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
	37
	38	/*------------------------------------------------------------------------
	39	* CACHE -- the following will support II/s and II/f. The II/s does not
	40	* have dcache, so the cache instructions will behave as NOPs.
	41	----------------------------------------------------------------------/
6d0f6bcf JCPV	42	#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
	43	#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
	44	#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
	45	#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
5c952cf0 WD	46
	47	/*------------------------------------------------------------------------
	48	* MEMORY BASE ADDRESSES
	49	----------------------------------------------------------------------/
6d0f6bcf JCPV	50	#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
	51	#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
	52	#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
	53	#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
	54	#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
	55	#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
5c952cf0 WD	56
	57	/*------------------------------------------------------------------------
	58	* MEMORY ORGANIZATION
	59	* -Monitor at top.
	60	* -The heap is placed below the monitor.
	61	* -Global data is placed below the heap.
	62	* -The stack is placed below global data (&grows down).
	63	----------------------------------------------------------------------/
6d0f6bcf JCPV	64	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
	65	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
	66	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
5c952cf0	67
6d0f6bcf JCPV	68	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	69	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
	70	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
	71	#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
5c952cf0 WD	72
	73	/*------------------------------------------------------------------------
	74	* FLASH (AM29LV065D)
	75	----------------------------------------------------------------------/
6d0f6bcf JCPV	76	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
	77	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
	78	#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
	79	#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
	80	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
5c952cf0 WD	81
5c952cf0 WD	82	/*------------------------------------------------------------------------
6d0f6bcf JCPV	83	* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
6d0f6bcf JCPV	84	* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
5c952cf0 WD	85	* reset address, no? This will keep the environment in user region
	86	* of flash. NOTE: the monitor length must be multiple of sector size
	87	* (which is common practice).
	88	----------------------------------------------------------------------/
5a1aceb0	89	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
0e8d1586	90	#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
5c952cf0	91	#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
6d0f6bcf	92	#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
5c952cf0 WD	93
	94	/*------------------------------------------------------------------------
	95	* CONSOLE
	96	----------------------------------------------------------------------/
c9d4f46b SM	97	#define CONFIG_ALTERA_UART 1 /* Use altera uart */
c9d4f46b SM	98	#if defined(CONFIG_ALTERA_JTAG_UART)
6d0f6bcf	99	#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
5c952cf0	100	#else
6d0f6bcf	101	#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
5c952cf0 WD	102	#endif
5c952cf0 WD	103
6d0f6bcf	104	#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
5c952cf0	105	#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
6d0f6bcf	106	#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
5c952cf0	107
6d0f6bcf	108	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
5c952cf0	109
0c1c117c	110	/*------------------------------------------------------------------------
6d0f6bcf	111	* EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
0c1c117c WD	112	* epcs device access is enabled. The base address is the epcs
0c1c117c WD	113	* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
3d22d0b8	114	* The register base is currently at offset 0x600 from the memory base.
0c1c117c	115	----------------------------------------------------------------------/
6d0f6bcf	116	#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
0c1c117c	117
5c952cf0 WD	118	/*------------------------------------------------------------------------
	119	* DEBUG
	120	----------------------------------------------------------------------/
	121	#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
	122
	123	/*------------------------------------------------------------------------
	124	* TIMEBASE --
	125	*
	126	* The high res timer defaults to 1 msec. Since it includes the period
	127	* registers, we can slow it down to 10 msec using TMRCNT. If the default
	128	* period is acceptable, TMRCNT can be left undefined.
	129	----------------------------------------------------------------------/
6d0f6bcf JCPV	130	#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
	131	#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
	132	#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
	133	#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
	134	#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
5c952cf0 WD	135
	136	/*------------------------------------------------------------------------
	137	* STATUS LED -- Provides a simple blinking led. For Nios2 each board
	138	* must implement its own led routines -- leds are, after all,
	139	* board-specific, no?
	140	----------------------------------------------------------------------/
6d0f6bcf	141	#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
5c952cf0 WD	142	#define CONFIG_STATUS_LED /* Enable status driver */
	143
	144	#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
	145	#define STATUS_LED_STATE 1 /* Blinking */
6d0f6bcf	146	#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
5c952cf0 WD	147
	148	/*------------------------------------------------------------------------
	149	* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
	150	* and really doesn't need any additional clutter. So I choose the lazy
	151	* way out to avoid changes there -- define the base address to ensure
	152	* cache bypass so there's no need to monkey with inx/outx macros.
	153	----------------------------------------------------------------------/
3d22d0b8	154	#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
7194ab80 BW	155	#define CONFIG_NET_MULTI
7194ab80 BW	156	#define CONFIG_SMC91111 /* Using SMC91c111 */
5c952cf0 WD	157	#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
	158	#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
	159
	160	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	161	#define CONFIG_NETMASK 255.255.255.0
	162	#define CONFIG_IPADDR 192.168.2.21
	163	#define CONFIG_SERVERIP 192.168.2.16
	164
acf02697	165
a1aa0bb5 JL	166	/*
	167	* BOOTP options
	168	*/
	169	#define CONFIG_BOOTP_BOOTFILESIZE
	170	#define CONFIG_BOOTP_BOOTPATH
	171	#define CONFIG_BOOTP_GATEWAY
	172	#define CONFIG_BOOTP_HOSTNAME
	173
	174
acf02697 JL	175	/*
	176	* Command line configuration.
	177	*/
	178
	179	#define CONFIG_CMD_BDI
	180	#define CONFIG_CMD_DHCP
	181	#define CONFIG_CMD_ECHO
bdab39d3	182	#define CONFIG_CMD_SAVEENV
acf02697 JL	183	#define CONFIG_CMD_FLASH
	184	#define CONFIG_CMD_IMI
	185	#define CONFIG_CMD_IRQ
	186	#define CONFIG_CMD_LOADS
	187	#define CONFIG_CMD_LOADB
	188	#define CONFIG_CMD_MEMORY
	189	#define CONFIG_CMD_MISC
	190	#define CONFIG_CMD_NET
	191	#define CONFIG_CMD_PING
	192	#define CONFIG_CMD_RUN
	193	#define CONFIG_CMD_SAVES
	194
5c952cf0	195
0c1c117c WD	196	/*------------------------------------------------------------------------
	197	* COMPACT FLASH
	198	----------------------------------------------------------------------/
acf02697	199	#if defined(CONFIG_CMD_IDE)
0c1c117c	200	#define CONFIG_IDE_PREINIT /* Implement id_preinit */
6d0f6bcf JCPV	201	#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
	202	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
	203
	204	#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
	205	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
	206	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
	207	#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */
	208	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
	209	#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */
0c1c117c WD	210	#define CONFIG_DOS_PARTITION
	211
	212	/* Board-specific cf regs */
6d0f6bcf JCPV	213	#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */
	214	#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/
	215	#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
0c1c117c	216
acf02697	217	#endif
0c1c117c WD	218
	219	/*------------------------------------------------------------------------
	220	* JFFS2
	221	----------------------------------------------------------------------/
acf02697	222	#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf	223	#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */
0c1c117c WD	224	#endif
0c1c117c WD	225
5c952cf0 WD	226	/*------------------------------------------------------------------------
	227	* MISC
	228	----------------------------------------------------------------------/
6d0f6bcf JCPV	229	#define CONFIG_SYS_LONGHELP /* Provide extended help*/
	230	#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
	231	#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
	232	#define CONFIG_SYS_MAXARGS 16 /* Max command args */
	233	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
	234	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
	235	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
	236	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
	237	#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
	238
	239	#define CONFIG_SYS_HUSH_PARSER
	240	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
0c1c117c	241
5c952cf0	242	#endif /* __CONFIG_H */