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Coding Style cleanup: remove trailing white space
[J-u-boot.git] / board / netphone / netphone.c
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04a85b3b
WD		 1/*
2 * (C) Copyright 2000-2004
c26e454d 3 * Pantelis Antoniou, Intracom S.A., [email protected]
04a85b3b
WD		 4 * Wolfgang Denk, DENX Software Engineering, [email protected].
5 *
3765b3e7 6 * SPDX-License-Identifier: GPL-2.0+
04a85b3b
WD		 7 */
8
9/*
10 * Pantelis Antoniou, Intracom S.A., [email protected]
11 * U-Boot port on NetTA4 board
12 */
13
14#include <common.h>
15#include <miiphy.h>
16#include <sed156x.h>
5cf91d6b 17#include <status_led.h>
04a85b3b
WD		 18
19#include "mpc8xx.h"
20
21#ifdef CONFIG_HW_WATCHDOG
22#include <watchdog.h>
23#endif
24
63ff004c
MB		 25int fec8xx_miiphy_read(char *devname, unsigned char addr,
26 unsigned char reg, unsigned short *value);
27int fec8xx_miiphy_write(char *devname, unsigned char addr,
28 unsigned char reg, unsigned short value);
29
04a85b3b
WD		 30/****************************************************************/
31
32/* some sane bit macros */
33#define _BD(_b) (1U << (31-(_b)))
34#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
35
36#define _BW(_b) (1U << (15-(_b)))
37#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
38
39#define _BB(_b) (1U << (7-(_b)))
40#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
41
42#define _B(_b) _BD(_b)
43#define _BR(_l, _h) _BDR(_l, _h)
44
45/****************************************************************/
46
47/*
48 * Check Board Identity:
49 *
50 * Return 1 always.
51 */
52
53int checkboard(void)
54{
c26e454d 55 printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
04a85b3b
WD		 56 return (0);
57}
58
59/****************************************************************/
60
61#define _NOT_USED_ 0xFFFFFFFF
62
63/****************************************************************/
64
65#define CS_0000 0x00000000
66#define CS_0001 0x10000000
67#define CS_0010 0x20000000
68#define CS_0011 0x30000000
69#define CS_0100 0x40000000
70#define CS_0101 0x50000000
71#define CS_0110 0x60000000
72#define CS_0111 0x70000000
73#define CS_1000 0x80000000
74#define CS_1001 0x90000000
75#define CS_1010 0xA0000000
76#define CS_1011 0xB0000000
77#define CS_1100 0xC0000000
78#define CS_1101 0xD0000000
79#define CS_1110 0xE0000000
80#define CS_1111 0xF0000000
81
82#define BS_0000 0x00000000
83#define BS_0001 0x01000000
84#define BS_0010 0x02000000
85#define BS_0011 0x03000000
86#define BS_0100 0x04000000
87#define BS_0101 0x05000000
88#define BS_0110 0x06000000
89#define BS_0111 0x07000000
90#define BS_1000 0x08000000
91#define BS_1001 0x09000000
92#define BS_1010 0x0A000000
93#define BS_1011 0x0B000000
94#define BS_1100 0x0C000000
95#define BS_1101 0x0D000000
96#define BS_1110 0x0E000000
97#define BS_1111 0x0F000000
98
c26e454d
WD		 99#define GPL0_AAAA 0x00000000
100#define GPL0_AAA0 0x00200000
101#define GPL0_AAA1 0x00300000
102#define GPL0_000A 0x00800000
103#define GPL0_0000 0x00A00000
104#define GPL0_0001 0x00B00000
105#define GPL0_111A 0x00C00000
106#define GPL0_1110 0x00E00000
107#define GPL0_1111 0x00F00000
108
109#define GPL1_0000 0x00000000
110#define GPL1_0001 0x00040000
111#define GPL1_1110 0x00080000
112#define GPL1_1111 0x000C0000
113
114#define GPL2_0000 0x00000000
115#define GPL2_0001 0x00010000
116#define GPL2_1110 0x00020000
117#define GPL2_1111 0x00030000
118
119#define GPL3_0000 0x00000000
120#define GPL3_0001 0x00004000
121#define GPL3_1110 0x00008000
122#define GPL3_1111 0x0000C000
04a85b3b
WD		 123
124#define GPL4_0000 0x00000000
125#define GPL4_0001 0x00001000
126#define GPL4_1110 0x00002000
127#define GPL4_1111 0x00003000
128
129#define GPL5_0000 0x00000000
130#define GPL5_0001 0x00000400
131#define GPL5_1110 0x00000800
132#define GPL5_1111 0x00000C00
133#define LOOP 0x00000080
134
135#define EXEN 0x00000040
136
137#define AMX_COL 0x00000000
138#define AMX_ROW 0x00000020
139#define AMX_MAR 0x00000030
140
141#define NA 0x00000008
142
143#define UTA 0x00000004
144
145#define TODT 0x00000002
146
147#define LAST 0x00000001
148
c26e454d
WD		 149#define A10_AAAA GPL0_AAAA
150#define A10_AAA0 GPL0_AAA0
151#define A10_AAA1 GPL0_AAA1
152#define A10_000A GPL0_000A
153#define A10_0000 GPL0_0000
154#define A10_0001 GPL0_0001
155#define A10_111A GPL0_111A
156#define A10_1110 GPL0_1110
157#define A10_1111 GPL0_1111
158
159#define RAS_0000 GPL1_0000
160#define RAS_0001 GPL1_0001
161#define RAS_1110 GPL1_1110
162#define RAS_1111 GPL1_1111
163
164#define CAS_0000 GPL2_0000
165#define CAS_0001 GPL2_0001
166#define CAS_1110 GPL2_1110
167#define CAS_1111 GPL2_1111
168
169#define WE_0000 GPL3_0000
170#define WE_0001 GPL3_0001
171#define WE_1110 GPL3_1110
172#define WE_1111 GPL3_1111
173
04a85b3b
WD		 174/* #define CAS_LATENCY 3 */
175#define CAS_LATENCY 2
176
177const uint sdram_table[0x40] = {
178
179#if CAS_LATENCY == 3
180 /* RSS */
181 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
182 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
183 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
184 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
185 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
186 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
187 _NOT_USED_, _NOT_USED_,
188
189 /* RBS */
190 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
191 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
192 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
193 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
194 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
195 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
196 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
197 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
198 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
199 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
200
201 /* WSS */
202 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
203 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
204 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
205 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
206 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
207 _NOT_USED_, _NOT_USED_, _NOT_USED_,
208
209 /* WBS */
210 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
211 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
212 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
213 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
214 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
215 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
216 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
217 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
218 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
219 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
220 _NOT_USED_, _NOT_USED_, _NOT_USED_,
221#endif
222
223#if CAS_LATENCY == 2
224 /* RSS */
225 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
226 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
227 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
228 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
229 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
230 _NOT_USED_,
231 _NOT_USED_, _NOT_USED_,
232
233 /* RBS */
234 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
235 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
236 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
237 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
238 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
239 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
240 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
241 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
242 _NOT_USED_,
243 _NOT_USED_, _NOT_USED_, _NOT_USED_,
244 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
245
246 /* WSS */
247 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
248 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
249 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
250 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
251 _NOT_USED_,
252 _NOT_USED_, _NOT_USED_,
253 _NOT_USED_,
254
255 /* WBS */
256 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
257 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
258 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
259 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
260 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
261 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
262 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
263 _NOT_USED_,
264 _NOT_USED_, _NOT_USED_, _NOT_USED_,
265 _NOT_USED_, _NOT_USED_, _NOT_USED_,
266 _NOT_USED_, _NOT_USED_,
267
268#endif
269
270 /* UPT */
271 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
272 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
273 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
274 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
275 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
276 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
277 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
278 _NOT_USED_, _NOT_USED_,
279
280 /* EXC */
281 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
282 _NOT_USED_,
283
284 /* REG */
285 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
286 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
287};
288
c26e454d
WD		 289#if CONFIG_NETPHONE_VERSION == 2
290static const uint nandcs_table[0x40] = {
291 /* RSS */
292 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
293 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
294 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
295 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
296 CS_0000 | GPL4_0000 | GPL5_1111,
297 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
298 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
299 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
300
301 /* RBS */
302 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
303 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
304 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
305 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
306
307 /* WSS */
308 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
309 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
310 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
311 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
312 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
313 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
314 CS_0000 | GPL4_1111 | GPL5_1111,
315 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
316
317 /* WBS */
318 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
319 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
321 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
322
323 /* UPT */
324 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
325 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
326 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
327
328 /* EXC */
329 CS_0001 | LAST,
330 _NOT_USED_,
331
332 /* REG */
333 CS_1110 ,
334 CS_0001 | LAST,
335};
336#endif
337
04a85b3b
WD		 338/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
339/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
340#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
341
342/* 8 */
6d0f6bcf 343#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
04a85b3b
WD		 344 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
345 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
346
347void check_ram(unsigned int addr, unsigned int size)
348{
349 unsigned int i, j, v, vv;
350 volatile unsigned int *p;
351 unsigned int pv;
352
353 p = (unsigned int *)addr;
354 pv = (unsigned int)p;
355 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
356 *p++ = pv;
357
358 p = (unsigned int *)addr;
359 for (i = 0; i < size / sizeof(unsigned int); i++) {
360 v = (unsigned int)p;
361 vv = *p;
362 if (vv != v) {
363 printf("%p: read %08x instead of %08x\n", p, vv, v);
364 hang();
365 }
366 p++;
367 }
368
369 for (j = 0; j < 5; j++) {
370 switch (j) {
371 case 0: v = 0x00000000; break;
372 case 1: v = 0xffffffff; break;
373 case 2: v = 0x55555555; break;
374 case 3: v = 0xaaaaaaaa; break;
375 default:v = 0xdeadbeef; break;
376 }
377 p = (unsigned int *)addr;
378 for (i = 0; i < size / sizeof(unsigned int); i++) {
379 *p = v;
380 vv = *p;
381 if (vv != v) {
382 printf("%p: read %08x instead of %08x\n", p, vv, v);
383 hang();
384 }
385 *p = ~v;
386 p++;
387 }
388 }
389}
390
9973e3c6 391phys_size_t initdram(int board_type)
04a85b3b 392{
6d0f6bcf 393 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
04a85b3b
WD		 394 volatile memctl8xx_t *memctl = &immap->im_memctl;
395 long int size;
396
c26e454d 397 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
04a85b3b
WD		 398
399 /*
400 * Preliminary prescaler for refresh
401 */
402 memctl->memc_mptpr = MPTPR_PTP_DIV8;
403
404 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
405
406 /*
407 * Map controller bank 3 to the SDRAM bank at preliminary address.
408 */
6d0f6bcf
JCPV		 409 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
410 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
04a85b3b 411
6d0f6bcf 412 memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
04a85b3b
WD		 413
414 udelay(200);
415
416 /* perform SDRAM initialisation sequence */
417 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
418 udelay(1);
419
420 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
421 udelay(1);
422
423 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
424 udelay(1);
425
426 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
427
428 udelay(10000);
429
430 {
431 u32 d1, d2;
432
433 d1 = 0xAA55AA55;
434 *(volatile u32 *)0 = d1;
435 d2 = *(volatile u32 *)0;
436 if (d1 != d2) {
437 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
438 hang();
439 }
440
441 d1 = 0x55AA55AA;
442 *(volatile u32 *)0 = d1;
443 d2 = *(volatile u32 *)0;
444 if (d1 != d2) {
445 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
446 hang();
447 }
448 }
449
450 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
451
04a85b3b
WD		 452 if (size == 0) {
453 printf("SIZE is zero: LOOP on 0\n");
454 for (;;) {
455 *(volatile u32 *)0 = 0;
456 (void)*(volatile u32 *)0;
457 }
458 }
459
460 return size;
461}
462
463/* ------------------------------------------------------------------------- */
464
465void reset_phys(void)
466{
467 int phyno;
468 unsigned short v;
469
470 udelay(10000);
471 /* reset the damn phys */
472 mii_init();
473
474 for (phyno = 0; phyno < 32; ++phyno) {
8ef583a0 475 fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
04a85b3b
WD		 476 if (v == 0xFFFF)
477 continue;
8ef583a0 478 fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
04a85b3b 479 udelay(10000);
8ef583a0
MF		 480 fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
481 BMCR_RESET | BMCR_ANENABLE);
04a85b3b
WD		 482 udelay(10000);
483 }
484}
485
486/* ------------------------------------------------------------------------- */
487
488/* GP = general purpose, SP = special purpose (on chip peripheral) */
489
490/* bits that can have a special purpose or can be configured as inputs/outputs */
491#define PA_GP_INMASK 0
492#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
493#define PA_SP_MASK 0
494#define PA_ODR_VAL 0
495#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
496#define PA_SP_DIRVAL 0
497
498#define PB_GP_INMASK _B(28)
499#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
500#define PB_SP_MASK (_BR(22, 25))
501#define PB_ODR_VAL 0
502#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
503#define PB_SP_DIRVAL 0
504
c26e454d 505#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 506#define PC_GP_INMASK _BW(12)
507#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
c26e454d
WD		 508#elif CONFIG_NETPHONE_VERSION == 2
509#define PC_GP_INMASK (_BW(13) | _BW(15))
510#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
511#endif
04a85b3b
WD		 512#define PC_SP_MASK 0
513#define PC_SOVAL 0
514#define PC_INTVAL 0
515#define PC_GP_OUTVAL (_BW(10) | _BW(11))
516#define PC_SP_DIRVAL 0
517
c26e454d 518#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 519#define PE_GP_INMASK _B(31)
520#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
c26e454d
WD		 521#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
522#elif CONFIG_NETPHONE_VERSION == 2
523#define PE_GP_INMASK _BR(28, 31)
524#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
525#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
526#endif
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WD		 527#define PE_SP_MASK 0
528#define PE_ODR_VAL 0
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WD		 529#define PE_SP_DIRVAL 0
530
531int board_early_init_f(void)
532{
6d0f6bcf 533 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
04a85b3b
WD		 534 volatile iop8xx_t *ioport = &immap->im_ioport;
535 volatile cpm8xx_t *cpm = &immap->im_cpm;
536 volatile memctl8xx_t *memctl = &immap->im_memctl;
537
538 /* NAND chip select */
c26e454d 539#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 540 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
541 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
c26e454d
WD		 542#elif CONFIG_NETPHONE_VERSION == 2
543 upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
544 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
545 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
546 memctl->memc_mamr = 0; /* all clear */
547#endif
04a85b3b
WD		 548
549 /* DSP chip select */
550 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
551 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
552
c26e454d
WD		 553#if CONFIG_NETPHONE_VERSION == 1
554 memctl->memc_br4 &= ~BR_V;
555#endif
04a85b3b
WD		 556 memctl->memc_br5 &= ~BR_V;
557 memctl->memc_br6 &= ~BR_V;
558 memctl->memc_br7 &= ~BR_V;
559
560 ioport->iop_padat = PA_GP_OUTVAL;
561 ioport->iop_paodr = PA_ODR_VAL;
562 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
563 ioport->iop_papar = PA_SP_MASK;
564
565 cpm->cp_pbdat = PB_GP_OUTVAL;
566 cpm->cp_pbodr = PB_ODR_VAL;
567 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
568 cpm->cp_pbpar = PB_SP_MASK;
569
570 ioport->iop_pcdat = PC_GP_OUTVAL;
571 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
572 ioport->iop_pcso = PC_SOVAL;
573 ioport->iop_pcint = PC_INTVAL;
574 ioport->iop_pcpar = PC_SP_MASK;
575
576 cpm->cp_pedat = PE_GP_OUTVAL;
577 cpm->cp_peodr = PE_ODR_VAL;
578 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
579 cpm->cp_pepar = PE_SP_MASK;
580
581 return 0;
582}
583
04a85b3b
WD		 584#ifdef CONFIG_HW_WATCHDOG
585
586void hw_watchdog_reset(void)
587{
588 /* XXX add here the really funky stuff */
589}
590
591#endif
592
593#ifdef CONFIG_SHOW_ACTIVITY
594
595static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
596
6d0f6bcf 597/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
04a85b3b
WD		 598void board_show_activity(ulong timestamp)
599{
600 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
601 --left_to_poll;
602}
603
604extern void phone_console_do_poll(void);
605
606static void do_poll(void)
607{
608 unsigned int base;
609
610 while (left_to_poll <= 0) {
611 phone_console_do_poll();
612 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
613 do {
614 left_to_poll = base;
615 } while (base != left_to_poll);
616 }
617}
618
619/* called when looping */
620void show_activity(int arg)
621{
622 do_poll();
623}
624
625#endif
626
6d0f6bcf 627#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
04a85b3b
WD		 628int overwrite_console(void)
629{
630 /* printf("overwrite_console called\n"); */
631 return 0;
632}
633#endif
634
635extern int drv_phone_init(void);
636extern int drv_phone_use_me(void);
5cf91d6b 637extern int drv_phone_is_idle(void);
04a85b3b
WD		 638
639int misc_init_r(void)
640{
641 return drv_phone_init();
642}
643
644int last_stage_init(void)
645{
646 int i;
647
c26e454d
WD		 648#if CONFIG_NETPHONE_VERSION == 2
649 /* assert peripheral reset */
6d0f6bcf 650 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
c26e454d
WD		 651 for (i = 0; i < 10; i++)
652 udelay(1000);
6d0f6bcf 653 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12);
c26e454d 654#endif
04a85b3b
WD		 655 reset_phys();
656
657 /* check in order to enable the local console */
658 left_to_poll = PHONE_CONSOLE_POLL_HZ;
6d0f6bcf 659 i = CONFIG_SYS_HZ * 2;
04a85b3b
WD		 660 while (i > 0) {
661
53677ef1 662 if (tstc()) {
04a85b3b
WD		 663 getc();
664 break;
665 }
666
667 do_poll();
668
669 if (drv_phone_use_me()) {
5cf91d6b
WD		 670 status_led_set(0, STATUS_LED_ON);
671 while (!drv_phone_is_idle()) {
672 do_poll();
6d0f6bcf 673 udelay(1000000 / CONFIG_SYS_HZ);
5cf91d6b
WD		 674 }
675
04a85b3b
WD		 676 console_assign(stdin, "phone");
677 console_assign(stdout, "phone");
678 console_assign(stderr, "phone");
679 setenv("bootdelay", "-1");
680 break;
681 }
682
6d0f6bcf 683 udelay(1000000 / CONFIG_SYS_HZ);
04a85b3b
WD		 684 i--;
685 left_to_poll--;
686 }
687 left_to_poll = PHONE_CONSOLE_POLL_HZ;
688
689 return 0;
690}
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